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Relevant bibliographies by topics / Logic gate circuits][Circuit technology

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Journal articles

Academic literature on the topic 'Logic gate circuits][Circuit technology'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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Journal articles on the topic "Logic gate circuits][Circuit technology"

1

Jiang, Jin Tao, Yu Zhang, and Jian Ping Hu. "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits." Advanced Materials Research 159 (December 2010): 155–61. http://dx.doi.org/10.4028/www.scientific.net/amr.159.155.

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With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65n

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2

Naveenkumar, Majety. "Novel Design of Reversible MUX and DEMUX using GDI Techinque." International Journal of Advances in Applied Sciences 4, no. 3 (2015): 103. http://dx.doi.org/10.11591/ijaas.v4.i3.pp103-108.

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Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type

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3

Sofeoul-Al-Mamun, Md, Mohammad Badrul Alam Miah, and Fuyad Al Masud. "A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology." European Scientific Journal, ESJ 13, no. 15 (2017): 254. http://dx.doi.org/10.19044/esj.2017.v13n15p254.

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In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for

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4

Galadima, B. Y., G. S. M. Galadanci, A. Tijjani, and M. Ibrahim. "A review on reversible logic gates." Bayero Journal of Pure and Applied Sciences 12, no. 1 (2020): 242–50. http://dx.doi.org/10.4314/bajopas.v12i1.38s.

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In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some

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5

Bobba, Ramyabanu, and Pooja Illa. "XOR Based Carry Select Adder for Area and Delay." International Journal of Innovative Science and Research Technology 5, no. 6 (2020): 1615–21. http://dx.doi.org/10.38124/ijisrt20jun1117.

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Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and

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6

Bansal, Deepika, Bal Chand Nagar, Brahamdeo Prasad Singh, and Ajay Kumar. "Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs." International Journal of Sensors, Wireless Communications and Control 10, no. 1 (2020): 55–62. http://dx.doi.org/10.2174/2210327909666190207163639.

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Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configur

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7

Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate." International Journal of Business Data Communications and Networking 11, no. 1 (2015): 36–49. http://dx.doi.org/10.4018/ijbdcn.2015010104.

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In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper

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8

Mohammadi, Hossein, and Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate." Journal of Circuits, Systems and Computers 27, no. 14 (2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.

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Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different leng

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9

Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.

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This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential cir

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10

Bansal, Deepika, Bal Chand Nagar, Brahamdeo Prasad Singh, and Ajay Kumar. "Improved Domino Logic Circuits and its Application in Wide Fan-In OR Gates." Micro and Nanosystems 12, no. 1 (2020): 58–67. http://dx.doi.org/10.2174/1876402911666190716161631.

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Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability. Objective: In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino

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