To see the other types of publications on this topic, follow the link: Logic gate circuits][Circuit technology.
Journal articles on the topic 'Logic gate circuits][Circuit technology'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 journal articles for your research on the topic 'Logic gate circuits][Circuit technology.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.
1
Jiang, Jin Tao, Yu Zhang, and Jian Ping Hu. "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits." Advanced Materials Research 159 (December 2010): 155–61. http://dx.doi.org/10.4028/www.scientific.net/amr.159.155.
Full textAbstract:
With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.
2
Naveenkumar, Majety. "Novel Design of Reversible MUX and DEMUX using GDI Techinque." International Journal of Advances in Applied Sciences 4, no. 3 (2015): 103. http://dx.doi.org/10.11591/ijaas.v4.i3.pp103-108.
Full textAbstract:
Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type of Reversible gate i.e. Fredkin Gate (FRG) and Not Gate. The simulations are done in H-Spice using 90nm technology.
3
Sofeoul-Al-Mamun, Md, Mohammad Badrul Alam Miah, and Fuyad Al Masud. "A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology." European Scientific Journal, ESJ 13, no. 15 (2017): 254. http://dx.doi.org/10.19044/esj.2017.v13n15p254.
Full textAbstract:
In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for future Integrated Circuits (ICs). A quantum dot cellular automaton complex gate is composed from simple 3-input majority gate. In this paper, a 8-3 encoder circuit is proposed based on QCA logic gates: the 4-input Majority Voter (MV) OR gate. This 7-input gate can be configured into many useful gate structures such as a 4-input AND gate, a 4-input OR gate, 2-input AND and 2-input OR gates, 2-input complex gates, multi-input complex gates. The proposed circuit has a promising future in the area of nano-computing information processing system and can be stimulated with higher digital applications in QCA.
4
Galadima, B. Y., G. S. M. Galadanci, A. Tijjani, and M. Ibrahim. "A review on reversible logic gates." Bayero Journal of Pure and Applied Sciences 12, no. 1 (2020): 242–50. http://dx.doi.org/10.4314/bajopas.v12i1.38s.
Full textAbstract:
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit. 
 Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,
5
Bobba, Ramyabanu, and Pooja Illa. "XOR Based Carry Select Adder for Area and Delay." International Journal of Innovative Science and Research Technology 5, no. 6 (2020): 1615–21. http://dx.doi.org/10.38124/ijisrt20jun1117.
Full textAbstract:
Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and complexity minimization. The proposed 16-bit carry select adder provides better results compared to the conventional 16-bit carry select adder with Area and delay.
6
Bansal, Deepika, Bal Chand Nagar, Brahamdeo Prasad Singh, and Ajay Kumar. "Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs." International Journal of Sensors, Wireless Communications and Control 10, no. 1 (2020): 55–62. http://dx.doi.org/10.2174/2210327909666190207163639.
Full textAbstract:
Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.
7
Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate." International Journal of Business Data Communications and Networking 11, no. 1 (2015): 36–49. http://dx.doi.org/10.4018/ijbdcn.2015010104.
Full textAbstract:
In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.
8
Mohammadi, Hossein, and Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate." Journal of Circuits, Systems and Computers 27, no. 14 (2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.
Full textAbstract:
Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.
9
Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.
Full textAbstract:
This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.
10
Bansal, Deepika, Bal Chand Nagar, Brahamdeo Prasad Singh, and Ajay Kumar. "Improved Domino Logic Circuits and its Application in Wide Fan-In OR Gates." Micro and Nanosystems 12, no. 1 (2020): 58–67. http://dx.doi.org/10.2174/1876402911666190716161631.
Full textAbstract:
Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability. Objective: In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino circuits. Methods: The proposed domino circuits are tested and verified using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by Stanford University. Conclusion: The power delay product of proposed DL-I and DL-II improves by 32.59 % and 40.98 % for 8-input OR gate as compared to standard logic respectively at the clock frequency of 500 MHz. The simulation results validate that the proposed circuits improve the performance of pseudo domino logic with respect to leakage power consumption, delay and unity noise gain.
11
Waheed, Sajjad, Sharmin Aktar, and Ali Newaz Bahar. "A Novel Design and Implementation of New Double Feynman and Six-correction logic (DFSCL) gates in Quantum-dot Cellular Automata (QCA)." European Scientific Journal, ESJ 13, no. 15 (2017): 265. http://dx.doi.org/10.19044/esj.2017.v13n15p265.
Full textAbstract:
In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.
12
Kannan, R., and K. Vidhya. "Design of Combinational Circuits Using Reversible Decoder in Tanner Tools." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1743–51. http://dx.doi.org/10.1166/jctn.2020.8436.
Full textAbstract:
Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.
13
Gupta, T. K., A. K. Pandey, and O. P. Meena. "Analysis and design of lector-based dual-Vt domino logic with reduced leakage current." Circuit World 43, no. 3 (2017): 97–104. http://dx.doi.org/10.1108/cw-03-2017-0013.
Full textAbstract:
Purpose This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current. Design/methodology/approach In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits. Findings The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits. Originality/value The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.
14
Thompson, R. F., D. T. Clark, A. E. Murphy, et al. "High Temperature Silicon Carbide CMOS Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (2011): 000115–19. http://dx.doi.org/10.4071/hiten-paper5-dclark.
Full textAbstract:
The wide band-gap of Silicon Carbide makes it a material suitable for IC's [1] operating up to 450°C. The maximum operating temperature achieved will depend on the transistor technology selected, interconnect metallisation and device packaging. This paper describes transistor and circuit results achieved in SiC CMOS technology, where the major issue addressed is the gate dielectric performance. N and p-channel MOSFET structures have been demonstrated operating at temperatures up to 400°C Test circuits including simple logic cells, ring oscillators, operational amplifiers and gate drive circuits have been fabricated and the characteristics of ring oscillators are presented here. Floating capacitor structures have also been fabricated for use in future analogue and mixed signal circuits. This technology will be initially applied in applications including signal conditioning for sensors and control of SiC based power switching devices, where the high temperature capability will match that of the SiC power devices which are now becoming commercially available.
15
K. Babulu, T. Subhashini, M. Kamaraju,. "AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (2021): 159–63. http://dx.doi.org/10.17762/itii.v9i1.115.
Full textAbstract:
Low power is essential in today’s technology. It is most significant with high speed, small size and stability. So, power reduction is most important in modern technology using VLSI design techniques. Today most of the market necessities require low power, long run time and market which also deserve small size and high speed. In this paper several logic circuits DFF with 5 transistors and sub tractor circuit using powerless XOR gate and Groundless XNOR gates are implemented. In the proposed DFF, the area can be decreased by 62% & substarctor circuit, area decreased by 80% and power consumption of DFF and subtractor circuit are 15.4µW and 13.76µW respectively, but these are very less as compared to existing techniques.
16
KANCHANA BHAASKARAN, V. S., and J. P. RAINA. "PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES." Journal of Circuits, Systems and Computers 21, no. 05 (2012): 1250045. http://dx.doi.org/10.1142/s0218126612500454.
Full textAbstract:
The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.
17
Kalagadda, B., N. Muthyala, and K. K. Korlapati. "Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques." Journal of Engineering Research [TJER] 14, no. 1 (2017): 74. http://dx.doi.org/10.24200/tjer.vol14iss1pp74-84.
Full textAbstract:
Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.
18
Dong, Zhekang, Donglian Qi, Yufei He, Zhao Xu, Xiaofang Hu, and Shukai Duan. "Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation." International Journal of Bifurcation and Chaos 28, no. 12 (2018): 1850149. http://dx.doi.org/10.1142/s0218127418501493.
Full textAbstract:
Memristor is a novel passive electronic element with resistance-switching dynamics. Due to the threshold property and the variable conductivity of the memristive element, its composite circuits are promising for the implementation of logic operations. In this paper, a flexible logic circuit based on the threshold-type memristor and the mature complementary metal-oxide-semiconductor (CMOS) technology is designed for the realization of Boolean logic operations. Specifically, the proposed method is able to perform the NAND, AND, OR, and NOR gate operations through two phases, i.e. the writing operation and the reading operation. In such implementation, the total delay is very small especially for time-sequence inputs. Furthermore, for existing memristor-based logic implementation, a contrastive analysis with relevant computer simulations is carried out. The experimental results indicate that the proposed method is capable of realizing all basic Boolean logic operations, and some more complicated cascaded logic operations with more compact circuit structures, higher efficiency, and lower operating cost.
19
Bentini, Andrea, Benedetto Pasciuto, Walter Ciccognani, Ernesto Limiti, Antonio Nanni, and Paolo Romanini. "Design and Realization of GaAs Digital Circuit for Mixed Signal MMIC Implementation in AESA Applications." International Journal of Microwave Science and Technology 2011 (January 15, 2011): 1–11. http://dx.doi.org/10.1155/2011/387137.
Full textAbstract:
A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.
20
DAS, KUNAL, and DEBASHIS DE. "A STUDY ON DIVERSE NANOSTRUCTURE FOR IMPLEMENTING LOGIC GATE DESIGN FOR QCA." International Journal of Nanoscience 10, no. 01n02 (2011): 263–69. http://dx.doi.org/10.1142/s0219581x11007892.
Full textAbstract:
Quantum dot cellular automata (QCA) define the nanostructure of basic computer. It is used as an alternative for designing high-speed computer over CMOS technology. The basic logic in QCA is the logic state that does not measure with voltage level; rather it measures the polarity of electrons in cell. The Majority Voter (MV) is first introduced to design the logic circuits, but only using MV, designing complex logic circuit became inefficient. Many proposals had been made for designing QCA logic gate. In this paper we focus on different useful nanostructures, reduced size and efficient design of Nand–Nor Inverter (NNI), 3 × 3 tile structures for implementing NNI, And–Or Logic, and AOI also present logic synthesis using proposed gates. We analyze QCA defect on proposed gates and describe its permissible defect tolerance. In QCA we describe application for implementing standard functions using proposed structures in this paper and describe effective area of proposed structures.
21
Pandey, Amit Kumar, Tarun Kumar Gupta, and Pawan Kumar Verma. "Sleep signal controlled footless domino circuit for low leakage current." Circuit World 44, no. 2 (2018): 87–98. http://dx.doi.org/10.1108/cw-06-2017-0030.
Full textAbstract:
Purpose This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents. Design/methodology/approach In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state. Findings The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits. Originality/value The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.
22
Dehghan, Bahram. "Design Multipurpose Circuits with Minimum Garbage Outputs Using CMVMIN Gate." Chinese Journal of Engineering 2014 (February 26, 2014): 1–7. http://dx.doi.org/10.1155/2014/532121.
Full textAbstract:
Quantum-dot cellular automata (QCA) suggest an emerging computing paradigm for nanotechnology. The QCA offers novel approach in electronics for information processing and communication. QCA have recently become the focus of interest in the field of low power nanocomputing and nanotechnology. The fundamental logic elements of this technology are the majority voter (MV) and the inverter (INV). This paper presents a novel design with less garbage output and minimum quantum cost in nanotechnology. In the paper we show how to create multipurpose reversible gates. By development of suitable gates in logic circuits as an example, we can combine MFA and HS in one design using CMVMIN gate. We offer CMVMIN gate implementations to be used in multipurpose circuit. We can produce concurrent half adder/subtractor and one bit comparator in one design using reversible logic gates and CMVMIN gates. Also, a 2×4 decoder from recent architecture has been shown independently. We investigate the result of the proposed design using truth table. A significant improvement in quality of the calculated parameters and variety of required outputs has been achieved.
23
Hatefinasab, Seyedehsomayeh. "Carbon Nanotube Field Effect Transistor-Based Hybrid Full Adders Using Gate-Diffusion Input Structure." Journal of Nanoelectronics and Optoelectronics 14, no. 11 (2019): 1512–22. http://dx.doi.org/10.1166/jno.2019.2661.
Full textAbstract:
Scaling down the size of transistor in the nanoscale reduces the power supply voltage, as a result, the design of high-performance nano-circuit at low voltage has been considered. Most of digital circuits are composed of different components which determine the performance of the entire digital circuits. With the improvement of these components, the digital circuits can be optimized. One of these components is full adder for which various structures have been proposed to improve its performance, among them the two novel full adder structures are based on Gate-Diffusion Input (GDI) structure and half-classical XOR/XNOR logic (SEMI XOR/XNOR) modules. In this paper, Carbon Nanotube Field Effect Transistor (CNTFET)-based low power full adders by using SEMI XOR logic style and GDI structure are presented. Due to the incomparable thermal and mechanical properties of the CNTFET, it can be the first alternative to substitute the metal oxide field effect transistors (MOSFET). The digital circuits have the better performance based on CNTFET. Therefore, the three proposed full adders in this paper are designed based on CNTFET technology with many merits, such as low power dissipation, less energy delay product (EDP), and high speed at various supply voltages, frequencies, temperatures, load capacitors, and the number of tubes. Moreover, these proposed full adders occupy the minimum area consumption and have better performance in comparison with previous standard full adders. All simulations are done by using the Synopsys HSPICE simulator in 32 nm-CNTFET technology and layout of all full adder circuits are presented on Electric.
24
Zgheib, Grace, and Iyad Ouaiss. "Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations." Journal of Circuits, Systems and Computers 24, no. 03 (2015): 1550039. http://dx.doi.org/10.1142/s0218126615500395.
Full textAbstract:
In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.
25
SENTHILPARI, C., K. DIWAKAR, and AJAY KUMAR SINGH. "LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 581–96. http://dx.doi.org/10.1142/s0218126609005277.
Full textAbstract:
As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.
26
Bhuvana, B. P., and V. S. Kanchana Bhaaskaran. "Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures." Journal of Circuits, Systems and Computers 29, no. 01 (2019): 2050016. http://dx.doi.org/10.1142/s0218126620500164.
Full textAbstract:
This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.
27
Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.
Full textAbstract:
In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.
28
K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.
Full textAbstract:
In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.
29
Singh, Rupali, and Devendra Kumar Sharma. "QCA-Based RAM Design Using a Resilient Reversible Gate with Improved Performance." Journal of Circuits, Systems and Computers 29, no. 13 (2020): 2050209. http://dx.doi.org/10.1142/s0218126620502096.
Full textAbstract:
Reversible logic and Quantum dot cellular automata are the prospective pillars of quantum computing. These paradigms can potentially reduce the size and power of the future chips while simultaneously maintaining the high speed. RAM cell is a crucial component of computing devices. Design of a RAM cell using a blend of reversible logic and QCA technology will surpass the limitations of conventional RAM structure. This motivates us to explore the design of a RAM cell using reversible logic in QCA framework. The performance of a reversible circuit can be improved by utilizing a resilient reversible gate. This paper presents the design of QCA-based reversible RAM cell using an efficient, fault-tolerant and low power reversible gate. Initially, a novel reversible gate is proposed and implemented in QCA. The QCA layout of the proposed reversible gate is designed using a unique multiplexer circuit. Further, a comprehensive analysis of the gate is carried out for standard Boolean functions, cost function and power dissipation and it has been found that the proposed gate is 75.43% more cost-effective and 58.54% more energy-efficient than the existing reversible gates. To prove the inherent testability of the proposed gate, its rigorous testing is carried out against various faults and the proposed gate is found to be 69.2% fault-tolerant. For all the performance parameters, the proposed gate has performed considerably better than the existing ones. Furthermore, the proposed gate is explicitly used for designing reversible D latch and RAM cell, which are crucial modules of sequential logic circuits. The proposed latch is 45.4% more cost effective than the formerly reported D latch. The design of QCA-based RAM cell using reversible logic is novel and not reported earlier in the literature.
30
Weng, Ming Hung, Muhammad I. Idris, S. Wright, et al. "First Demonstration of High Temperature SiC CMOS Gate Driver in Bridge Leg for Hybrid Power Module Application." Materials Science Forum 924 (June 2018): 854–57. http://dx.doi.org/10.4028/www.scientific.net/msf.924.854.
Full textAbstract:
A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond.
31
Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.
Full textAbstract:
Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
32
Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.
Full textAbstract:
In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
33
Misra, Neeraj Kumar, Bibhash Sen, Subodh Wairya, and Bandan Bhoi. "Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750145. http://dx.doi.org/10.1142/s0218126617501456.
Full textAbstract:
In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the [Formula: see text]-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm2 area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.
34
O., Mohammad Zulkarnain, Amar Faiz Z.A., Syahrul Hisham M., Nur Dalila K.A., and N. Ismail. "E-Logic Trainer Kit : Development of an Electronic Educational Simulator and Quiz Kit for Logic Gate Combinational Circuit by using Arduino as Application." International Journal of Online and Biomedical Engineering (iJOE) 15, no. 14 (2019): 67. http://dx.doi.org/10.3991/ijoe.v15i14.11410.
Full textAbstract:
To supplement conventional teaching methods, use of new technology have recently being adapted in the current education system. Such examples are implementing simulators and quiz kits in a classroom session to assist teachers in providing standardized evaluation or practical and more direct examples of concepts that are being taught. Additionally, the well-known issue of attracting student interest in a so-called uninteresting conventional lecture may be solved by using this technological method. The objective of this works to provide methods on developing a prototype training kit (named as e-Logic trainer kit or e-LTK) which comprises of an electronic simulator and quiz assessment module to evaluate subject knowledge on logic gates. The e-LTK is developed by using Arduino Mega 2560 as the base microcontroller, equipped with keypad and display module as the user input/output interface. The quiz assessment module contained in the prototype also allows conversion of inputs by combinatorial logic circuits into output in the form of timing diagram. This equipment enables electrical engineering students to simulate several combinations of logic circuit, reinforcing the understanding of logic circuit operation. The effectiveness of using this prototype in educational settings have been evaluated through a survey on students and instructors at Faculty of Technology in Engineering (FTK) in Universiti Teknikal Malaysia Melaka (UTeM). Response has been positive, with 60% of the correspondence has shown positive feedbacks, indicating the usefulness of the prototype kit.
35
TIEN, P. K. "PROPAGATION DELAY IN HIGH SPEED SILICON BIPOLAR AND GaAs HBT DIGITAL CIRCUITS." International Journal of High Speed Electronics and Systems 01, no. 01 (1990): 101–24. http://dx.doi.org/10.1142/s012915649000006x.
Full textAbstract:
The needs for multi-gigabits/second digital electronics in advanced lightwave systems have motivated R & D for the next generation of high speed bipolar technology. The speed of the digital circuit may be estimated from the propagation delay of the logic gate. We discuss physics of the delay and show that it is fundamentally limited by the time needed for turning on (off) a transistor and by the time for charging (discharging) of capacitances in the circuit. We present a large-signal theory based on a charge-control model for the calculation of these limits. The results obtained for emitter coupled logic and current mode logic are used to analyze current technologies of silicon bipolar and GaAs HBTs.
36
WASHIO, KATSUYOSHI. "SELF-ALIGNED Si BJT/SiGe HBT TECHNOLOGY AND ITS APPLICATION TO HIGH-SPEED CIRCUITS." International Journal of High Speed Electronics and Systems 11, no. 01 (2001): 77–114. http://dx.doi.org/10.1142/s0129156401000794.
Full textAbstract:
In a Si bipolar transistor (BJT) and a SiGe heterojunction bipolar transistor (HBT), self-aligned structures help to improve high-speed and high-frequency characteristics. These structures are used to reduce parasitic capacitance and resistance, and thus maximize the transistor's intrinsic performance. In addition to generally used process technology, selective metal deposition to form electrodes and selective epitaxial growth of Si/SiGe multilayers are applied in the fabrication process. To improve the intrinsic speed, the cutoff frequency, a shallow diffusion process for Si BJTs and a graded-Ge profile SiGe-base layer for SiGe HBTs are used. These also enable a high maximum oscillation frequency and a small gate delay in the emitter-coupled logic through the synergistic effect of the self-aligned structure. Both high-speed digital circuits — frequency dividers up to millimeter-wave bands and a multiplexer/demultiplexer for optical-fiber-links — and high-frequency analog circuits for optical-fiber-links — a preamplifier, an automatic gain control amplifier. a limiting amplifier, and a decision circuit — have been implemented by applying the self-aligned Si BJTs and/or SiGe HBTs.
37
Hu, Jian Ping, Li Fang Ye, and Li Su. "A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials." Applied Mechanics and Materials 29-32 (August 2010): 1930–36. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1930.
Full textAbstract:
Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.
38
Irmansyah, Muhammad. "GERBANG LOGIKA BERBASIS PROGRAMMABLE LOGIC DEVICE (PLD)." Elektron : Jurnal Ilmiah 1, no. 1 (2009): 75–81. http://dx.doi.org/10.30630/eji.1.1.12.
Full textAbstract:
In middle 1990, electronics industry had evolution in personal Computer, telephone cellular and high speed data communication equipment. To follow this development, electronics companies have designed and produce new product. One of these innovations is Programmable Logic Devices (PLD) technology. It is a technology to change function of IC digital logic using programming. Many of Programmable Logic Device (PLD) can be used to programming logic using single chip of integrated circuit (IC). Programmable Logic Devices (PLD) technology is applied using IC PAL 22V10 to design basic logic gate AND, OR, NOT and combinational logic gate NAND and NOR.
39
SHRIVASTAVA, ANUJ KUMAR, and SHYAM AKASHE. "DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY." International Journal of Nanoscience 12, no. 06 (2013): 1350042. http://dx.doi.org/10.1142/s0219581x13500427.
Full textAbstract:
Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.
40
Itoh, Kiyoo. "Trends in low-voltage embedded-RAM technology." Facta universitatis - series: Electronics and Energetics 15, no. 1 (2002): 1–12. http://dx.doi.org/10.2298/fuee0201001i.
Full textAbstract:
First, trends in the gate-oxide thickness of MOSFET for DRAM and MPU are discussed to clarify the strong need for low-voltage operation of embedded RAMs. Then, modern peripheral logic circuits for reducing leakage currents and DRAM/SRAM cells to cope with the ever-decreasing signal charges are described. Finally, needs for developments of subthreshold-current reduction circuits for use in active mode, memory-rich SoC architectures, and gain cells and non-volatile cells are emphasized.
41
Huang, Chun Lei, Lun Yao Wang, Hao Liang, and Yin Shui Xia. "A Design of Three-Input Low-Power AND/XOR Complex Gate." Applied Mechanics and Materials 687-691 (November 2014): 3149–52. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3149.
Full textAbstract:
For the deficiencies of the existing complex circuit designs, a novel transistor-level three-input AND/XOR logic complex gate with simple and symmetry structure is proposed. HPSICE simulation results show that the proposed circuit has correct operation. Further, in 55nm process CMOS technology, compared with the conventional cell-based cascaded AND/XOR circuit at different operation frequencies, the proposed circuit has a significant improvement at delay, power consumption and power delay product (PDP).
42
Lanni, Luigia, Bengt Gunnar Malm, Mikael Östling, and Carl Mikael Zetterling. "ECL-Based SiC Logic Circuits for Extreme Temperatures." Materials Science Forum 821-823 (June 2015): 910–13. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.910.
Full textAbstract:
Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.
43
V.Naga Lakshmi, E., and Dr N.Siva Sankara Reddy. "Estimation of Power for Reversible Subtractors." International Journal of Engineering & Technology 7, no. 4.5 (2018): 102. http://dx.doi.org/10.14419/ijet.v7i4.5.20021.
Full textAbstract:
In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG). Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor. Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.
44
Garg, Sandeep, and Tarun K. Gupta. "A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology." Journal of Circuits, Systems and Computers 28, no. 10 (2019): 1950165. http://dx.doi.org/10.1142/s0218126619501652.
Full textAbstract:
In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.
45
Reed, Lynn. "A 250°C ASIC Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (2013): 000134–38. http://dx.doi.org/10.4071/hiten-ta16.
Full textAbstract:
Tekmos has developed a 250°C ASIC technology that uses the X-Fab XI10 SOI process. A gate array architecture was chosen to allow reduced mask costs and quicker manufacturing cycle times. The design of the technology includes first determining the optimum routing grid and then designing of the basic gate array transistors. The “A” style transistor was chosen over the “H” style to create stronger transistors. The choice of the transistor in turn sets the characteristics of the basic “Block” that is used in the gate array architecture. Another factor in the block design is the requirement for a pre-determined source with “A” transistors. This prevents the use of shared diffusions that are used in most gate array architectures and resulted in a different block layout. The pre-determined sources also required a change to the logic cell library. Since the basic transmission gate found in most flop designs cannot be used, alternative logic architectures were developed. By implementing the SOI specific library into the Tekmos standard logic library, the SOI peculiarities were masked from the end designer. The 250°C ASIC technology was demonstrated in a FPGA conversion, in which a design in an Actel MX series FPGA was reimplemented in the 250°C ASIC technology. A standard FPGA design conversion flow was used, and the only issues were related to the speed and voltage differences between the FPGA and the 1.0μ ASIC. These were addressed through critical path analysis and some slight circuit modifications. The temperature derating for 250°C was significant, but enough margin was retained to allow the circuit to work. Parts were made and worked as expected at 250°C. The life testing results at 280°C have been satisfactory. On an experimental basis, parts were evaluated at temperatures of up to 305°C without failure.
46
Singh, Shakti, Nourhan El Sayed, Hazem Elgabra, Tamador ElBoshra, Maisam Wahbah, and Mariam Al Zaabi. "Modeling of High Performance 4H-SiC Emitter Coupled Logic Circuits." Materials Science Forum 778-780 (February 2014): 1009–12. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.1009.
Full textAbstract:
SiC, a wide band gap semiconductor, is capable of robust operation at temperatures well above 600°C. SiC bipolar transistors are well suited for applications at high temperatures as, unlike MOSFET, it does not have a critical gate oxide, and hence oxide reliability at high temperatures is not an issue. In this paper, the design of optimized emitter coupled logic technology circuits using 4H-SiC bipolar transistors is presented. The circuits work over a wide range of temperatures and power supply voltages at high speeds, demonstrating the potential of robust high speed ECL integrated circuits in SiC for small-scale logic applications.
47
Shaik, Sadulla, K. Sri Rama Krishna, and Ramesh Vaddi. "Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD." Journal of Circuits, Systems and Computers 27, no. 03 (2017): 1850046. http://dx.doi.org/10.1142/s0218126618500469.
Full textAbstract:
Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.
48
Wei Kai, Woo, Nabihah Ahmad, and Mohamad Hairol Jabbar. "Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (2019): 912. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp912-920.
Full textAbstract:
In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of supply. The result showed the reduction of VBB technique in term of peak power, and average power, compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.
49
Shafi, Abdullah Al, Ali Newaz Bahar, and Md Shifatul Islam. "A Quantitative Approach of Reversible Logic Gates in QCA." Journal of Communications Technology, Electronics and Computer Science 3 (December 29, 2015): 22. http://dx.doi.org/10.22385/jctecs.v3i0.33.
Full textAbstract:
Abstract—Quantum Dot Cellular Automata (QCA) is an eminent nano-technology and solution of Complementary Metal Oxide Semiconductor (CMOS) for it’s computation and transformation procedure. It is attractive for it’s size, faster speed, high scalable feature, low power consumption and higher switching frequency compared to CMOS technology. Reversible logic has many factual operation in QCA as well as VLSI design, nanotechnology, digital signal processing (DSP). This paper presents a systematic design of reversible gate based on QCA. A modified pattern of Fredkin gate, MCL gate and a new scheme of URG gate, BJN gate is proposed in this paper. For design and verification QCADesigner, a widely used simulation tool is employed. The proposed circuits can be used in erecting of nano scale low power information processing system and modelingcomplex computing systems.
50
Sabu, Neethu Anna, and K. Batri. "Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique." Journal of Circuits, Systems and Computers 29, no. 08 (2019): 2050123. http://dx.doi.org/10.1142/s0218126620501236.
Full textAbstract:
One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).