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Relevant bibliographies by topics / Logic partitioning

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Academic literature on the topic 'Logic partitioning'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

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Journal articles on the topic "Logic partitioning"

1

Dey, S., F. Brglez, and G. Kedem. "Circuit partitioning for logic synthesis." IEEE Journal of Solid-State Circuits 26, no. 3 (1991): 350–63. http://dx.doi.org/10.1109/4.75014.

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Catania, V., M. Malgeri, and M. Russo. "Applying fuzzy logic to codesign partitioning." IEEE Micro 17, no. 3 (1997): 62–70. http://dx.doi.org/10.1109/40.591657.

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Schmerl, James H. "Partitioning large vector spaces." Journal of Symbolic Logic 68, no. 4 (2003): 1171–80. http://dx.doi.org/10.2178/jsl/1067620179.

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The theme of this paper is the generalization of theorems about partitions of the sets of points and lines of finite-dimensional Euclidean spaces ℝd to vector spaces over ℝ of arbitrary dimension and, more generally still, to arbitrary vector spaces over other fields so long as these fields are not too big. These theorems have their origins in the following striking theorem of Sierpiński [12] which appeared a half century ago.Sierpiński's Theorem. The Continuum Hypothesis is equivalent to: There is a partition {X, Y, Z} of ℝ3such that if ℓ is a line parallel to the x-axis [respectively: y-axis

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4

LALA, P. K., and D. L. TAO. "Partitioning of logic circuits for exhaustive testing." International Journal of Electronics 69, no. 2 (1990): 225–31. http://dx.doi.org/10.1080/00207219008920309.

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Blutman, Kristof, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, and Jose Pineda de Gyvez. "Logic Design Partitioning for Stacked Power Domains." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 11 (2017): 3045–56. http://dx.doi.org/10.1109/tvlsi.2017.2729587.

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Kim, Hong K., and Jack Jean. "Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation." VLSI Design 9, no. 3 (1999): 253–70. http://dx.doi.org/10.1155/1999/18373.

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A partitioning algorithm for parallel discrete event gate-level logic simulations is proposed in this paper. Unlike most other partitioning algorithms, the proposed algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to few

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Bays, Timothy. "Partitioning subsets of stable models." Journal of Symbolic Logic 66, no. 4 (2001): 1899–908. http://dx.doi.org/10.2307/2694983.

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Abstract.This paper discusses two combinatorial problems in stability theory. First we prove a partition result for subsets of stable models: for any A and B, we can partition A into ∣B∣<κ(T) pieces. 〈Ai ∣ i < ∣B∣<κ(T)〉. such that for each Ai there is a Bi ⊆ B where ∣Bi∣ < κ(T) and , Second, if A and B are as above and ∣A∣ > ∣B∣, then we try to find A′ ⊂ A and B′ ⊂ B such that ∣A′∣ is as large as possible. ∣B′∣ is as small as possible, and . We prove some positive results in this direction, and we discuss the optimality of these results under ZFC + GCH.

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Russell, Kamala. "Turning Quarantine Inside Out." Space and Culture 23, no. 3 (2020): 274–78. http://dx.doi.org/10.1177/1206331220938631.

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In this essay, I describe two logics of space that are operative in responses to the COVID-19 pandemic. Quarantine partitioning is unavoidable and widespread. As a mode of governing, it presents a logic of space understood through its divisibility, making this logic seem like a given. Using the topological concept of a sphere eversion, I describe an alternative way of understanding spaces of quarantine as surroundings that we are exposed to or in contact with. I locate this alternative logic of space within already existing practices and concerns around public spaces newly invested with the po

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Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (2000): 219–35. http://dx.doi.org/10.1155/2000/12198.

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In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Increm

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Das, Jayita, Syed M. Alam, and Sanjukta Bhanja. "Nano Magnetic STT-Logic Partitioning for Optimum Performance." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 1 (2014): 90–98. http://dx.doi.org/10.1109/tvlsi.2012.2236690.

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Dissertations / Theses on the topic "Logic partitioning"

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Khan, Shoab Ahmad. "Logic and algorithm partitioning." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13738.

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Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Hering, Klaus, Reiner Haupt, and Thomas Villmann. "An Improved Mixture of Experts Approach for Model Partitioning in VLSI-Design Using Genetic Algorithms." Universität Leipzig, 1995. https://ul.qucosa.de/id/qucosa%3A34495.

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The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together the di®erent partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. We present two new partitioning algorithms (experts), the Backward-Cone-Concentration algorithm (n-BCC) and the Mini

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Krishnamurthy, Sivasubramaniam T. "STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

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Buchele, Suzanne Fox. "Three-dimensional binary space partitioning tree and constructive solid geometry tree construction from algebraic boundary representations /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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KASAT, AMIT. "MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220.

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Kheriji, Sabrine. "Design of an Energy-Aware Unequal Clustering Protocol based on Fuzzy Logic for Wireless Sensor Networks." Universitätsverlag Chemnitz, 2020. https://monarch.qucosa.de/id/qucosa%3A73303.

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Energy consumption is a major concern in Wireless Sensor Networks (WSNs) resulting in a strong demand for energy-aware communication technologies. In this context, several unequal cluster-based routing protocols have been proposed. However, few of them adopt energetic analysis models for the calculation of the optimal cluster radius and several protocols can not realize an optimal workload balance between sensor nodes. In this scope, the aim of the dissertation is to develop a cluster-based routing protocol for improving energy efficiency in WSN. We propose a Fuzzy-based Energy-Aware Unequal C

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Hepp, Luiz Ubiratan. "Partição da diversidade de insetos aquáticos em riachos do sul do Brasil." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2011. http://hdl.handle.net/10183/37433.

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O presente estudo teve por objetivo principal avaliar a distribuição espacial de insetos aquáticos (Ephemeroptera, Plecoptera e Trichoptera; EPT) em riachos do Sul do Brasil. Para tanto, foram realizados diferentes estudos com objetivos específicos direcionados a (i) avaliar o efeito de fatores ambientais e espaciais sobre a distribuição dos organismos, (ii) verificar as escalas heirárquicas onde ocorreram maior variação da comunidade (diversidade beta), (iii) testar a existência de relação entre a composição de espécies e diferentes distâncias espaciais e (iv) avaliar a importância da inclusã

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Huang, Juinn-Dar, and 黃俊達. "Logic Synthesis and Partitioning for FPGAs." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/54860090825196275940.

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博士<br>國立交通大學<br>電子工程學系<br>86<br>This dissertation explores the issues of logic synthesis, technologymapping and partitioning for field programmable gate arrays andproposes the corresponding algorithms to solve them. On thesynthesis of LUT-based FPGAs, an improved algorithm based on Roth-Karp decomposition is proposed to make the given logic networksfeasible. On the input variable partitioning, a novel heuristicalgorithm, which selects a good bound set in Roth- Karpdecomposition, is present

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"GBAW for logic synthesis and circuit partitioning." 2006. http://library.cuhk.edu.hk/record=b5892784.

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Ho Chi Kit.<br>Thesis submitted in: September 2005.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.<br>Includes bibliographical references (leaves 66-70).<br>Abstracts in English and Chinese.<br>Chapter 1 --- Introduction --- p.9<br>Chapter 1.1 --- Aims and Contribution --- p.9<br>Chapter 1.2 --- Dissertation Overview --- p.10<br>Chapter 2 --- Literature Review --- p.11<br>Chapter 2.1 --- ATPG-based Alternative Wiring --- p.11<br>Chapter 2.1.1 --- Post-Layout Logic Restructuring for Performance Optimization --- p.11<br>Chapter 2.1.2 --- Timing Optimization by an Improved Redu

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Books on the topic "Logic partitioning"

1

Healey, Steven Thomas. Abstract partitioning and routing of logic networks for custom module generation. Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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2

Kahng, Andrew B. VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer Science+Business Media B.V., 2011.

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3

Hudak, David E. Compiling parallel loops for high performance computers: Partitioning, data assignment, and remapping. Kluwer Academic, 1993.

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4

Partitioning Implementations for IBM Eserver P5 Servers. IBM.Com/Redbooks, 2005.

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Redbooks, IBM, and Keigo Matsubara. The Complete Partitioning Guide for IBM pSeries Servers (IBM Redbooks). Vervante, 2003.

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6

Redbooks, IBM. Capacity Planning for Logical Partitioning on the IBM Elogo Server Iseries Server. Ibm, 2001.

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7

Abraham, Santosh G., and David E. Hudak. Compiling Parallel Loops for High Performance Computers:: Partitioning, Data Assignment and Remapping (The International Series in Engineering and Computer Science). Springer, 1992.

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Book chapters on the topic "Logic partitioning"

1

Mukherjee, Rajarshi, and Seda Ogrenci Memik. "Power-Driven Design Partitioning." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_75.

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2

Winterstein, Felix. "Heap Partitioning and Parallelisation." In Separation Logic for High-level Synthesis. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53222-6_4.

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3

Wehn, N., M. Glesner, A. Kister, and S. Kastner. "Timing Driven Partitioning of Combinational Logic." In Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme. Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/978-3-642-84304-4_5.

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4

Wolz, Frank, and Reiner Kolla. "Bubble Partitioning for LUT-Based Sequential Circuits." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_35.

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5

Angelopoulos, Nicos. "Probabilistic Space Partitioning in Constraint Logic Programming." In Advances in Computer Science - ASIAN 2004. Higher-Level Decision Making. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30502-6_4.

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Hyvärinen, Antti E. J., Tommi Junttila, and Ilkka Niemelä. "Partitioning SAT Instances for Distributed Solving." In Logic for Programming, Artificial Intelligence, and Reasoning. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-16242-8_27.

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7

Weinhardt, Markus. "Integer programming for partitioning in software oriented codesign." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/3-540-60294-1_116.

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Harkin, Jim, Thomas M. McGinnity, and Liam P. Maguire. "Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_62.

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Velinov Chichkov, Anton, and Carlos Beltrán Almeida. "An hardware/software partitioning algorithm for custom computing machines." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63465-7_232.

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Zhong, Alin, Shun Ren, and Shouzhi Xu. "CDLP: A Core Distributing Policy Based on Logic Partitioning." In Green, Pervasive, and Cloud Computing. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-57186-7_33.

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Conference papers on the topic "Logic partitioning"

1

De, K., and P. Banerjee. "Parallel Logic Synthesis Using Partitioning." In 1994 International Conference on Parallel Processing Vol. 3. IEEE, 1994. http://dx.doi.org/10.1109/icpp.1994.150.

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Wu, Xindong, Shaojing Sheng, and Peng Zhou. "Balanced Tree Partitioning with Succinct Logic." In 2020 IEEE International Conference on Knowledge Graph (ICKG). IEEE, 2020. http://dx.doi.org/10.1109/icbk50248.2020.00083.

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Neela, Gopi, and Jeffrey Draper. "Logic-on-logic partitioning techniques for 3-dimensional integrated circuits." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571965.

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4

Dehkordi, Mehrdad Eslami, Stephen D. Brown, and Terry Borer. "Modular Partitioning for Incremental Compilation." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311202.

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Wu, Yu-Liang, Xiao-Long Yuan, and David Ihsin Cheng. "Circuit partitioning with coupled logic restructuring techniques." In the 2000 conference. ACM Press, 2000. http://dx.doi.org/10.1145/368434.368862.

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Chou, Nan-Chi, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, and Rodney Lindelof. "Circuit partitioning for huge logic emulation systems." In the 31st annual conference. ACM Press, 1994. http://dx.doi.org/10.1145/196244.196365.

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Spacey, Simon A., Wayne Luk, Paul H. J. Kelly, and Daniel Kuhn. "Rapid Design Space visualisation through hardware/software partitioning." In 2009 5th Southern Conference on Programmable Logic (SPL). IEEE, 2009. http://dx.doi.org/10.1109/spl.2009.4914913.

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El-Masry, Hisham, and Dhamin Al-Khalili. "A complementary logic partitioning algorithm for a library-free logic synthesis paradigm." In Microelectronics, MEMS, and Nanotechnology, edited by Alex J. Hariz and Vijay K. Varadan. SPIE, 2007. http://dx.doi.org/10.1117/12.759536.

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Nunna, Krishna Chaitanya, Farhad Mehdipour, and Kazuaki Murakami. "Thermal-aware partitioning for 3D FPGAs." In 2012 22nd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2012. http://dx.doi.org/10.1109/fpl.2012.6339198.

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Patil, S., P. Banerjee, and C. Polychronopoulos. "Efficient circuit partitioning algorithms for parallel logic simulation." In the 1989 ACM/IEEE conference. ACM Press, 1989. http://dx.doi.org/10.1145/76263.76303.

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