Academic literature on the topic 'Logical effort'
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Journal articles on the topic "Logical effort"
Lasbouygues, B., S. Engels, R. Wilson, P. Maurine, N. Azemard, and D. Auvergne. "Logical effort model extension to propagation delay representation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (September 2006): 1677–84. http://dx.doi.org/10.1109/tcad.2005.857400.
Full textLevi, Itamar, Alexander Belenky, and Alexander Fish. "Logical Effort for CMOS-Based Dual Mode Logic Gates." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 5 (May 2014): 1042–53. http://dx.doi.org/10.1109/tvlsi.2013.2257902.
Full textRahman, M., H. Tennakoon, and C. Sechen. "Library-Based Cell-Size Selection Using Extended Logical Effort." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 7 (July 2013): 1086–99. http://dx.doi.org/10.1109/tcad.2013.2247657.
Full textKabbani, A., D. Al-Khalili, and A. J. Al-Khalili. "Delay analysis of CMOS gates using modified logical effort model." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 6 (June 2005): 937–47. http://dx.doi.org/10.1109/tcad.2005.847892.
Full textMilic, Miodrag, and Vojin Senk. "Uniform logical cryptanalysis of CubeHash function." Facta universitatis - series: Electronics and Energetics 23, no. 3 (2010): 357–66. http://dx.doi.org/10.2298/fuee1003357m.
Full textWest, Donna E. "Logical and practical advantages of double consciousness." Cognitive Semiotics 14, no. 1 (May 1, 2021): 47–69. http://dx.doi.org/10.1515/cogsem-2021-2038.
Full textKarandikar, S. K., and S. S. Sapatnekar. "Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 1 (January 2008): 45–58. http://dx.doi.org/10.1109/tcad.2007.907067.
Full textShine, Lester C., and Charles M. Stoup. "On Transforming Ordered Residuals for Purposes of Testing the Correctness of a Regression Model." Educational and Psychological Measurement 45, no. 2 (July 1985): 211–16. http://dx.doi.org/10.1177/001316448504500203.
Full textKabbani, A. "Logical effort based dynamic power estimation and optimization of static CMOS circuits." Integration 43, no. 3 (June 2010): 279–88. http://dx.doi.org/10.1016/j.vlsi.2010.02.002.
Full textbasireddy, hareesh-reddy, Karthikeya challa, and Tooraj Nikoubin. "Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 5 (May 2019): 1138–47. http://dx.doi.org/10.1109/tvlsi.2018.2889833.
Full textDissertations / Theses on the topic "Logical effort"
Wunderlich, Richard Bryan. "CMOS gate delay, power measurements and characterization with logical effort and logical power." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31652.
Full textCommittee Chair: Paul Hasler; Committee Member: David V Anderson; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Alegretti, Caio Graco Prates. "Analytical logical effort formulation for local sizing." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/97867.
Full textMicroelectronics industry has been relying more and more upon cell-based design methodology to face the growing complexity in the design of digital integrated circuits, since cell-based integrated circuits are designed in a faster and cheaper way than fullcustom circuits. Nevertheless, in spite of the advancements in the field of Electronic Design Automation, cell-based digital integrated circuits show inferior performance when compared with full-custom circuits. Therefore, it is desirable to find ways to bring the performance of cell-based circuits closer to that of full-custom circuits without compromising the design costs of the former circuits. Bearing this goal in mind, this thesis presents contributions towards an automatic flow of local optimization for cellbased digital circuits. By local optimization, it is meant circuit optimization within small context windows, in which optimizations are done taking into account the global context. This way, local optimization may include the detection and isolation of critical regions of the circuit and the generation of logic and transistor networks; these networks are sized according to the existing design constraints. Since local optimizations act in a reduced context, several solutions may be obtained considering local constraints, out of which the fittest solution is chosen to replace the original subcircuit (critical region). The specific contribution of this thesis is the development of a subcircuit sizing method capable of obtaining minimum active area solutions, taking into account the maximum input capacitance, the output load to be driven, and the imposed delay constraint. The method is based on the logical effort formulation, and the main contribution is to compute the area derivative to obtain minimum area, instead of making the delay derivative to obtain minimum delay, as it is done in the traditional logical effort formulation. Electrical simulations show that the proposed method is very precise for a first order approach, as it presents average errors of 1.48% in power dissipation, 2.28% in propagation delay, and 6.5% in transistor sizes.
Galvis, Jorge Alberto. "Low-power flip-flop using internal clock gating and adaptive body bias." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001465.
Full textYongyi, Yuan. "Investigation and implementation of data transmission look-ahead D flip-flops." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2529.
Full textThis thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.
Veřmiřovský, Jakub. "Koevoluce v evolučním návrhu obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255429.
Full textKalargaris, Charalampos. "Design methodologies and tools for vertically integrated circuits." Thesis, University of Manchester, 2017. https://www.research.manchester.ac.uk/portal/en/theses/design-methodologies-and-tools-for-vertically-integrated-circuits(63c9c674-566a-44e5-b6b6-8a277b1adf08).html.
Full textSzalapaj, Peter J. "Logical graphics : logical representation of drawings to effect graphical transformation." Thesis, University of Edinburgh, 1988. http://hdl.handle.net/1842/19334.
Full textRogers, Donna R. B. "The Effect of Dyad Interaction and Marital Adjustment on Cognitive Performance in Everyday Logical Problem Solving." DigitalCommons@USU, 1992. https://digitalcommons.usu.edu/etd/6061.
Full textRijn, Dirk Hendrik van. "Exploring the limited effect of inductive discovery learning computational models and model-based analyses /." [Amsterdam : Amsterdam : EPOS, experimenteel-psychologische onderzoekschool] ; Universiteit van Amsterdam [Host], 2003. http://dare.uva.nl/document/68567.
Full textMay, Bruce Matthew. "Elementary Logic as a Tool in Proving Mathematical Statements." Thesis, University of the Western Cape, 2008. http://etd.uwc.ac.za/index.php?module=etd&action=viewtitle&id=gen8Srv25Nme4_1025_1263170321.
Full textThe findings of the study indicate that knowledge of logic does help to improve the ability of students to make logical connections (deductions) between and from
statements. The results of the study, however, do not indicate that knowledge and understanding of logic translates into improved proving ability of mathematical
statements by students.
Books on the topic "Logical effort"
F, Sproull Robert, and Harris David, eds. Logical effort: Designing fast CMOS circuits. San Francisco, Calif: Morgan Kaufmann Publishers, 1999.
Find full textVilkko, Risto. A hundred years of logical investigation: Reform efforts of logic in Germany, 1781-1879. Paderborn: Mentis, 2002.
Find full textVarlamov, Oleg. Mivar databases and rules. ru: INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1508665.
Full textVarlamov, Oleg. 18 examples of mivar expert systems. ru: INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1248446.
Full textBorzyh, Stanislav. Pananthropea. ru: INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1218149.
Full textCritical transitions in nature and society. Princeton: Princeton University Press, 2009.
Find full textAbramsky, S., Dov M. Gabbay, and T. S. E. Maibaum, eds. Handbook of Logic in Computer Science: Volume 5. Algebraic and Logical Structures. Oxford University Press, 2001. http://dx.doi.org/10.1093/oso/9780198537816.001.0001.
Full textBerto, Francesco, and Mark Jago. Impossible Worlds. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780198812791.001.0001.
Full textLorino, Philippe. Abduction. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198753216.003.0007.
Full textAllwein, Gerard, and Jon Barwise. Logical Reasoning with Diagrams. Oxford University Press, 1996. http://dx.doi.org/10.1093/oso/9780195104271.001.0001.
Full textBook chapters on the topic "Logical effort"
Abbas, Karim. "Logical Effort." In Handbook of Digital CMOS Technology, Circuits, and Systems, 145–56. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_4.
Full textAlioto, Massimo, Elio Consoli, and Gaetano Palumbo. "The Logical Effort Method." In Flip-Flop Design in Nanometer CMOS, 1–26. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-01997-0_1.
Full textMaheshwari, Sachin, Himadri Singh Raghav, and Anu Gupta. "Characterization of Logical Effort for Improved Delay." In Communications in Computer and Information Science, 108–17. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-42024-5_14.
Full textLasbouygues, B., R. Wilson, P. Maurine, N. Azémard, and D. Auvergne. "Physical Extension of the Logical Effort Model." In Lecture Notes in Computer Science, 838–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_86.
Full textDao, Hoang Q., and Vojin G. Oklobdzija. "Performance Comparison of VLSI Adders Using Logical Effort." In Lecture Notes in Computer Science, 25–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x_3.
Full textAlves, Luís M., Pedro Ribeiro, and Ricardo J. Machado. "Architectural Element Points: Estimating Software Development Effort by Analysis of Logical Architectures." In Information Systems: Development, Research, Applications, Education, 72–84. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-46642-2_5.
Full textMaheshwari, Sachin, Rameez Raza, Pramod Kumar, and Anu Gupta. "Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology." In Communications in Computer and Information Science, 185–93. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-42024-5_23.
Full textHeinemann, Bernhard. "Observational Effort and Formally Open Mappings." In Logic, Language, Information and Computation, 197–208. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-02261-6_16.
Full textKarmakar, Supriya. "Introduction: Multistate Devices and Logic." In Novel Three-state Quantum Dot Gate Field Effect Transistor, 1–6. New Delhi: Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1635-3_1.
Full textEgger, Jeff, Rasmus Ejlers Møgelberg, and Alex Simpson. "Enriching an Effect Calculus with Linear Types." In Computer Science Logic, 240–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-04027-6_19.
Full textConference papers on the topic "Logical effort"
Keane, John, Hanyong Eom, Tae-Hyoung Kim, Sachin Sapatnekar, and Chris Kim. "Subthreshold logical effort." In the 43rd annual conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1146909.1147022.
Full textJohari, A., S. Mohamed, A. K. Halim, I. M. Yassin, and H. A. Hassan. "Logical circuit gate sizing using PSO guided by Logical Effort." In 2010 International Conference on Computer Applications and Industrial Electronics (ICCAIE). IEEE, 2010. http://dx.doi.org/10.1109/iccaie.2010.5735110.
Full textHaile Yu, Yuk Hei Chan, and Philip H. W. Leong. "FPGA interconnect design using logical effort." In 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4629980.
Full textYu, Haile, Yuk Hei Chan, and Philip H. W. Leong. "FPGA interconnect design using logical effort." In the 16th international ACM/SIGDA symposium. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1344671.1344710.
Full textMaheshwari, Sachin, Jimit Patel, Sumit K. Nirmalkar, and Anu Gupta. "Logical effort based power-delay-product optimization." In 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2014. http://dx.doi.org/10.1109/icacci.2014.6968530.
Full textAli, Muhammad, Mohammad Ahmed, and Malgorzata Chrzanowska-Jeske. "Logical Effort model for CNFET-based circuits." In 2014 IEEE 14th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2014. http://dx.doi.org/10.1109/nano.2014.6968105.
Full textYu, Haile. "FPGA interconnect sizing using extended logical effort model." In 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4630042.
Full textAnacan, Rommel M., and Josephine L. Bagay. "Logical Effort Analysis of various VLSI design algorithms." In 2015 IEEE International Conference on Control System, Computing and Engineering (ICCSCE). IEEE, 2015. http://dx.doi.org/10.1109/iccsce.2015.7482151.
Full textTiwari, Satish Chandra, Aneesh Gupta, Kunwar Singh, and Maneesha Gupta. "Logical effort based automated transistor width optimization methodology." In 2011 World Congress on Information and Communication Technologies (WICT). IEEE, 2011. http://dx.doi.org/10.1109/wict.2011.6141396.
Full textChun-Hui Wu, Shun-Hua Lin, and Herming Chiueh. "logical effort model extension with temperature and voltage variations." In 2008 14th International Workshop on Thermal Inveatigation of ICs and Systems (THERMINIC). IEEE, 2008. http://dx.doi.org/10.1109/therminic.2008.4669884.
Full textReports on the topic "Logical effort"
Hicks, Julie, Laurin Yates, and Jackie Pettway. Mat Sinking Unit supply study : Mississippi River revetment. Engineer Research and Development Center (U.S.), September 2021. http://dx.doi.org/10.21079/11681/41867.
Full textBjella, Kevin, Yuri Shur, Misha Kanevskiy, Paul Duvoy, Bruno Grunau, John Best, Stephen Bourne, and Rosa Affleck. Improving design methodologies and assessment tools for building on permafrost in a warming climate. Engineer Research and Development Center (U.S.), November 2020. http://dx.doi.org/10.21079/11681/38879.
Full textKim, Sung H. Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic. Fort Belvoir, VA: Defense Technical Information Center, May 2012. http://dx.doi.org/10.21236/ada561720.
Full textRose, Jonathan, Robert J. Francis, Paul Chow, and David Lewis. The Effect of Logic Block Complexity on Area of Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, January 1987. http://dx.doi.org/10.21236/ada207172.
Full textWiecha, Jean L., and Mary K. Muth. Agreements Between Public Health Organizations and Food and Beverage Companies: Approaches to Improving Evaluation. RTI Press, January 2021. http://dx.doi.org/10.3768/rtipress.2021.op.0067.2101.
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