Relevant bibliographies by topics / Look up-tables (LUT)

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Academic literature on the topic 'Look up-tables (LUT)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Look up-tables (LUT)"

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Yang, Jun-Yu, Wei-Jhe Ma, Feng-Ting Pai, and Ching-Chun Lin. "P‐129: A Self‐adaptive Gamma LUT Conversion to Achieve Optical Consistency under a Variety of IR‐drop Compensation Scenarios." SID Symposium Digest of Technical Papers 54, no. 1 (2023): 1330–33. http://dx.doi.org/10.1002/sdtp.16828.

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The OLED display can support various IRC conditions for better user experience. However, the more IRC conditions in display, the more gamma Look‐Up Tables (LUT) are required. This paper proposed a method to convert gamma LUT automatically according to IRC condition of itself. The proposed method can save the One‐Time‐Programmable (OTP) memory and shorten the production time. Up to 80% OTP size and time could be saved in the experimental results. In addition, the converted gamma LUT have better optical consistency than the traditional measured gamma LUT.
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Al-Ibrahim (Jarrah), M. M. "Extremely High Frequency Resolution and Low Harmonic Distortion Digital Look-Up-Table Sinusoidal Oscillators." Active and Passive Electronic Components 23, no. 2 (2000): 101–13. http://dx.doi.org/10.1155/apec.23.101.

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New techniques to efficiently increase the frequency resolution of digital sinusoidal oscillators based on look-up-table (LUT) methods are proposed. The increase in frequency resolution is achieved while maintaining very low level of spurious harmonic distortion. The proposed techniques increase the LUT length to a level at which the spurious harmonic distortion is negligible. The first proposed technique is based on partitioning the address register into three sets and dividing the available LUT length into three smaller tables addressed according to the content of the address register sets.
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Sun, Jun-Wei, Xing-Tong Zhao, and Yan-Feng Wang. "Multi-Input Look-Up-Table Design Based on Nanometer Memristor." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (2020): 113–21. http://dx.doi.org/10.1166/jno.2020.2721.

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The logic blocks of Field Programmable Gate Array (FPGA) basic unit are mainly composed of Look-Up-Tables (LUTs). The traditional LUTs use the static random access memory (SRAM), which causes FPGA reach the limitation in term of the density, speed, and configuration overhead. In this paper, a novel nanometer memristor-based LUT (NMLUT) is composed of memristors, MOS field effect transistors, decoders, resistors. A three-input NMLUT and a four-input NMLUT circuits are investigated. Moreover, an adder is used to verify the practicality of NMLUT circuit. The proposed NMLUT circuit can implement s
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Putra, Agfianto Eko, Oskar Natan, and Jazi Eko Istiyanto. "Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques." IIUM Engineering Journal 26, no. 1 (2025): 240–53. https://doi.org/10.31436/iiumej.v26i1.3328.

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Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/O
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Barkalov, Alexander, Larysa Titarenko, and Sławomir Chmielewski. "Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs." Journal of Circuits, Systems and Computers 28, no. 08 (2019): 1950131. http://dx.doi.org/10.1142/s0218126619501317.

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A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.
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Ko, Hyung-Hwa. "Enhanced Binary MQ Arithmetic Coder with Look-Up Table." Information 12, no. 4 (2021): 143. http://dx.doi.org/10.3390/info12040143.

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Binary MQ arithmetic coding is widely used as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as a unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity that happens in the MQ coder, the output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to
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Magini, Jacopo, Pietro Pisciotta, Mohammad Hussein, et al. "Integration of microdosimetry into treatment planning systems using look-up tables (LUT): A proof-of-concept." Physica Medica 136 (August 2025): 105031. https://doi.org/10.1016/j.ejmp.2025.105031.

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Al-Ibrahim (Jarrah), M. M. "A Novel Coherent Digital Sweep Oscillator with Extremely Low Sweep Rates and Harmonic Distortion." Active and Passive Electronic Components 23, no. 4 (2001): 197–217. http://dx.doi.org/10.1155/apec.23.197.

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A novel technique to efficiently increase the resolution of coherent digital sweep oscillators based on look-up-table (LUT) methods is proposed. The increase in resolution measured in terms of sweep rates is achieved while maintaining very low levels of spurious harmonic distortion. The proposed technique increases the LUT length to a level at which the spurious harmonic distortion is negligible. The proposed technique is based on partitioning the address register into three sets and dividing the available LUT length into five smaller tables addressed according to the content of the three addr
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9

Choi, Soyeon, and Hoyoung Yoo. "Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA." Electronics 9, no. 7 (2020): 1132. http://dx.doi.org/10.3390/electronics9071132.

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This paper presents a fast method to extract logic functions of look-up tables (LUTs) from a bitstream in Xilinx FPGAs. In general, FPGAs utilize LUTs as a primary resource to realize a logic function, and a typical N-input LUT comprises 2N 1-bit SRAM and N – 1 multiplexers. Whereas the previous research demands 2N exhaustive processing to find a mapping rule between an LUT and a bitstream, the proposed method decreases the processing to 2N by eliminating unnecessary processing. Experimental results show that the proposed method can reduce reversing time by more than 57% and 85% for Xilinx Spa
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Kim, HanBit, HeeSeok Kim, and Seokhie Hong. "Power-Balancing Software Implementation to Mitigate Side-Channel Attacks without Using Look-Up Tables." Applied Sciences 10, no. 7 (2020): 2454. http://dx.doi.org/10.3390/app10072454.

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With the increasing number of side-channel attacks, countermeasure designers continue to develop various implementations to address such threats. Power-balancing (PB) methods hold the number of 1s and/or transitions (i.e., Hamming weight/distance) of internal processes constant to ensure side-channel safety in an environment in which it is difficult to use random numbers. Most existing studies employed look-up tables (LUTs) to compute those operations, except for XOR and NOT operations. However, LUT-based schemes exhibit some side-channel issues in the address bits of LUTs. In this paper, we p
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Conference papers on the topic "Look up-tables (LUT)"

1

Goutzoulis, A. P., D. K. Davies, E. C. Malarkey, J. C. Bradley, and P. R. Beaudet. "Residue Position-Coded Look-Up Table Processing." In Optical Computing. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/optcomp.1987.md3.

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Residue arithmetic(1) has some very desirable features(2,3) which include: lack of carries, bounded input/output dynamic range and the ability to decompose a calculation into many parallel subcalculations of lesser complexity. Such features, when combined with high-speed position-coded optoelectronic look-up tables (LUT), result in high-speed, power efficient, low complexity processors.
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Journal articles
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