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Journal articles on the topic 'Low latency'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Hasbrouck, Joel, and Gideon Saar. "Low-latency trading." Journal of Financial Markets 16, no. 4 (2013): 646–79. http://dx.doi.org/10.1016/j.finmar.2013.05.003.

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Murtala, I., and O. A. Tiamiyu. "Comparative Analysis of Low Latency Anonymous Communication Systems." Proceedings of Telecommunication Universities 4, no. 3 (2018): 85–97. http://dx.doi.org/10.31854/1813-324x-2018-4-3-85-97.

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Riley, Holly, Rebecca B. MacLeod, and Matthew Libera. "Low Latency Audio Video." Update: Applications of Research in Music Education 34, no. 3 (2014): 15–23. http://dx.doi.org/10.1177/8755123314554403.

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Roy, Pratanu, Jens Teubner, and Rainer Gemulla. "Low-latency handshake join." Proceedings of the VLDB Endowment 7, no. 9 (2014): 709–20. http://dx.doi.org/10.14778/2732939.2732944.

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Marinšek, Alexander, Daan Delabie, Lieven De Strycker, and Liesbet Van der Perre. "Physical Layer Latency Management Mechanisms: A Study for Millimeter-Wave Wi-Fi." Electronics 10, no. 13 (2021): 1599. http://dx.doi.org/10.3390/electronics10131599.

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Emerging applications in fields such as extended reality require both a high throughput and low latency. The millimeter-wave (mmWave) spectrum is considered because of the potential in the large available bandwidth. The present work studies mmWave Wi-Fi physical layer latency management mechanisms, a key factor in providing low-latency communications for time-critical applications. We calculate physical layer latency in an ideal scenario and simulate it using a tailor-made simulation framework, based on the IEEE 802.11ad standard. Assessing data reception quality over a noisy channel yielded l

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Liu, Qing, Heming Wang, Fangxu Lyu, Geng Zhang, and Dongbin Lyu. "A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0." Electronics 12, no. 14 (2023): 3102. http://dx.doi.org/10.3390/electronics12143102.

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As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filt

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Kavamahanga, Lambert, Theodette Uwimbabazi, and Damascene Uwizeyemungu. "Low-Latency and Ultra-Reliable Communication for Industrial 5G." Journal of Current Trends in Computer Science Research 3, no. 4 (2024): 01–05. http://dx.doi.org/10.33140/jctcsr.03.04.02.

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The Internet of Things(IoT) is a planned Internet extension in which everyday objects are outfitted with circuitry, software, sensors, and internet connectivity is required so that data can be received and sent over the Internet. Emerging applications like factory automation and au- tonomous driving necessitate affordable, dependable, and low- latency communication making wireless architecture It’s more convoluted than before. The study’s goal is to understand existing study issues and solutions in connection with 5G-enabled Industrial IoT based on both sectors’ original goals and commitments.

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Litz, Heiner, Javier Gonzalez, Ana Klimovic, and Christos Kozyrakis. "RAIL: Predictable, Low Tail Latency for NVMe Flash." ACM Transactions on Storage 18, no. 1 (2022): 1–21. http://dx.doi.org/10.1145/3465406.

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Flash-based storage is replacing disk for an increasing number of data center applications, providing orders of magnitude higher throughput and lower average latency. However, applications also require predictable storage latency. Existing Flash devices fail to provide low tail read latency in the presence of write operations. We propose two novel techniques to address SSD read tail latency, including Redundant Array of Independent LUNs (RAIL) which avoids serialization of reads behind user writes as well as latency-aware hot-cold separation (HC) which improves write throughput while maintaini

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Arribas, Victor, Zhenda Zhang, and Svetla Nikova. "LLTI: Low-Latency Threshold Implementations." IEEE Transactions on Information Forensics and Security 16 (2021): 5108–23. http://dx.doi.org/10.1109/tifs.2021.3123527.

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Hurtig, Per, Karl-Johan Grinnemo, Anna Brunstrom, Simone Ferlin, Ozgu Alay, and Nicolas Kuhn. "Low-Latency Scheduling in MPTCP." IEEE/ACM Transactions on Networking 27, no. 1 (2019): 302–15. http://dx.doi.org/10.1109/tnet.2018.2884791.

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Chen, Kwang-Cheng, Tao Zhang, Richard D. Gitlin, and Gerhard Fettweis. "Ultra-Low Latency Mobile Networking." IEEE Network 33, no. 2 (2019): 181–87. http://dx.doi.org/10.1109/mnet.2018.1800011.

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Oesch, Christian, and Dietmar Maringer. "Low-latency liquidity inefficiency strategies." Quantitative Finance 17, no. 5 (2016): 717–27. http://dx.doi.org/10.1080/14697688.2016.1242765.

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13

Shukla, Rohit, and Kailash Chandra Ray. "Low Latency Hybrid CORDIC Algorithm." IEEE Transactions on Computers 63, no. 12 (2014): 3066–78. http://dx.doi.org/10.1109/tc.2013.173.

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14

Giard, Pascal, Gabi Sarkis, Camille Leroux, Claude Thibeault, and Warren J. Gross. "Low-Latency Software Polar Decoders." Journal of Signal Processing Systems 90, no. 5 (2016): 761–75. http://dx.doi.org/10.1007/s11265-016-1157-y.

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15

Zhao, W., P. M. Melliar-Smith, and L. E. Moser. "Low Latency Fault Tolerance System." Computer Journal 56, no. 6 (2012): 716–40. http://dx.doi.org/10.1093/comjnl/bxs131.

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Timmermann, D., H. Hahn, and B. J. Hosticka. "Low latency time CORDIC algorithms." IEEE Transactions on Computers 41, no. 8 (1992): 1010–15. http://dx.doi.org/10.1109/12.156543.

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Sowmiyaa P, Saranya P, Sabena M, Saranya R, and Subhisha K. "LOW-LATENCY APPROXIMATE ADDERIN FPGA." international journal of engineering technology and management sciences 9, no. 2 (2025): 23–25. https://doi.org/10.46647/ijetms.2025.v09i02.005.

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Approximate computing has gained significant attention for applications where absolute precision isnot critical, such as image processing, machine learning, and signal processing. The proposeddesign divides the addition process into two stages: a main sub-adder for high-speed approximatecomputation and an error sub-adder for refining accuracy. By limiting carry propagation in the mainsub-adder, the critical path delay is significantly reduced, achieving low latency. Simultaneously,the error sub-adder operates in parallel to correct errors, ensuring a balance between performanceand precision. E

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18

Ge, Jun Wei, Hai Ming Zheng, and Yi Qiu Fang. "A Hybird Virtual Machine Placement Aglrithm for Virtualized Desktop Infrastructure." Advanced Materials Research 760-762 (September 2013): 1906–10. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.1906.

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As we all kown, The virtual machine placement is one kind of bin-packing problem. By optimizing placement of virtual machine. We can improve VM performance, enhance resource utilization, reduce energy comsumption. After analysis the existing virtual machine placement aglrithm. We propose a hybird virtual machine placement aglrithm (HTA) which based on network latency threshold for the requirement of low network latence and low VM migraiton ratio in Virtualized Desktop Infrastructure. It elect qualified node set based on network latency threshold and palce the virtual machines with load-balance

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19

Han, Feixue, Mowei Wang, Yong Cui, et al. "Future Data Center Networking: From Low Latency to Deterministic Latency." IEEE Network 36, no. 1 (2022): 52–58. http://dx.doi.org/10.1109/mnet.102.2000622.

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20

Caspe, Franco, Jordie Shier, Mark Sandler, Charalampos Saitis, and Andrew McPherson. "Designing Neural Synthesizers for Low-Latency Interaction." Journal of the Audio Engineering Society 73, no. 5 (2025): 240–55. https://doi.org/10.17743/jaes.2022.0204.

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Neural audio synthesis (NAS) models offer interactive musical control over high-quality, expressive audio generators. While these models can operate in real time, they often suffer from high latency, making them unsuitable for intimate musical interaction. The impact of architectural choices in deep learning models on audio latency remains largely unexplored in the NAS literature. In this work, the authors investigate the sources of latency and jitter typically found in interactive NAS models. They then apply this analysis to the task of timbre transfer using the RAVE model (Realtime Audio Var

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21

Shin, Ho, and Eui-Young Chung. "In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs." Micromachines 10, no. 2 (2019): 124. http://dx.doi.org/10.3390/mi10020124.

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Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed,

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22

Renfei Liu and K. K. Parhi. "Low-Latency Low-Complexity Architectures for Viterbi Decoders." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 10 (2009): 2315–24. http://dx.doi.org/10.1109/tcsi.2008.2012217.

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23

Chiola, G., and G. Ciaccio. "Implementing a low cost, low latency parallel platform." Parallel Computing 22, no. 13 (1997): 1703–17. http://dx.doi.org/10.1016/s0167-8191(96)00072-5.

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24

Gürel, O., and M. U. Çakır. "XMPP Based Applications under Low Bandwidth and High Latency Conditions." Lecture Notes on Software Engineering 3, no. 4 (2015): 314–17. http://dx.doi.org/10.7763/lnse.2015.v3.211.

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25

Ganachari, Girish. "Low Latency Data Lookups in Real - Time Data Engineering Pipelines." International Journal of Science and Research (IJSR) 9, no. 10 (2020): 1815–19. http://dx.doi.org/10.21275/sr24801075034.

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26

Halbhuber, David, Philipp Schauhuber, Valentin Schwind, and Niels Henze. "The Effects of Latency and In-Game Perspective on Player Performance and Game Experience." Proceedings of the ACM on Human-Computer Interaction 7, CHI PLAY (2023): 1308–29. http://dx.doi.org/10.1145/3611070.

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Previous work shows that high latency, a prolonged delay between player in- and system output, negatively affects player experience and performance. However, previous work also comes to contrary conclusions about how the in-game perspective alters the latency sensitivity of video games. Currently, it is unclear if the in-game perspective independently modulates latency's effects. To investigate how a game's in-game perspective interacts with latency, we developed a shooting game incorporating three perspectives (First-Person-, Third-Person-, and Bird's-Eye-View). In a study, participants (N =

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27

Jiang, Xiaolin, Hossein Shokri-Ghadikolaei, Gabor Fodor, et al. "Low-Latency Networking: Where Latency Lurks and How to Tame It." Proceedings of the IEEE 107, no. 2 (2019): 280–306. http://dx.doi.org/10.1109/jproc.2018.2863960.

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28

Avranas, Apostolos, Marios Kountouris, and Philippe Ciblat. "Energy-Latency Tradeoff in Ultra-Reliable Low-Latency Communication With Retransmissions." IEEE Journal on Selected Areas in Communications 36, no. 11 (2018): 2475–85. http://dx.doi.org/10.1109/jsac.2018.2874143.

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29

FAROOQ, SHEZA, AMAN KUMAR, SUMAN CHAUDHARY, and SUSHILA MAAN. "Development of TaqMan probe-based RT-qPCR assays for detection of BoHV-1 latency in Bovine." Indian Journal of Animal Sciences 94, no. 3 (2024): 247–50. http://dx.doi.org/10.56093/ijans.v94i3.143188.

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Bovine herpesvirus-1 is highly contagious virus of cattle and buffaloes all over the world. It establishes lifelong latency in ganglionic neurons of the peripheral nervous system. Since, trigeminal ganglia are the main sites of latency, therefore, it is challenging to detect BoHV-1 in latently infected live animals. No research work has been done to correlate the sero-prevalence and latency in peripheral blood mononuclear cells (PBMC). The present study was designed to detect BoHV-1 latency related transcript or microRNA in peripheral blood mononuclear cells of sero-positive animals. The highl

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30

Das, Debajyoti, Easwar Vivek Mangipudi, and Aniket Kate. "OrgAn: Organizational Anonymity with Low Latency." Proceedings on Privacy Enhancing Technologies 2022, no. 3 (2022): 582–605. http://dx.doi.org/10.56553/popets-2022-0087.

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There is a growing demand for network-level anonymity for delegates at global organizations such as the UN and Red Cross. Numerous anonymous communication (AC) systems have been proposed over the last few decades to provide anonymity over the internet; however, they introduce high latency overhead, provide weaker anonymity guarantees, or are difficult to deploy at the organizational networks. Recently, the PriFi system introduced a client/relay/server model that suitably utilizes the organizational network topology and proposes a low-latency, strong-anonymity AC protocol. Using an efficient la

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31

Usui, Soichiro, Shinji Fukatsu, Eiichiro Matsumoto, Maiko Imoto, Daisuke Shirai, and Shingo Kinoshita. "Marathon × Ultra-low-latency Communication Technology." NTT Technical Review 19, no. 12 (2021): 78–84. http://dx.doi.org/10.53829/ntr202112fa10.

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32

NGUYEN, Hong-Thu, Xuan-Thuan NGUYEN, and Cong-Kha PHAM. "A Low-Latency Parallel Pipeline CORDIC." IEICE Transactions on Electronics E100.C, no. 4 (2017): 391–98. http://dx.doi.org/10.1587/transele.e100.c.391.

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33

Dong, Jialin, Kai Yang, and Yuanming Shi. "Blind Demixing for Low-Latency Communication." IEEE Transactions on Wireless Communications 18, no. 2 (2019): 897–911. http://dx.doi.org/10.1109/twc.2018.2886191.

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34

Thomas, Yannis, Merkourios Karaliopoulos, George Xylomenos, and George C. Polyzos. "Low Latency Friendliness for Multipath TCP." IEEE/ACM Transactions on Networking 28, no. 1 (2020): 248–61. http://dx.doi.org/10.1109/tnet.2019.2961759.

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35

Chan, R. P. K., O. C. S. Choy, C. F. Chan, and K. P. Pun. "A Low-Latency Asynchronous Shift Register." IEEE Transactions on Circuits and Systems II: Express Briefs 51, no. 5 (2004): 217–21. http://dx.doi.org/10.1109/tcsii.2004.824051.

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36

Friston, Sebastian, and Jim Foley. "Low-Latency Rendering With Dataflow Architectures." IEEE Computer Graphics and Applications 40, no. 3 (2020): 94–104. http://dx.doi.org/10.1109/mcg.2020.2980183.

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37

Brook, Andrew. "Low-latency distributed applications in finance." Communications of the ACM 58, no. 7 (2015): 42–50. http://dx.doi.org/10.1145/2747303.

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38

V., Chinnappa Gowda D., and Kanagavalli R. "Video semantic segmentation with low latency." TELKOMNIKA (Telecommunication Computing Electronics and Control) 22, no. 5 (2024): 1147. http://dx.doi.org/10.12928/telkomnika.v22i5.25157.

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39

Knight, Thomas F. "Technologies for low latency interconnection switches." ACM SIGARCH Computer Architecture News 19, no. 1 (1991): 61–68. http://dx.doi.org/10.1145/121956.121963.

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40

Goel, Ashvin, Charles Krasic, and Jonathan Walpole. "Low-latency adaptive streaming over tcp." ACM Transactions on Multimedia Computing, Communications, and Applications 4, no. 3 (2008): 1–20. http://dx.doi.org/10.1145/1386109.1386113.

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K, Venkata Reddy, Simranjeet Singh C, Vivian Desalphine, and David Selvakumar. "A Low Latency Montgomery Modular Exponentiation." Procedia Computer Science 171 (2020): 800–809. http://dx.doi.org/10.1016/j.procs.2020.04.087.

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42

Bos, Joppe W. "Low-Latency Elliptic Curve Scalar Multiplication." International Journal of Parallel Programming 40, no. 5 (2012): 532–50. http://dx.doi.org/10.1007/s10766-012-0198-5.

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43

Horbach, Ulrich. "REDUCED LATENCY LOW FREQUENCY EQUALIZATION SYSTEM." Journal of the Acoustical Society of America 134, no. 2 (2013): 1433. http://dx.doi.org/10.1121/1.4817601.

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44

Pekmestzi, K. Z., and C. Caraiscos. "Low-latency bit-parallel systolic multiplier." Electronics Letters 29, no. 4 (1993): 367. http://dx.doi.org/10.1049/el:19930247.

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45

Yakovlev, A., A. Petrov, and L. Lavagno. "A low latency asynchronous arbitration circuit." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 3 (1994): 372–77. http://dx.doi.org/10.1109/92.311648.

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Pu, Qifan, Ganesh Ananthanarayanan, Peter Bodik, et al. "Low Latency Geo-distributed Data Analytics." ACM SIGCOMM Computer Communication Review 45, no. 4 (2015): 421–34. http://dx.doi.org/10.1145/2829988.2787505.

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47

Rezaei, Hossein, Nandana Rajatheva, and Matti Latva-Aho. "Low-Latency Multi-Kernel Polar Decoders." IEEE Access 10 (2022): 119460–74. http://dx.doi.org/10.1109/access.2022.3221742.

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48

Hildinger, Rainer, and Marco Breiling. "The DVB-SH low-latency extension." International Journal of Satellite Communications and Networking 32, no. 6 (2013): 475–84. http://dx.doi.org/10.1002/sat.1051.

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49

Wang, Jingxian, Vaishnavi Ranganathan, Jonathan Lester, and Swarun Kumar. "Ultra Low-Latency Backscatter for Fast-Moving Location Tracking." Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies 6, no. 1 (2022): 1–22. http://dx.doi.org/10.1145/3517242.

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This paper explores building an ultra-low latency and high-accuracy location tracking solution using battery-free tags. While there is rich prior work on location tracking with battery-free RFID tags and backscatter devices, these systems typically face tradeoffs with accuracy, power consumption, and latency. Such limitations make these existing solutions unsuitable for emerging applications like industrial augmented reality which requires tracking fast-moving machinery; monitoring indoor sports activities that require real-time tracking of fast-moving objects with high precision and under str

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50

Rosing, Matt, and Joel Saltz. "Low Latency Messages on Distributed Memory Multiprocessors." Scientific Programming 4, no. 1 (1995): 35–43. http://dx.doi.org/10.1155/1995/531941.

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This article describes many of the issues in developing an efficient interface for communication on distributed memory machines. Although the hardware component of message latency is less than 1 ws on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 μs. The reason for this imbalance is that the software interface does not match the hardware. By changing the interface to match the hardware more closely, applications with fine grained communication can be put on these machines. This article describes several tests p

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