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Academic literature on the topic 'LOW NOISE ADC'

Author: Grafiati
Published: 11 September 2023

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Journal articles on the topic "LOW NOISE ADC"

1

McCartney, Damien, Adrian Sherry, John O'Dowd, and Pat Hickey. "Low-noise low-drift transducer ADC." Computer Standards & Interfaces 21, no. 2 (1999): 102. http://dx.doi.org/10.1016/s0920-5489(99)91937-2.

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2

McCartney, D., A. Sherry, J. O'Dowd, and P. Hickey. "A low-noise low-drift transducer ADC." IEEE Journal of Solid-State Circuits 32, no. 7 (1997): 959–67. http://dx.doi.org/10.1109/4.597286.

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3

Ren, Si Kui, and Zhi Qun Li. "Design of Low Voltage Low Power ADC for WSN Node." Advanced Materials Research 760-762 (September 2013): 561–66. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.561.

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This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.
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4

Choi, Gyuri, Hyunwoo Heo, Donggeun You, et al. "A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier." Applied Sciences 11, no. 17 (2021): 7982. http://dx.doi.org/10.3390/app11177982.

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In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.
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5

Li, Jiamin, Qian Lv, Jing Yang, Pengcheng Zhu, and Xiaohu You. "Spectral and Energy Efficiency of Distributed Massive MIMO with Low-Resolution ADC." Electronics 7, no. 12 (2018): 391. http://dx.doi.org/10.3390/electronics7120391.

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In this paper, considering a more realistic case where the low-resolution analog-to-digital convertors (ADCs) are employed at receiver antennas, we investigate the spectral and energy efficiency in multi-cell multi-user distributed massive multi-input multi-output (MIMO) systems with two linear receivers. An additive quantization noise model is provided first to study the effects of quantization noise. Using the model provided, the closed-form expressions for the uplink achievable rates with a zero-forcing (ZF) receiver and a maximum ratio combination (MRC) receiver under quantization noise and pilot contamination are derived. Furthermore, the asymptotic achievable rates are also given when the number of quantization bits, the per user transmit power, and the number of antennas per remote antenna unit (RAU) go to infinity, respectively. Numerical results prove that the theoretical analysis is accurate and show that quantization noise degrades the performance in spectral efficiency, but the growth in the number of antennas can compensate for the degradation. Furthermore, low-resolution ADCs with 3 or 4 bits outperform perfect ADCs in energy efficiency. Numerical results imply that it is preferable to use low-resolution ADCs in distributed massive MIMO systems.
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6

ZHU, ZHANGMING, HONGBING WU, GUANGWEN YU, YANHONG LI, LIANXI LIU, and YINTANG YANG. "A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350018. http://dx.doi.org/10.1142/s0218126613500187.

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A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.
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7

Lee, Sang-Hun, and Won-Young Lee. "A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction." Sensors 22, no. 16 (2022): 6078. http://dx.doi.org/10.3390/s22166078.

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This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampling rate and optimize the power consumption of the dual-domain comparator. The proposed SAR ADC is fabricated in 180-nm CMOS technology with an area of 0.836 mm2. At a 0.6-V supply voltage and a 400-kS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.59 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.47/−0.53 LSB and +0.92/−0.64 LSB, respectively. The FoM is 10.31 fJ/conversion step with a power consumption of 2.36 μW.
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8

Xu, Daiguo, Kaikai Xu, Shiliu Xu, Lu Liu, and Tao Liu. "A System-Level Correction SAR ADC with Noise-Tolerant Technique." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850202. http://dx.doi.org/10.1142/s021812661850202x.

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A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.
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9

Ding, Wei, Heng Liu, and Tao Wu. "Optimizing for High Resolution ADC Model With Combined Architecture." International Journal of Cognitive Informatics and Natural Intelligence 14, no. 3 (2020): 118–32. http://dx.doi.org/10.4018/ijcini.2020070106.

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High resolution analog-digital conversion (ADC) is a key instrument to convert analog signals to digital signals, which is deployed in data acquisition system to match high resolution analog signals from seismometers systems. To achieve high resolution, architecture of Σ-△ oversampling or pipeline ADC architecture have following disadvantages: high power consumption, low linearity of modulators, and complex structure. This work presents a novel model architecture, which design principle is validated by mathematical formulations which combined advantages of both pipeline and Σ-△oversampling ADC architecture. By discussing the adverse effects of the whole ADC architecture with an external noise theoretically, an amended theoretical model is proposed according to the assessment result of a noise simulation algorithm. The simulation results represent that the whole performance of combined architecture is determined by the noise level of integrator and subtractor. Using these two components with a noise index no more than 10-7 V/√Hz, the resolution of the prototype can achieve a reservation of 144.5 dB.
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10

Sheng, Shuran, Peng Chen, Yuxuan Yao, Lenan Wu, and Zhimin Chen. "Atomic Network-Based DOA Estimation Using Low-Bit ADC." Electronics 10, no. 6 (2021): 738. http://dx.doi.org/10.3390/electronics10060738.

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In the direction of arrival (DOA) estimation problem, when a low-bit analog to digital converter (ADC) is used, the estimation performance severely deteriorates. In this paper, the DOA estimation problem is considered in a low-cost direction finding system with low-bit ADC. To eliminate quantization noise, we propose a novel network ADCnet, which is a composition of fully connected layers and exponential linear unit (ELU) layers, and the input signals are the received signals using low-bit ADC. After the ADCnet, an AtomicNet is also proposed to estimate the DOA from the denoised signals, where atomic vectors are corresponding to the steer vectors. A loss function considering both the reconstruction performance and the sparsity is proposed in the AtomicNet. Different from the exiting atomic norm-based methods, the proposed method can avoid an optimization problem and estimate the DOA with lower computational complexity. Simulation results show that the proposed method outperforms the existing methods in the DOA estimation performance using low-bit ADC.
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