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Cherukumudi, Dinesh. "Ultra-Low Noise and Highly Linear Two-Stage Low Noise Amplifier (LNA)." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71355.
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An ultra-low noise two-stage LNA design for cellular basestations using CMOS is proposed in this thesis work. This thesis is divided into three parts. First, a literature survey which intends to bring an idea on the types of LNAs available and their respective outcomes in performances, thereby analyze how each design provides different results and is used for different applications. In the second part, technology comparison for 0.12µm, 0.18µm, and 0.25µm technologies transistors using the IBM foundry PDKs are made to analyze which device has the best noise performance. Finally, in the third phase bipolar and CMOS-based two-stage LNAs are designed using IBM 0.12µm technology node, decided from the technology comparison. In this thesis a two-stage architecture is used to obtain low noise figure, high linearity, high gain, and stability for the LNA. For the bipolar design, noise figure of 0.6dB, OIP3 of 40.3dBm and gain of 26.8dB were obtained. For the CMOS design, noise figure of 0.25dB, OIP3 of 46dBm and gain of 26dB were obtained. Thus, the purpose of this thesis is to analyze the LNA circuit in terms of design, performance, application and various other parameters. Both designs were able to fulfill the design goals of noise figure < 1 dB, OIP3 > 40 dBm, and gain >18 dB.
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Khan, Abbas. "Optimization through Co-Simulation of Antenna, Bandpass Filter and Low-Noise Amplifier at 6-9 GHz." Thesis, Linköpings universitet, Fysik och elektroteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110575.
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Ultra-wide band (UWB) 6-9 GHz antenna, band pass filter and low-noise amplifier (LNA) optimization using co-simulation of the RF front-end. At higher frequencies, carefully conducted design methodologies are required for RF front-end parameter optimization, such as power gain and low noise figure with low power consumption.
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Pimentel, Henrique Luiz Andrade. "Projeto de um amplificador de baixo ruído em tecnologia CMOS 130nm para frequências de 50MHZ a 1GHz." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/67180.
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O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm.This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).
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Klegová, Hana. "Nízkošumové zesilovače pro pásmo 1-3 GHz." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316424.
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This masters thesis deals with low noise amplifier design for frequency range 1 GHz - 3 GHz. There is a short theoretical introduction in the first part of the thesis. There are described parameters and properties of transistors and general two-ports. Description of the noise characteristics two-ports follows. The next capture contains design of two-stage amplifiers. One of them is with a microstrip filter between stages and the second one is with combline filter on input of the amplifier. The amplifiers and the microstrip filter were designed in program ANSOFT Designer. The design of combline filter was realised in program CST Microwave Studio. Both amplifiers ware made and their properties ware compared with simulations.
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Potěšil, Dušan. "Nízkošumový zesilovač pro pásmo S." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217670.
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This work deals with design, simulation and realisation of a receiving systém of an S-band front end for satellite communication. The first part of the project is designed the low noise amplifier (LNA) with high associated gain. The basic point of the design is choice of the active device. In the present time are available the ultra low noise transistors based on the GaAs with high mobility electron. The two-stage LNA has been designed with Agilent ATF-55143. It is pseudomorphic HEMTs ,which work in an enhancement mode.These transistor do not require a negative bias voltage and have extremely good typical noise figure. The design includes an interdigital tuned band pass filter between stages. The second part of the project is search another way design circuit. There are designed two LNA with paralel coupled line filter. The first has been applied on a PTFE substrate Duroid 5880 with relative permitivity 2,2 and tg d = 0,009. The substrate FR-4 (r = 4.34) with the thickness 0.06” was used for the realization.
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Ganesan, Sivakumar. "Highly linear low noise amplifier." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5928.
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The CDMA standard operating over the wireless environment along with various other
wireless standards places stringent specifications on the RF Front end. Due to possible
large interference signal tones at the receiver end along with the carrier, the Low Noise
Amplifier (LNA) is expected to provide high linearity, thus preventing the intermodulation
tones created by the interference signal from corrupting the carrier signal.
The research focuses on designing a novel LNA which achieves high linearity without
sacrificing any of its specifications of gain and Noise Figure (NF). The novel LNA
proposed achieves high linearity by canceling the IM3 tones in the main transistor in both
magnitude and phase using the IM3 tones generated by an auxiliary transistor. Extensive
Volterra series analysis using the harmonic input method has been performed to prove the
concept of third harmonic cancellation and a design methodology has been proposed. The
LNA has been designed to operate at 900MHz in TSMC 0.35um CMOS technology. The
LNA has been experimentally verified for its functionality. Linearity is usually measured
in terms of IIP3 and the LNA has an IIP3 of +21dBm, with a gain of 11 dB, NF of 3.1 dB
and power consumption of 22.5 mW.
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Mcculloch, Mark Anthony. "Enhancing the noise performance of low noise amplifiers : with applications for future cosmic microwave background observatories." Thesis, University of Manchester, 2014. https://www.research.manchester.ac.uk/portal/en/theses/enhancing-the-noise-performance-of-low-noise-amplifiers--with-applications-for-future-cosmic-microwave-background-observatories(cd1da9b9-af7f-4bd2-a797-766c02855ab9).html.
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Low Noise Amplifiers (LNAs) are one of the most important components found in some of the radio receivers used in radio astronomy. A good LNA should simultaneously possess both a gain in excess of 25\,dB and as low a noise contribution as possible. This is because the gain is used to suppress the noise contribution of the subsequent components but the noise generated by the LNA adds directly to the noise of the overall receiver. The work presented in this thesis aimed to further enhance the noise performance through a variety of techniques with the aim of applying these techniques to the study of the polarisation of the Cosmic Microwave Background. One particular technique investigated was to cool the LNAs beyond the standard 20\,K typically used in experiments to 2\,K. In doing so it was found that the noise performance increased by between 20 and 30\% depending on the amplifier. Another technique investigated involved uniting the two technologies (MICs and MMIC) used in LNA fabrication to lower the noise performance of the LNA. Such an LNA, known as a T+MMIC LNA was successfully developed and possessed an average noise temperature of 9.4\,K and a gain in excess of 40\,dB for a 27-33\,GHz bandwidth at 8\,K physical temperature. Potential ``in field'' applications for these technologies are discussed, and a design for a variant of the T+MMIC LNA that utilises both of these technologies is presented. This particular LNA with a predicted average noise temperature of 6.8\,K for a 26-36\,GHz bandwidth, would if fabricated successfully represent the lowest noise Ka-band LNA ever reported.
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yasami, saeed. "Design and Evaluation of an Ultra-Low PowerLow Noise Amplifier LNA." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50923.
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This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW
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Aitha, Venkat Ramana, and Mohammad Kawsar Imam. "Low Noise Amplifier for radio telescope at 1 : 42 GHz." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-997.
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This is a part of the project “Radio telescope system” working at 1.42 GHz, which includes designing of patch antenna and LNA. The main objective of this thesis is to design a two stage low noise amplifier for a radio telescope system, working at the frequency 1.42 GHz. Finally our aim is to design a two stage LNA, match, connect and test together with patch antenna to reduce
the system complexity and signal loss.
The requirements to design a two stage low noise amplifier (LNA) were well studied, topics including RF basic theory, layout and fabrication of RF circuits. A number of tools are available to design and simulate low noise amplifiers but our simulation work was done using advanced design system (ADS 2004 A). The design process includes selection of a proper device, stability check of the device, biasing, designing of matching networks and layout of total design and fabrication. A lot of time has been
spent on designing of impedance matching network, fabrication and testing of the design circuits and finally a two stage low noise amplifier (LNA) was designed. After the fabrication work, the circuits were tested by the spectrum analyzer in between 9 KHz to 25 GHz frequency range. Finally the resulting noise figure 0.299 dB and gain 24.25 dB are obtained from the simulation.
While measuring the values from the fabricated circuit board, we found that bias point is not stable due to self oscillations in the amplifier stages at lower frequencies like 149 MHz for first stage and 355 MHz for second stage.
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Amoêdo, David Jorge Tiago. "A 1.2 V low noise amplifier with double feedback for high gain and low noise figure." Master's thesis, Faculdade de Ciências e Tecnologia, 2013. http://hdl.handle.net/10362/11040.
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Dissertação para obtenção do Grau de Mestre em
Engenharia Eletrotécnica e de ComputadoresIn this thesis we present a balun low noise amplifier (LNA) in which the gain is boosted using a double feedback structure. The circuit is based in a Balun LNA with noise and distortion cancellation. The LNA is based in two basic stages: common-gate (CG) and common-source (CS). We propose to replace the resistors by active loads, which have two inputs that will be used to provide the feedback (in the CG and CS stages). This proposed methodology will boost the gain and reduce the NF (Noise Figure). Simulation results, with a 130 nm CMOS technology, show that the gain is 19.65 dB and the NF is less than 2.17 dB. The total power dissipation is only 5 mW (since no extra blocks are required), leading to an FOM (Figure of Merit) of 3.13 mW-1 from a nominal 1.2 supply.
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Bandla, Atchaiah. "Highly Linear 2.45 GHz Low-Noise Amplifier Design." Thesis, Linköpings universitet, Fysik och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-119982.
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One critical component of the communication receiver of front-end system is the low-noise amplifier (LNA). For good sensitivity and dynamic range, the LNA should provide a low noise figure and maximum attainable power gain. Another concern is the linearity of the LNA. Strong signals produce intermodulation products in a frequency band close to the operating frequency that might affect the performance of the receiver. In many cases, the intermodulation products can be reduced by increasing the current through the active device. Hence, a trade-off between power consumption and linearity must be considered when designing the LNA. The thesis includes the bias network design, stability analysis, matching network design and layout design of the LNA RF module with layout simulation. The simulation has been performed using Advanced Design System (ADS) simulation software. After implementation of LNA on a PCB, the LNA is measured with the help of the power supply unit and vector network analyzer. The proposed design aim is to provide a low noise figure (NF) and high gain while maintaining the low power consumption.
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Costa, Arthur Liraneto Torres. "Inductorless balun low-noise amplifier (LNA) for RF wideband application to IEEE 802.22." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/106442.
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Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V.A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.
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Wang, Kefei. "Parameter Estimation of a High Frequency Cascode Low Noise Amplifier Model." Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-theses/1053.
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"A Low Noise Amplifier (LNA) is an important building block in the RF receiver chain. Typically the LNA should provide acceptable gain and high linearity while maintaining low noise and power consumption. To optimize these conflicting goals the so-called Cascode topology is widely used in industry. Here the gain cell is comprised of two transistors, one in common-source and the other in common gate configuration. Cascode has a number of competitive advantages over other topologies such as high output impedance that shields the input device from voltage variations at the output, good reverse isolation resulting in improved stability, and acceptable input matching. Moreover, the topology features excellent frequency characteristics. Unfortunately, a Cascode design is expensive to deploy in RF systems and it requires more careful tuning and matching. Since the design relies on many circuit components, optimization methods are generally difficult to implement and often inaccurate in their predictions. To overcome these problems, this thesis proposes a modeling environment within the Advanced Design Systems (ADS) simulator that utilized DC and RF measurements in an effort to characterize each transistor separately. The model creates an easy-to-apply design approach capable of predicting the most important circuit components of the Cascode topology. The validity of the method is tested in ADS with a realistic p-HEMT library device. The comparison between model prediction and the realistic device involves both standard transistor parameters and high-frequency parasitic effects. "
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Webber, Scott. "Design of Ultra Wideband Low Noise Amplifier for Satellite Communications." Thesis, University of North Texas, 2020. https://digital.library.unt.edu/ark:/67531/metadc1703346/.
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This thesis offers the design and improvement of a 2 GHz to 20 GHz low noise amplifier (LNA) utilizing pHEMT technology. The pHEMT technology allows the LNA to generate a boosted signal at a lower noise figure (NF) while consuming less power and achieving smooth overall gain. The design achieves an overall gain (S21) of ≥ 10 dB with an NF ≤ 2 dB while consuming ≤ 30 mA of power while using commercial off-the-shelf (COTS) components.
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Hansen, Hans Herman. "A 33 µW Sub-3 dB Noise Figure Low Noise Amplifier for Medical Ultrasound Applications." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-14178.
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The low noise amplifier is a critical part of most high performance ultrasoundreceivers, and is important for achieving high sensitivity and a wide dynamic range.By having a large gain in the low noise amplifier, the total noise of the receiversystem will be dominated by that of the amplifier. For most low noise amplifier,there is a fundamental trade–off between accuracy and power consumption, whichmakes it difficult to design micro power front–end amplifiers with excellent noiseperformance. In some cases, however, lower accuracy can be tolerated if the sourceitself is noisy. This is the case for small, high impedance sources, where the noiselevel is in the region of 18 nV/sqrt{Hz}.This thesis presents the design and simulations of a low noise amplifier instandard 180 nm CMOS suitable for use with high impedance sources. In fact,high impedance sources pose challenges on the biasing of voltage amplifiers,where maintaining high input impedance is necessary. In addition, for differentialamplifiers, implementing common–mode feedback will typically result in a significantincrease in power consumption and area overhead. To alleviate this problem, aswitched common–mode feedback scheme is implemented, that also provide highinput impedance biasing of the input transistors.In order to cope with the large dynamic range requirement inherent in manyultrasound modalities, variable gain is often used to compress the dynamic rangefor the analog front–end. Methods for adding variable gain without resulting in alarge increase in area and power consumption is therefore of huge interest in manyultrasound applications. Several methods of adding variable gain is investigated inthis thesis, and a capacitive attenuator is proposed, which causes minimum increasein noise factor, while increasing the gain range by at least 20 dB.Large scale integration of several thousands analog front–ends in a singleultrasound probe handle requires low power consumption and minimum areaoverhead for all parts of the analog front–end, including the low noise amplifier.By using a figure–of–merit based optimization technique, the designed amplifiertopology achieves an low power consumption of 17.3 μA, while maintaining a noisefactor of less than 3 dB at resonance. In addition to performing a single–ended todifferential conversion, this amplifier realizes a maximum voltage gain of 23.4 dB,with a 3 dB bandwidth of 21.5 MHz.
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Botes, Dewald Alewyn. "Wide band, low-noise amplifiers for the mid-range SKA." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/97058.
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Thesis (MEng)--Stellenbosch University, 2015.ENGLISH ABSTRACT: This thesis presents the design, construction and measurement of two wide-band LNA’s for the SKA-Mid range (350-1200 MHz). The first wide-band LNA involves the investigation of classic low noise amplifier techniques, which includes basic noise theory, stability analysis, feedback design and the development of sophisticated matching techniques for ultra wide-band performance. Final measurements show a flat gain response equal to 19 dB, with a noise figure of 1.5 dB and an output return loss of 10 dB across the entire bandwidth. A multi-path cascading concept is introduced for the second low noise amplifier design, which aims to connect two single frequency amplifiers in parallel to operate from 500 to 700 MHz. The design process involves several optimization schemes to realise the matching networks for the cascaded topology and the noise performance of the device was confirmed by using multi-port noise theory. The prototype presents significant bandwidth improvements compared to a single frequency LNA design. Excellent agreement between the simulation and measurement were obtained with a flat gain response of 20 dB across a 2:1 bandwidth, with a low noise figure of 0.95 dB and an output return loss of 13 dB across the operation bandwidth of 400 to 800 MHz.
AFRIKAANSE OPSOMMING: Hierdie tesis behandel die ontwerp, konstruksie en meting van twee wyeband laeruis versterkers vir die SKA - Mid reeks (350–1200 MHz). Die eerste wyeband laeruis versterker, ondersoek klassieke laeruis versterker tegnieke wat insluit basiese ruisteorie, stabiliteit analise, terugvoerontwerp en die ontwikkeling van gevorderde aanpassingstegnieke vir ultra wyeband werkverrigting. Finale metings het ’n plat aanwins van 19 dB, met ’n ruisfiguur van 1.5 dB en ’n uittree-refleksie koëffisiënt van -10 dB oor die hele bandwydte vertoon. ’n Multi-pad konsep word bekend gestel vir die tweede laeruis versterker. Die ontwerp het twee enkel frekwensie laeruis versterkers in parallel verbind om vanaf 500 tot 700 MHz te werk. Die ontwerp proses bevat verskeie optimalisering skemas om die aanpassings netwerke vir die kaskade topologie te realiseer. Die ruissyfer van die versterker is bevestig deur die gebruik van multi-pad ruisteorie. Die prototipe het beduidende bandwydte verbeterings vertoon in vergelyking met ’n enkel frekwensie versterker ontwerp. ’n Uitstekende ooreenkoms tussen die simulasie en meting was verkry met ’n plat aanwins van 20 dB oor ’n 2:1 bandwydte, met ’n laeruisfiguur van 0.95 dB en ’n uittree-refleksie koëffisiënt van -13 dB oor die bandwydte van 400-800 MHz.
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Woo, Sang Hyun. "Low noise RF CMOS receiver integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50127.
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The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which senses and compensates local oscillator (LO) phase mismatches, the dominant cause of flicker noise.
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Hansson, Martin. "Design of microwave low-noise amplifiers in a SiGe BiCMOS process." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1530.
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In this thesis, three different types of low-noise amplifiers (LNA’s) have been designed using a 0.25 mm SiGe BiCMOS process. Firstly, a single-stage amplifier has been designed with 11 dB gain and 3.7 dB noise figure at 8 GHz. Secondly, a cascode two-stage LNA with 16 dB gain and 3.8 dB noise figure at 8 GHz is also described. Finally, a cascade two-stage LNA with a wide-band RF performance (a gain larger than unity between 2-17 GHz and a noise figure below 5 dB between 1.7 GHz and 12 GHz) is presented.
These SiGe BiCMOS LNA’s could for example be used in the microwave receivers modules of advanced phased array antennas, potentially making those more cost- effective and also more compact in size in the future.
All LNA designs presented in this report have been implemented with circuit layouts and validated through simulations using Cadence RF Spectre.
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Jeong, Jihoon. "Low Power Merged LNA and Mixer Design for Medical Implant Communication Services." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/31152.
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The FCC allocated the spectrum of 402-405 MHz for MICS (Medical Implant Communication Services) applications in 1999. The regulations for MICS band apply to devices that support the diagnostic and/or therapeutic functions associated with implanted medical electronics. The implanted devices aid organs and control body functions of patients to support specific treatments, and monitor patients continuously so that necessary action can be taken in advance to avoid serious conditions. To enable to use MICS applications, several requirements must be satisfied. An implanted wireless device should have a small size, consume ultra-low power, and achieve the date rate of at least 200 kbps within 2 m distance. The major challenge is to realize ultra-low power devices. Thus the low-power design of the RF circuit is crucial for MICS applications as the power consumption of the wireless devices is mostly contributed by RF circuits.
This thesis investigates low-power design of an LNA and a down-conversion mixer of a receiver for MICS applications. The key idea is to stack an LNA and a mixer, while the LNA operates in the normal super-threshold region and the mixer in the sub-threshold region. In addition, a gm-boosting technique with a capacitor cross-coupled at the LNA input stage is also adopted to achieve a low noise figure (NF) and high linearity, which is critical to the overall performance of the receiver. The mixer operating in the sub-threshold region significantly reduces power dissipation and relaxes the voltage headroom without sacrificing the LNA performance. The relaxed voltage headroom enables stack of the LNA and the mixer with a low supply voltage of 1.2 V. The proposed circuit is designed in 0.18 μm RF CMOS technology. The merged LNA and mixer consumes only 1.83 mW, and achieves 21.6 dB power gain. The NF of the block is 3.55 dB at 1 MHz IF, and the IIP3 is -6.08 dBm.Master of Science
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Ondráš, Michal. "Anténa a LNA pro vícepásmový přijímač GNSS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400543.
Full textAbstract:
This project describesa microwave antenna for GNSS and low noise amplifier. Mikrostrip antenna is a modern type of antenna. This mikrostrip antenna is Dual – band antenna with circual polarization. The thesis describes how to make anantenna, what a circular polarization is, whata patch antenna is and what GNSS is. Low noise amplifier amplifies the antenna output signal.
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Logan, Nandi. "CMOS design enhancement techniques for RF receivers : analysis, design and implementation of RF receivers with component enhancement and component reduction for improved sensitivity and reduced cost, using CMOS technology." Doctoral thesis, University of Bradford, 2010. http://hdl.handle.net/10454/5418.
Full textAbstract:
Silicon CMOS Technology is now the preferred process for low power wireless
communication devices, although currently much noisier and slower than comparable
processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing
gate sizes and correspondingly higher speeds, higher Ft CMOS processes are
increasingly competitive, especially in low power wireless systems such as Bluetooth,
Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate
sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS
technology, but at a reduced operational voltage, even with thicker gate oxides as
compensation.
This thesis investigates newer techniques, both from a systems point of view and at a
circuit level, to implement an efficient transceiver design that will produce a more
sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a
starting point, the overall components and available SoC were investigated, together
with their architecture.
Two novel techniques were developed during this investigation. The first was a high
compression point LNA design giving a lower overall systems noise figure for the
receiver. The second was an innovative means of matching circuits with low Q
components, which enabled the use of smaller inductors and reduced the attenuation
loss of the components, the resulting smaller circuit die size leading to smaller and
lower cost commercial radio equipment. Both these techniques have had patents filed by the
University.
Finally, the overall design was laid out for fabrication, taking into account package
constraints and bond-wire effects and other parasitic EMC effects.
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Muhammad, Wasim. "CMOS LNA Design for Multi-Standard Applications." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7841.
Full textAbstract:
This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.
As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.
Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.
Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.
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Khamis, Safa. "Study and performance characterization of two key RF hardware subsystems: microwave divide-by-two frequency prescalers and low noise amplifiers." Thesis, Kansas State University, 2013. http://hdl.handle.net/2097/17149.
Full textAbstract:
Master of ScienceDepartment of Electrical and Computer Engineering
William B. Kuhn
This thesis elaborates on the theory and art of the design of two key RF radio hardware subsystems: analog Frequency Dividers and Low Noise Amplifiers (LNAs). Specifically, the design and analysis of two Injection Locked Frequency Dividers (ILFDs), one Regenerative Frequency Divider (RFD), and two different LNAs are documented. In addition to deriving equations for various performance metrics and topology-specific optimization criterion, measurement data and software simulations are presented to quantify several parameters of interest. Also, a study of the design of LNAs is discussed, based on three “regimes:” impedance matching, transconductance-boosting, and active noise cancelling (ANC). For the ILFDs, a study of injection-locked synchronization and phase noise reduction is offered, based on previous works. As the need for low power, high frequency radio devices continues to be driven by the mobile phone industry, Frequency Dividers that are used as prescalars in phase locked loop frequency synthesizers (PLLs) must too become capable of operation at higher frequencies while consuming little power. Not only should they be low power devices, but a wide “Locking Range” (LR) is also desired. The LR is the bandwidth of signals that a Frequency Divider is capable of dividing. As such, this thesis documents the design and analysis of two ILFDs: a Tail-ILFD and a Quench-ILFD. Both of these ILFDs are implemented on the same oscillator circuit, which consumes 2.28 mW, nominally. Measurements of the Tail and Quench-ILFDs’ LRs are plotted, including one representing the Quench-ILFD operating at “very low” power. Also, an RFD is detailed in this thesis, which consumes 410 μW. This thesis documents Locking Ranges for the Tail and Quench-ILFDs of 12% and 3.7% of 6.4 GHz respectively, during nominal operation. In “very low” power mode, the Quench-ILFD has a LR of 4.8% while consuming 219.6 μW of power. For the RFD, simulations report a LR of 16.7% while consuming 410 μW. Recently in 2011, a wideband LNA topology by Nozahi et al., which employs Partial Noise Cancelling (PNC) of the thermal noise generated by active devices, was presented and claimed to achieve a minimum and maximum NF of 1.4 dB and 1.7 dB (from 100 MHz to 2.3 GHz), while consuming 18 mW from a 1.8 V supply. This thesis details the theory, design, and simulation results of a narrowband version of this PNC LNA. In order to compare the largesignal performance of this narrowband LNA to that of a well-known implementation, an LNA employing inductive source-degeneration (referred to as a “S-L LNA”) is designed and analyzed through simulation. The PNC LNA operates at a frequency of 2.3 GHz while the S-L LNA operates at 2.8 GHz. Simulations report a NF of 1.76 dB for the PNC LNA and 2.3 dB for the SL LNA, at their respective operating frequencies. Both LNAs consume roughly 15 mW of quiescent power from a 1.8 V supply. Lastly, a case for the suspected design and layout faults, which caused fabricated versions of the RFD and two LNAs documented in this thesis to fail, is presented. First, measurements of the two LNAs are shown, which display the input impedance of the S-L LNA and the s₂₁ responses for both. Then, general layout concerns are addressed, followed by topology-specific circuit design flaws.
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Thrivikraman, Tushar. "Analysis and Design of Low-Noise Amplifiers in Silicon-Germanium Hetrojunction Bipolar Technology for Radar and Communication Systems." Thesis, Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19755.
Full textAbstract:
This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed.
In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs.
We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.
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Weststrate, Marnus. "LC-ladder and capacitive shunt-shunt feedback LNA modelling for wideband HBT receivers." Thesis, University of Pretoria, 2011. http://hdl.handle.net/2263/26615.
Full textAbstract:
Although the majority of wireless receiver subsystems have moved to digital signal processing over the last decade, the low noise amplifier (LNA) remains a crucial analogue subsystem in any design being the dominant subsystem in determining the noise figure (NF) and dynamic range of the receiver as a whole. In this research a novel LNA configuration, namely the LC-ladder and capacitive shunt-shunt feedback topology, was proposed for use in the implementation of very wideband LNAs. This was done after a thorough theoretical investigation of LNA configurations available in the body of knowledge from which it became apparent that for the most part narrowband LNA configurations are applied to wideband applications with suboptimal results, and also that the wideband configurations that exist have certain shortcomings. A mathematical model was derived to describe the new configuration and consists of equations for the input impedance, input return loss, gain and NF, as well as an approximation of the worst case IIP3. Compact design equations were also derived from this model and a design strategy was given which allows for electronic design automation of a LNA using this configuration. A process for simultaneously optimizing the circuit for minimum NF and maximum gain was deduced from this model and different means of improving the linearity of the LNA were given. This proposed design process was used successfully throughout this research. The accuracy of the mathematical model has been verified using simulations. Two versions of the LNA were also fabricated and the measured results compared well with these simulations. The good correlation found between the calculated, simulated and measured results prove the accuracy of the model, and some comments on how the accuracy of the model could be improved even further are provided as well. The simulated results of a LNA designed for the 1 GHz to 18 GHz band in the IBM 8HP process show a gain of 21.4 dB and a minimum NF of only 1.7 dB, increasing to 3.3 dB at the upper corner frequency while maintaining an input return loss below -10 dB. After steps were taken to improve the linearity, the IIP3 of the LNA is -14.5 dBm with only a small degradation in NF now 2.15 dB at the minimum. The power consumption of the respective LNAs are 12.75 mW and 23.25 mW and each LNA occupies a chip area of only 0.43 mm2. Measured results of the LNA fabricated in the IBM 7WL process had a gain of 10 dB compared to an expected simulated gain of 20 dB, however significant path loss was introduced by the IC package and PCB parasitics. The S11 tracked the simulated response very well and remained below -10 dB over the feasible frequency range. Reliable noise figure measurements could not be obtained. The measured P1dB compression point is -22 dBm. A 60 GHz LNA was also designed using this topology in a SiGe process with ƒT of 200 GHz. A simulated NF of 5.2 dB was achieved for a gain of 14.2 dB and an input return loss below -15 dB using three amplifier stages. The IIP3 of the LNA is -8.4 dBm and the power consumption 25.5 mW. Although these are acceptable results in the mm-wave range it was however found that the wideband nature of this configuration is redundant in the unlicensed 60 GHz band and results are often inconsistent with the design theory due to second order effects. The wideband results however prove that the LC-ladder and capacitive shunt-shunt feedback topology is a viable means for especially implementing LNAs that require a very wide operating frequency range and also very low NF over that range.Thesis (PhD(Eng))--University of Pretoria, 2011.
Electrical, Electronic and Computer Engineering
unrestricted
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Pabón, Armando Ayala. "Projeto de um bloco LNA-misturador para radiofrequência em tecnologia CMOS." Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-11082010-172655/.
Full textAbstract:
Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos.This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.
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Govind, Vinu. "Design of Baluns and Low Noise Amplifiers in Integrated Mixed-Signal Organic Substrates." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7208.
Full textAbstract:
The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems.
A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed.
The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.
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Janse, van Rensburg Christo. "A SiGe BiCMOS LNA for mm-wave applications." Diss., University of Pretoria, 2012. http://hdl.handle.net/2263/26501.
Full textAbstract:
A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.Dissertation (MEng)--University of Pretoria, 2012.
Electrical, Electronic and Computer Engineering
unrestricted
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Kolář, Jan. "Vstupní část přijímače pro pásmo L." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219836.
Full textAbstract:
This Master's Thesis deals with a design of L-band receiver front-end. In the concrete the receiver is designed for receiving signals of frequency band 1,3 GHz. All particular blocks from low noise amplifier to intermediate frequency amplifier and frequency doubler in LO input are described, designed and simulated in program Ansoft. The part of this Master's Thesis is aimed to construct a working front-end receiver and to measure its basic parameters.
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Saini, Kanika. "Linearity Enhancement of High Power GaN HEMT Amplifier Circuits." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/94361.
Full textAbstract:
Gallium Nitride (GaN) technology is capable of very high power levels but suffers from high non-linearity. With the advent of 5G technologies, high linearity is in greater demand due to complex modulation schemes and crowded RF (Radio Frequency) spectrum. Because of the non-linearity issue, GaN power amplifiers have to be operated at back-off input power levels. Operating at back-off reduces the efficiency of the power amplifier along-with the output power. This research presents a technique to linearize GaN amplifiers. The linearity can be improved by splitting a large device into multiple smaller devices and biasing them individually. This leads to the cancellation of the IMD3 (Third-order Intermodulation Distortion) components at the output of the FETs and hence higher linearity performance.
This technique has been demonstrated in Silicon technology but has not been previously implemented in GaN. This research work presents for the first time the implementation of this technique in GaN Technology.
By the application of this technique, improvement in IMD3 of 4 dBc has been shown for a 0.8-1.0 GHz PA (Power Amplifier), and 9.5 dBm in OIP3 (Third-order Intercept Point) for an S-Band GaN LNA, with linearity FOM (IP3/DC power) reaching up to 20.
Large-signal simulation and analysis have been done to demonstrate linearity improvement for two parallel and four parallel FETs. A simulation methodology has been discussed in
detail using commercial CAD software. A power sampler element is used to compute the IMD3 currents coming out of various FETs due to various bias currents. Simulation results show by biasing one device in Class AB and others in deep Class AB, IMD3 components of parallel FETs can be made out of phase of each other, leading to cancellation and improvement in linearity. Improvement up to 20 dBc in IMD3 has been reported through large-signal simulation when four parallel FETs with optimum bias were used.
This technique has also been demonstrated in simulation for an X-Band MMIC PA from 8-10 GHz in GaN technology. Improvements up to 25-30 dBc were shown using the technique of biasing one device with Class AB and other with deep class AB/class B. The proposed amplifier achieves broadband linearization over the entire frequency compared to state-of-the-art PA's. The linearization technique demonstrated is simple, straight forward, and low cost to implement. No additional circuitry is needed. This technique finds its application in high dynamic range RF amplifier circuits for communications and sensing applications.Doctor of Philosophy
Power amplifiers (PAs) and Low Noise Amplifiers (LNAs) form the front end of the Radio Frequency (RF) transceiver systems. With the advent of complex modulation schemes, it is becoming imperative to improve their linearity. Through this dissertation, we propose a technique for improving the linearity of amplifier circuits used for communication systems. Meanwhile, Gallium Nitride (GaN) is becoming a technology of choice for high-power amplifier circuits due to its higher power handling capability and higher breakdown voltage compared with Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and Complementary Metal-Oxide-Semiconductor (CMOS) technologies. A circuit design technique of using multiple parallel GaN FETs is presented. In this technique, the multiple parallel FETs have independently controllable gate voltages. Compared to a large single FET, using multiple FETs and biasing them individually helps to improve the linearity through the cancellation of nonlinear distortion components. Experimental results show the highest linearity improvement compared with the other state-of-the-art linearization schemes. The technique demonstrated is the first time implementation in GaN technology. The technique is a simple and cost-effective solution for improving the linearity of the amplifier circuits. Applications include base station amplifiers, mobile handsets, radars, satellite communication, etc.
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Casañas, César William Vera. "Projeto de amplificadores de baixo ruído usando algoritmos metaheurísticos." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-18072013-111332/.
Full textAbstract:
O projeto de amplificadores de baixo ruído (LNA) aparenta ser um trabalho simples pelos poucos componentes ativos e passivos que o compõe, porém a alta correlação entre os seus parâmetros de projeto dificulta muito esse trabalho. Esta dissertação apresenta uma proposta para contornar essa dificuldade: o uso de algoritmos metaheurísticos, em particular algoritmos genéticos e simulated annealing. Algoritmos metaheurísticos são técnicas avançadas que emulam princípios físicos ou naturais para resolver problemas com alto grau de complexidade. Esses algoritmos estão emergindo nos últimos anos porque têm mostrado eficiência e eficácia. São feitos neste trabalho os projetos de três LNAs, dois (LNA1 e LNA2) para sistemas com arquitetura homódine (LNA com carga capacitiva) e um (LNA3) para sistemas com arquitetura heteródine (LNA com carga resistiva) utilizando-se algoritmos genéticos e simulated annealing (recozimento simulado). Apresenta-se inicialmente a análise detalhada da configuração escolhida para os projetos (fonte comum cascode com degeneração indutiva FCCDI). A frequência de operação dos LNAs é 1,8 GHz e a fonte de alimentação de 2,0 V. Para o LNA1 e o LNA2 se atingiu uma figura de ruído de 2,8 dB e 3,2 dB, consumo de potência de 6,8 mW e 2,7 mW e ganho de tensão de 22 dB e 24 dB, respectivamente. Para LNA3 se atingiu uma figura de ruído de 3,5 dB, consumo de potência de 7,8 mW e ganho de tensão de 15,5 dB. Os resultados obtidos e comparações feitas com LNAs da literatura demonstram viabilidade e eficácia da aplicação de algoritmos metaheurísticos no projeto de LNA. Neste trabalho utilizaram-se as ferramentas ELDO (simulador de circuitos elétricos), versão 2009.1 patch1 64 bits, ASITIC (para projetar e simular os indutores), versão 03.19.00.0.0.0 e MATLAB (o toolbox fornece os algoritmos metaheurísticos), versão 7.9.0.529 R2009b. Além disso, os projetos foram desenvolvidos na tecnologia CMOS 0,35 m da AMS (Austria Micro Systems).The design of low noise amplifiers (LNA) seems to be a simple work because the small number of active and passive device that they are composes, nevertheless the high trade off of LNA parameters complicates very much the work. This research presents a proposal to contour act the obstacle: to use metaheuristic algorithms, in special genetic algorithms and simulated annealing. The metaheuristic algorithms are advanced techniques that emulate physics or natural principles to solve problems with high grade of complexity. They have been emerging in the last years because they have shown effectiveness and efficiency. In this dissertation were designed three LNAs using genetic algorithms and simulated annealing: two (LNA1 and LNA2) to homódine architecture (LNA with capacitive load) and one (LNA3) to heteródine architecture (LNA with resistive load). First it is show the detailed analysis of configuration chosen to the designs (common source cascode with inductive degeneration). The operation frequency is 1.8 GHz and power supply is 2.0 V for all LNAs. LNA1 and LNA2 reached a noise figure of 2.8 dB and 3.2 dB, a dissipation power of 6.8 mW and 2.7 mW, and a voltage gain of 22 dB and 24 dB respectively. LNA3 reached 3.5 dB of noise figure, 7.8 mW of dissipation power, and 15.5 dB of voltage gain. The results obtained and the comparisons with LNAs from the literature demonstrate that the metaheuristic algorithms show efficiency and effectiveness in the design of LNA. This study was developed with the help of the tools ELDO (electric circuit simulator) version 2009.1 patch1 64 bits, ASITIC (to design and simulate the inductors) version 03.19.00.0.0.0, and MATLAB (the toolbox provides the metaheuristic algorithms) version 7.9.0.529 R2009b. Furthermore, the designs were developed on CMOS 0.35 AMS (Austria Micro Systems) technology.
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Wang, Yu. "Design and Implementation of Fully Integrated CMOS On-chip Bandpass Filter with Wideband High-Gain Low Noise Amplifier." Wright State University / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1629373771035261.
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Ma, Rui, Martin Kreißig, and Frank Ellinger. "A Fast Switchable and Band-Tunable 5-7.5GHz LNA in 45nm CMOS SOI Technology for Multi-Standard Wake-up Radios." IEEE / Institute of Electrical and Electronics Engineers Incorporated, 2019. https://tud.qucosa.de/id/qucosa%3A35061.
Full textAbstract:
This work presents design and full implementation of a fast switchable and band-tunable 5 - 7.5 GHz low noise amplifier (LNA) in a 45nm CMOS SOI technology. The target application are wake-up receivers that employ aggressive duty cycling. Based on a cascode topology, the LNA utilizes a transformer for its 50 input matching as well as a balun with a capacitor bank to realize 8 digitally selectable bands. According to measurement results, the fabricated LNA exhibits a voltage gain of 18 - 21 dB while drawing a current of merely 2.2mA from a 1V supply. At all the 8 bands from 5 to 7.5 GHz, the input reflection coefficient lies below -8 dB, and the noise figure ranges from 7.8 to 6.2 dB. The LNA is able to settle in less than 9.5 ns
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Brundage, William D. "VLA X-Band Preparation for Voyager 2 at Neptune." International Foundation for Telemetering, 1987. http://hdl.handle.net/10150/615320.
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International Telemetering Conference Proceedings / October 26-29, 1987 / Town and Country Hotel, San Diego, CaliforniaThe Very Large Array (VLA) radio telescope, located in west-central New Mexico, obtains high-resolution radio images of astronomical objects by using Fourier aperture synthesis with 27 antennas. With the addition of X-band to its receiving capabilities by 1989, and when arrayed with the Goldstone Deep Space Communications Complex (GDSCC), the VLA will double the Deep Space Network (DSN) receiving aperture in the U. S. longitude for signals from Voyager 2 at Neptune. This paper describes the VLA and the installation of the X-band system, its operation and performance for Voyager data reception, and its capabilities for other science at X-band.
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Ahmad, Norhawati Binti. "Modelling and design of Low Noise Amplifiers using strained InGaAs/InAlAs/InP pHEMT for the Square Kilometre Array (SKA) application." Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/modelling-and-design-of-low-noise-amplifiers-using-strained-ingaasinalasinp-phemt-for-the-square-kilometre-array-ska-application(b2b50fd8-0a13-4f71-b3f0-616ee4b2a82b).html.
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The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.
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Adiseno. "Design Aspects of Fully Integrated Multiband Multistandard Front-End Receivers." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3581.
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In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components.
Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach.
The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from9.2 dB to17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuits first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.
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Madan, Anuj. "Design and reliability of high dynamic range RF building blocks in SOI CMOS and SiGe BiCMOS technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45853.
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The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layouts (that don't need process modifications). The total-ionizing dose tolerance of SOI CMOS devices has been understood with extensive measurements. Furthermore, the role of body contacts in SOI technology is understood for dynamic range performance improvement. In this work, CMOS low-noise amplifier design for high linearity WLAN applications and its integration with RF switch on the same chip is presented. The LNA and switches designed provide state-of-the-art performance in silicon based technologies. Further, the work aims to explore applications of SiGe HBT in the context of highly linear and reliable RF building blocks. The RF reliability of SiGe HBT based RF switches is investigated and compared with CMOS counterparts. The inverse-mode operation of SiGe HBT based switches is understood to give considerably higher linearity.
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Kamanzi, Janvier. "Development of a low energy cooling technology for a mobile satellite ground station." Thesis, Cape Peninsula University of Technology, 2013. http://hdl.handle.net/20.500.11838/1072.
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Thesis submitted in fulfillment of the requirements for the degree
Master of Technology:Electrical Engineering
in the Faculty ofEngineering
at the Cape Peninsula University of Technology
Supervisor:Prof MTE KAHN
Bellville
December 2013The work presented in this thesis consists of the simulation of a cooling plant for a future mobile satellite ground station in order to minimize the effects of the thermal noise and to maintain comfort temperatures onboard the same station. Thermal problems encountered in mobile satellite ground stations are a source of poor quality signals and also of the premature destruction of the front end microwave amplifiers. In addition, they cause extreme discomfort to the mission operators aboard the mobile station especially in hot seasons. The main concerns of effective satellite system are the quality of the received signal and the lifespan of the front end low noise amplifier (LNA). Although the quality of the signal is affected by different sources of noise observed at various stages of a telecommunication system, thermal noise resulting from thermal agitation of electrons generated within the LNA is the predominant type. This thermal noise is the one that affects the sensitivity of the LNA and can lead to its destruction. Research indicated that this thermal noise can be minimized by using a suitable cooling system. A moveable truck was proposed as the equipment vehicle for a mobile ground station. In the process of the cooling system development, a detailed quantitative study on the effects of thermal noise on the LNA was conducted. To cool the LNA and the truck, a 2 kW solar electric vapor compression system was found the best for its compliance to the IEA standards: clean, human and environment friendly. The principal difficulty in the development of the cooling system was to design a photovoltaic topology that would ensure the solar panels were always exposed to the sun, regardless the situation of the truck. Simulation result suggested that a 3.3 kW three sided pyramid photovoltaic topology would be the most effective to supply the power to the cooling system. A battery system rated 48 V, 41.6 Ah was suggested to be charged by the PV system and then supply the power to the vapor compression system. The project was a success as the objective of this project has been met and the research questions were answered.
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Moreno, Sergio Andrés Chaparro. "Projeto de LNAs CMOS para radiofrequência usando programação geométrica." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18082014-121213/.
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O objetivo desta dissertação é propor o projeto de amplificadores de baixo rudo (LNAs) do tipo banda estreita e banda larga em tecnologia CMOS. O projeto de LNAs de banda estreita é representado através de um método de otimização conhecido como programação geométrica. Também, neste trabalho foi projetada uma topologia para LNAs de banda larga, aplicando a programação geométrica durante a fase inicial de projeto. Os layouts de ambos os circuitos foram desenhados e fabricados usando três processos CMOS diferentes. O aumento da utilização de circuitos digitais está reduzindo e substituindo a quantidade de circuitos analógicos implementados nos sistemas atuais. Nos transceptores de radiofrequência, a maior parte dos circuitos foi substituída por circuitos digitais equivalentes. A razão para esta substituição é devido a sua escalabilidade, variações PVT (Process, Voltage and Temperature) baixas, e menor tempo de projeto, resultado de um fluxo altamente automatizado. A redução do tempo de projeto representa um time-to-market menor e custos mais baixos. No entanto, o amplificador de baixo rudo é um dos blocos de radiofrequência que permanecem principalmente no domínio analógico, tornando a redução do tempo de projeto mediante a otimização do fluxo analógico como um bom foco de estudo. O LNA deve ser capaz de receber um sinal de baixa potência e alta frequência, e amplificá-lo adicionando o menor rudo possível, mantendo o casamento de impedâncias, baixo consumo de potência, e uma linearidade adequada a fim de evitar a distorção. Nesta dissertação, a maioria das especificações de desempenho citadas são formuladas rigorosamente e descritas como um programa geométrico. Além disso, vários scripts são escritos de forma a automatizar o fluxo de projeto. A programação geométrica é considerada como uma boa opção porque se o problema de otimização tem solução, o resultado é o ponto de otimização global, e pode ser atingido rapidamente (na ordem de segundos). Para um LNA fonte comum de banda estreita, o problema de projeto é completamente formulado como um programa geométrico, e alguns parâmetros normalmente desprezados, como as não idealidades dos indutores CMOS e a capacitância portadreno do transistor MOS são considerados no projeto. O problema de otimização é resolvido em minutos e testado em cinco processos CMOS diferentes, e para diferentes frequências de operação entre 1,5 GHz e 5 GHz. Os resultados são comparados e validados através de simulações, e dois layouts de LNAs para 2,45 GHz foram desenhados, fabricados e testados usando dois processos de 0,18 mm diferentes. Neste trabalho, também foi formulado um LNA de banda larga com cancelamento de rudo, e um bloco LNA-Misturador de banda larga é projetado incluindo a programação geométrica no cálculo da impedância de entrada e o cancelamento de rudo. Os layouts de dois protótipos diferentes do bloco LNA-Misturador de banda larga, operando na faixa de frequência entre 1 GHz e 5 GHz, foram desenhados e fabricados usando um processo de 0,18 mm.This dissertation proposes the design of CMOS narrowband and wideband low noise amplifiers. The design problem of narrowband LNAs is represented as an optimization problem known as geometric programming. Furthermore, a topology for wideband LNAs is designed including the geometric programming in an early stage of the design. Both type of circuits were layouted and fabricated using three different CMOS processes. The tendency to increase the number of applications for digital-intensive circuitry, is reducing and replacing the amount of analog circuits implemented on systems nowadays. In radiofrequency transceivers, most of the circuits have been replaced by a digital-intensive counterpart. Digital circuitry is preferred over the analog one due to its scalability, low PVT (Process, Voltage and Temperature) variations, and shorter designing time result of a highly automated flow. The reduction of the designing time represents a faster time-to-market and lower costs. However, the low noise amplifier is one of the radiofrequency blocks that remain mainly in the analog domain, thus reducing its designing time by optimizing an analog design flow become a good focus of study. The LNA should be capable of receiving a low power and high frequency signal and amplify it adding the minimum noise possible, while maintaining good impedance matching, low power consumption and an adequate linearity in order to avoid distortion. In this dissertation, most of the performance parameters aforementioned are formulated rigorously and described as a geometric program. Moreover, various scripts are written in order to automate the design flow. The geometric programming is considered a good option because if the optimization problem is feasible, the result is the global optimum and can be obtained in seconds. For a common source narrowband LNA, the design problem is fully formulated as a geometric program and some parameters commonly neglected, as the CMOS inductors non-idealities and the gate-drain capacitance of MOS transistor are considered. The optimization problem is solved in minutes and tested on five different CMOS processes at different operating frequencies between 1.5 GHz and 5 GHz. The results are compared and validated through simulations, and two layouts for 2.45 GHz LNAs are drawn, fabricated and tested using two different 0.18 mm processes. In addition, a noise canceling wideband LNA is formulated, and a wideband LNA-Mixer cell is designed by including the geometric programming to estimate the input impedance matching and assure the noise cancelation. The layouts of two different prototypes of the wideband LNA-Mixer cells for the 1 GHz-5 GHz frequency band are drawn and fabricated using a 0.18 mm process.
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Park, Jinsung. "A highly linear and low flicker-noise CMOS direct conversion receiver front-end for multiband applications." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07092007-054701/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Dr. Chang-Ho Lee, Committee Member ; Dr . Kevin T Kornegay, Committee Member ; Dr. Emmanouil M Tentzeris, Committee Member ; Dr. Joy Laskar, Committee Chair ; Dr. Oliver Brand, Committee Member.
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Banerjee, Debashis. "Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53882.
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In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can adapt to multi-dimensional channel conditions, are proposed. Secondly, the thesis proves that adaptive systems can have multiple modes of operation depending upon the throughput requirements of the system. Two such modes were demonstrated: one optimizing the energy-per-bit (energy priority mode) and another achieving the lowest power consumption at the highest throughput (data priority mode). Finally, to achieve process tolerant channel adaptive operation a self-learning methodology is proposed which learns the optimal re-configuration setting for the system on-the-fly. Implications of the research are discussed and future avenues of further research are proposed.
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Mohamad, Isa Muammar Bin. "Low Noise Amplifiers using highly strained InGaAs/InAlAs/InP pHEMT for implementation in the Square Kilometre Array (SKA)." Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/low-noise-amplifiers-using-highly-strained-ingaasinalasinp-phemt-for-implementation-in-the-square-kilometre-array-ska(31b6cbae-7b7e-43fe-a612-b3555dd2263d).html.
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The Square Kilometre Array (SKA) is a multibillion and a multinational science project to build the world’s largest and most sensitive radio telescope. For a very large field of view, the combined collecting area would be one square kilometre (or 1, 000, 000 square metre) and spread over more than 3,000 km wide which will require a massive count of antennas (thousands). Each of the antennas contains hundreds of low noise amplifier (LNA) circuits. The antenna arrays are divided into low, medium and high operational frequencies and located at different positions to boost up the telescope’s scanning sensitivity.The objective of this work was to develop and fabricate fully on-chip LNA circuits to meet the stringent requirements for the mid-frequency array from 0.4 GHz to 1.4 GHz of the SKA radio astronomy telescope using Monolithic Microwave Integrated Circuit technology (MMIC). Due to the number of LNA reaching figures of millions, the fabricated circuits were designed with the consideration for low cost fabrication and high reliability in the receiver chain. Therefore, a relaxed optical lithography with Lg = 1 µm was adopted for a high yield fabrication process.Towards the fulfilment of the device’s low noise characteristics, a large number of device designs, fabrication and characterisation of InGaAs/InAlAs/InP pHEMTs were undertaken. These include optimisations at each critical fabrication steps. The device’s high breakdown and very low gate leakage characteristics were further improved by a combination of judicious epitaxial growth and manipulation of materials’ energy gaps. An attempt to increase the device breakdown voltage was also employed by incorporating Field Plate structure at the gate terminal. This yielded the devices with improvements in the breakdown voltage up to 15 V and very low gate leakage of 1 µA/mm, in addition to high transconductance (gm) characteristic. Fully integrated double stage LNA had measured NF varying from 1.2 dB to 1.6 dB from 0.4 GHz to 1.4 GHz, compared with a slightly lower NF obtained from simulation (0.8 dB to 1.1 dB) across the same frequency band.These are amongst the attractive device properties for the implementation of a fully on-chip MMIC LNA circuits demonstrated in this work. The lower circuit’s low noise characteristic has been demonstrated using large gate width geometry pHEMTs, where the system’s noise resistance (Rn) has successfully reduced to a few ohms. The work reported here should facilitate the successful implementation of rugged low noise amplifiers as required by SKA receivers.
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Erixon, Mats. "Design of a Direct-conversion Radio Receiver Front-end in CMOS Technology." Thesis, Linköping University, Department of Science and Technology, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1197.
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In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology.
Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end.
The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated.
The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.
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Onabajo, Marvin Olufemi. "Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique." Thesis, [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-2501.
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Gong, Fei. "Front End Circuit Module Designs for A Digitally Controlled Channelized SDR Receiver Architecture." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1322606039.
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Roy, Mousumi. "Front-end considerations for next generation communication receivers." Thesis, University of Manchester, 2011. https://www.research.manchester.ac.uk/portal/en/theses/frontend-considerations-for-next-generation-communication-receivers(636dc047-7772-46c3-b049-183d3af2a7bb).html.
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The ever increasing diversity in communication systems has created a demand for constant improvements in receiver components. This thesis describes the design and characterisation of front-end receiver components for various challenging applications, including characterisation of low noise foundry processes, LNA design and multi-band antenna design. It also includes a new theoretical analysis of noise coupling in low noise phased array receivers.In LNA design much depends on the choice of the optimum active devices. A comprehensive survey of the performance of low noise transistors is therefore extremely beneficial. To this end a comparison of the DC, small-signal and noise behaviours of 10 state-of-the-art GaAs and InP based pHEMT and mHEMT low noise processes has been carried out. Their suitability in LNA designs has been determined, with emphasis on the SKA project. This work is part of the first known detailed investigation of this kind. Results indicate the superiority of mature GaAs-based pHEMT processes, and highlight problems associated with the studied mHEMT processes. Two of the more promising processes have then been used to design C-band and UHF-band MMIC LNAs. A new theoretical analysis of coupled noise between antenna elements of a low noise phased array receiver has been carried out. Results of the noise wave analysis, based on fundamental principles of noisy networks, suggest that the coupled noise contribution to system noise temperatures should be smaller than had previously been suggested for systems like the SKA. The principles are applicable to any phased array receiver. Finally, a multi-band antenna has been designed and fabricated for a severe operating environment, covering the three extremely crowded frequency bands, the 2.1 GHz UMTS, the 2.4 GHz ISM and the 5.8 GHz ISM bands. Measurements have demonstrated excellent performance, exceeding that of equivalent commercial antennas aimed at similar applications.
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Hu, Xin. "RF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency and Controllable Bandwidth: Design Sythesis and Verification." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright149572725296626.
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Fadhuile-Crepy, François. "Méthodologie de conception de circuits analogiques pour des applications radiofréquence à faible consommation de puissance." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0028/document.
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Les travaux de thèse présentés se situent dans le contexte de la conception de circuits intégrés en technologie CMOS avancée pour des applications radiofréquence à très faible consommation de puissance. Les circuits sont conçus à travers deux concepts. Le premier est l'utilisation du coefficient d'inversion qui permet de normaliser le transistor en fonction de sa taille et de sa technologie, ceci permet une analyse rapide pour différentes performances visées ou différentes technologies. La deuxième approche est d'utiliser un facteur de mérite pour trouver la polarisation la plus adéquate d'un circuit en fonction de ses performances. Ces deux principes ont été utilisés pour définir des méthodes de conception efficaces pour deux blocs radiofréquence : l'amplificateur faible bruit et l'oscillateurThesis work are presented in the context of the integrated circuits design in advanced CMOS technology for ultra low power RF applications. The circuits are designed around two concepts. The first is the use of the inversion coefficient to normalize the transistor as a function of its size and its technology, this allows a quick analysis for different performances or different technologies. The second approach is to use a figure of merit to find the most appropriate polarization of a circuit based on its performance. These two principles were used to define effective design methods for two RF blocks: low noise amplifier and oscillator
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Severino, Raffaele Roberto. "Design methodology for millimeter wave integrated circuits : application to SiGe BiCMOS LNAs." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14284/document.
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Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur SiliciumThe interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver
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Abdomerovic, Iskren. "Silicon-Based PALNA Transmit/Receive Circuits for Integrated Millimeter Wave Phased Arrays." Diss., Virginia Tech, 2020. http://hdl.handle.net/10919/96333.
Full textAbstract:
Phased array element RF front ends typically use single pole double throw (SPDT) switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, the physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This work demonstrates a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multi-variable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the power amplifier (PA) and the low noise amplifier (LNA) while maximizing power transfer efficiency and minimizing dissipative losses in each (transmit or receive) mode of operation.
Three PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. The first example design in 32SOI CMOS leverages PA and LNA circuits that already include 50 Ω matching networks at both input and output. The second example design in 8XP SiGe develops the PA and LNA circuits and integrates the PA output and LNA input matching networks into the PALNA matching network that connects the PA and the LNA. The third design in 32SOI CMOS leverages the loss-aware PALNA design methodology to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes, this dissertation also presents an efficient, switch-based T/R circuit design in 32SOI CMOS technology, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.Doctor of Philosophy
In military and commercial applications, phased arrays are devices primarily used to achieve focusing and steering of transmitted or received electromagnetic energy. Phased arrays consist of many elements, each with an ability to both transmit and receive radio frequency (RF) signals. Each element incorporates a power amplifier (PA) for transmit and a low noise amplifier (LNA) for receive, which are typically connected using a single pole double throw (SPDT) switch or a circulator with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased arrays exploit the latest technological advances in circuit integration and their frequencies of operation increase, physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This dissertation provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits where the switches and circulators are replaced by carefully designed power amplifier/low-noise amplifier (PALNA) impedance matching networks. In the switchless T/R circuits, the design goals of maximum power efficiency and minimum noise in transmit and receive, respectively, are achieved through impedance matching that is optimal and low-loss in both modes of operation simultaneously. Three distinct PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. With each new design, lessons learned are leveraged and design methodologies are enhanced. The first example design leverages already available PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to guarantee optimum impedance match in receive and transmit mode of operation. The second example design develops new PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to simultaneously achieve optimum impedance matching for maximum power efficiency in transmit mode of operation and lowest noise in receive mode of operation. The third design leverages a loss-aware PALNA design methodology, a multi-variable optimization procedure, to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes with the third PALNA design, this dissertation also presents an efficient, switch-based T/R circuit design, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.