Log in

Relevant bibliographies by topics / Low power ADC / Dissertations / Theses

To see the other types of publications on this topic, follow the link: Low power ADC.

Dissertations / Theses on the topic 'Low power ADC'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'Low power ADC.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Chang, Yin-Ting Melody. "An ultra-low power SAR ADC." Thesis, University of British Columbia, 2009. http://hdl.handle.net/2429/14703.

Full text

Abstract:

Wireless sensor networks are used in variety of applications including environmental monitoring, industrial control, healthcare, home automation, traffic control, and temperature and pressure monitoring systems. Many one-time use wireless micro sensor applications require ultra-low-power devices due to the limited energy capacity and lifetime of their small-size battery. Many sensor nodes require an analog-to-digital converter (ADC) to convert the analog output of the sensor to digital for storage and/or further processing. In this work, an 8-bit ultra-low-power successive approximation regist

APA, Harvard, Vancouver, ISO, and other styles

2

Agarwal, Anuj. "Low-power current-mode ADC for CMOS sensor IC." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2706.

Full text

Abstract:

A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate with very low duty cycle due to limited energy. Ideally these sensor networks will be massive in size and dense in order to promote redundancy. In addition the networks will be collectively intelligent and adaptive. To achieve these goals, distributed sensor networks will require very small,inexpensive nodes that run for long periods of time on very little energy.

APA, Harvard, Vancouver, ISO, and other styles

3

Verma, Naveen. "An ultra low power ADC for wireless micro-sensor applications." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34462.

Full text

Abstract:

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 143-147).<br>Autonomous micro-sensor nodes rely on low-power circuits to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work pursues the design of an ultra low-power analog-to-digital converter (ADC) whose sampling rate and resolution can be scaled to dynamically recover power savings. The proposed ADC has a sampling rate of 0-100 kS/s and a resolution of either 12 or 8 bits. The design is bas

APA, Harvard, Vancouver, ISO, and other styles

4

Høye, Dag Sverre. "Optimisation of a Pipeline ADC by using a low power, high resolution Flash ADC as backend." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8924.

Full text

Abstract:

<p>Flash ADCs with resolutions from 3 to 5 bits have been implemented on a transistor level. These ADCs are to be incorporated as the backend of a higher resolution Pipeline ADC. The motivation for this work has been to see how much the resolution of this backend can be increased before the power consumption becomes to high. This is beneficial in Pipeline ADCs because the number of Pipeline stages is reduced so that the throughput delay of the Pipeline ADC is also reduced. All the Flash ADCs are implemented with the same Capacitive Interpolation-technique. This technique was found to have seve

APA, Harvard, Vancouver, ISO, and other styles

5

Sami, Abdul Wahab. "Area Efficient ADC for Low Frequency Application." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-117413.

Full text

Abstract:

Analog to digital converters (ADCs) are the fundamental building blocks in communication systems. The need to design ADCs, which are area and/or power efficient, has been common. Various ADC architectures, constrained by resolution capabilities, can be used for this purpose. The cyclic algorithmic architecture of ADC with moderate number of bits comes out to be probably best choice for the minimum area implementation. In this thesis a cyclic ADC is designed using CMOS 65 nm technology. The ADC high-level model is thoroughly explored and its functional blocks are modelled to attain the best pos

APA, Harvard, Vancouver, ISO, and other styles

6

Radhakrishnan, Venkataraman. "Design of a low power analog to digital converter in a 130nmCMOS technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

Full text

Abstract:

Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the d

APA, Harvard, Vancouver, ISO, and other styles

7

Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Full text

Abstract:

<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR

APA, Harvard, Vancouver, ISO, and other styles

8

Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Hassan, Raza Naqvi Syed. "1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.

Full text

Abstract:

<p>The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.</p><p>Of all types of ADCs the flash ADC is not only famous for its data conversion

APA, Harvard, Vancouver, ISO, and other styles

10

Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82177.

Full text

Abstract:

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (p. 195-199).<br>As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-d

APA, Harvard, Vancouver, ISO, and other styles

11

Zhang, Chenglong. "LOW-POWER LOW-VOLTAGE ANALOG CIRCUIT TECHNIQUES FOR WIRELESS SENSORS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/982.

Full text

Abstract:

This research investigates lower-power lower-voltage analog circuit techniques suitable for wireless sensor applications. Wireless sensors have been used in a wide range of applications and will become ubiquitous with the revolution of internet of things (IoT). Due to the demand of low cost, miniature desirable size and long operating cycle, passive wireless sensors which don't require battery are more preferred. Such sensors harvest energy from energy sources in the environment such as radio frequency (RF) waves, vibration, thermal sources, etc. As a result, the obtained energy is very limite

APA, Harvard, Vancouver, ISO, and other styles

12

Guo, Wei. "A low-power 10-bit 50 MS/s CMOS successive approximation register ADC." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43200.

Full text

Abstract:

An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the ad

APA, Harvard, Vancouver, ISO, and other styles

13

Aust, Carrie Ellen. "A Low-Power, Variable-Resolution Analog-to-Digital Converter." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/33737.

Full text

Abstract:

Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary

APA, Harvard, Vancouver, ISO, and other styles

14

Kandala, Veera Raghavendra Sai Mallik. "ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC." OpenSIUC, 2012. https://opensiuc.lib.siu.edu/dissertations/539.

Full text

Abstract:

Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, whic

APA, Harvard, Vancouver, ISO, and other styles

15

Nistad, Jon Helge. "Low Power Continuous-Time Delta-Sigma ADC : The robustness of finite amplifier GBW compensation." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9320.

Full text

Abstract:

<p>This paper reports on the modeling and simulation of a continuous-time delta-sigma analog to digital converter (ADC) in VHDL AMS. The ADC is intended for use in a microcontroller and is therefore underlying restrictions on power consumption. Continuous-time delta-sigma architectures are well known for their good low-power capabilities compared to discrete-time realizations. This is due to their reduced demands to the gain bandwidth product (GBW) of the internal amplifiers in the ADCs. Continuous-time ADCs often operate with GBWs in the range of the sampling frequency, fs. The ADC presented

APA, Harvard, Vancouver, ISO, and other styles

16

Shahzad, Khurram. "Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20314.

Full text

Abstract:

<p>In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.</p><p>In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective

APA, Harvard, Vancouver, ISO, and other styles

17

Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.

Full text

Abstract:

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, ty

APA, Harvard, Vancouver, ISO, and other styles

18

Itskovich, Mikhail. "Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34901.

Full text

Abstract:

The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often ta

APA, Harvard, Vancouver, ISO, and other styles

19

ZHANG, GUANGLEI ZHANG. "SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC." University of Akron / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Balasubramanian, Sidharth. "Low-voltage and low-power libraries for Medical SoCs." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1259776639.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Lindeberg, Johan. "Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Full text

Abstract:

The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In the complete measurement unit, in which the ADC is part of, different sensors will be measured. One set of these sensors are three strain gauges with weak output signals which are to be pre-amplified before being converted. The focus of the application for the ADC has been these sensors as they were considered a limiting factor. The report describes theory for the algorithmic and incremental converter as well as a hybrid converter utilizing both of th

APA, Harvard, Vancouver, ISO, and other styles

22

Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

Full text

Abstract:

Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power effici

APA, Harvard, Vancouver, ISO, and other styles

23

Sekar, Ramgopal. "LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.

Full text

Abstract:

In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show tha

APA, Harvard, Vancouver, ISO, and other styles

24

Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

Full text

Abstract:

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture. Based on this analysis, dynamic two-stage comparator is select

APA, Harvard, Vancouver, ISO, and other styles

25

Santos, Maico Cassel dos. "Adaptive low power receiver combining ADC resolution and digital baseband for wireless sensors networks based in IEEE 802.15.4 standard." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/142125.

Full text

Abstract:

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. E

APA, Harvard, Vancouver, ISO, and other styles

26

Dornelas, Helga Uchoa. "Low power SAR analog-to-digital converter for internet-of-things RF receivers." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/186015.

Full text

Abstract:

The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microproc

APA, Harvard, Vancouver, ISO, and other styles

27

Liu, Shaolong. "SAR ADCs Design and Calibration in Nano-scaled Technologies." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1073.

Full text

Abstract:

The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Amon

APA, Harvard, Vancouver, ISO, and other styles

28

Mollén, Christopher. "On Massive MIMO Base Stations with Low-End Hardware." Licentiate thesis, Linköpings universitet, Kommunikationssystem, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-130516.

Full text

Abstract:

Massive MIMO (Multiple-Input Multiple-Output) base stations have proven, both in theory and in practice, to possess many of the qualities that future wireless communication systems will require. They can provide equally high data rates throughout their coverage area and can concurrently serve multiple low-end handsets without requiring wider spectrum, denser base station deployment or significantly more power than current base stations. The main challenge of massive MIMO is the immense hardware complexity and cost of the base station—each element in the large antenna array needs to be indivi

APA, Harvard, Vancouver, ISO, and other styles

29

Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.

Full text

Abstract:

<p>This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.</p><p>The comparator is designed for time-interleaved bandpass sigma-delta ADC.</p><p>Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less

APA, Harvard, Vancouver, ISO, and other styles

30

Lee, Sang Min. "A CMOS analog pulse compressor with a low-power analog-to-digital converter for MIMO radar applications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/42875.

Full text

Abstract:

Multiple-input multiple-output (MIMO) radars, which utilize multiple transmitters and receivers to send and receive independent waveforms, have been actively investigated as a next generation radar technology inspired by MIMO techniques in communication theory. Complementary metal-oxide-semiconductor (CMOS) technology offers an opportunity for dramatic cost and size reduction for a MIMO array. However, the resulting formidable signal processing burden has not been addressed properly and remains a challenge. On the other hand, from a block-level point of view, an analog-to-digital converter (AD

APA, Harvard, Vancouver, ISO, and other styles

31

Lin, Jin-Yi, and 林晉毅. "Low Voltage Low Power SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/c8jb65.

Full text

Abstract:

博士<br>國立清華大學<br>電機工程學系<br>105<br>Analog to digital converter (ADC) plays an important role in the modern system on a chip (SoC) because it provides interfaces between the real world and the virtual digital systems. Recently, the demand on low power ADC has dramatically increased due to the growth of portable devices and environmental monitoring network. This dissertation presents three successive approximation register (SAR) ADCs with good power efficiency at low voltage. The first part of this dissertation presents an 11-bit two-step switching SAR ADC. It only requires 64 unit capacitors and

APA, Harvard, Vancouver, ISO, and other styles

32

Chai, Angelia Yolanda, and 翟芸. "A Low-Power Low-Voltage Dual-Path Pipelined ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/41878529653789855808.

Full text

Abstract:

碩士<br>國立交通大學<br>電子研究所<br>99<br>With recent application on higher speed and higher integration capability of circuits; The trend that the channel length of MOS transistor is smaller and the thinkness of gate oxide also becomes thinner. Therefore, the intrinsic gain of MOS transistor is lower and the operation voltage is also reduced. By the demand of integrate analog-to-digital converter with digital signal-processing system in the same chip (SOC), a low-power low-voltage analog-to-digital converter is an important key factor in mixed signal system nowadays. The improved Pipelined analog-to-dig

APA, Harvard, Vancouver, ISO, and other styles

33

Malachira, Bopanna Kariappa. "Low-power sampled-data dual-slope ADC /." 2007. http://proquest.umi.com/pqdweb?did=1421621561&sid=9&Fmt=2&clientId=10361&RQT=309&VName=PQD.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Chen, Yi-Ting, and 陳奕廷. "A low power 10bit 200Ms/s Pipelined ADC." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/h244uc.

Full text

Abstract:

碩士<br>國立清華大學<br>電子工程研究所<br>106<br>A 10-bit 200-MS/s pipelined analog-to-digital converter (ADC) using virtual ground reference buffer and foreground calibration technique in TSMC 0.18μm standard CMOS process technology is presented. The simulated ADC performances achieve -85 dB of Noise Level , 61.6dB of SNDR for 4.5MHz input signal. Under 1.8-V supply, the power consumption of the proposed ADC is 68.5-mW. The measured ADC performances achieve -40 dB of Noise Level, 24.8 dB of SNDR for 10MHz input signal. The chip area including I/O pads is 2.52 mm2.

APA, Harvard, Vancouver, ISO, and other styles

35

Liu, Te-Hsiang, and 劉德祥. "A Low-power 10-bit Successive Approximation ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/93018442633893142862.

Full text

Abstract:

碩士<br>國立暨南國際大學<br>電機工程學系<br>101<br>A low-power 10-bit successive approximation ADC for wireless sensor networks is proposed in this thesis. In order to achieve low power consumption, the chip operating voltage is 0.7 V, and the input is single-ended rail-to-rail voltage signals. The digital-to-analog converter employed in the ADC, using binary-weighted multilayered sandwich capacitor array, can effectively reduce the overall capacitance value and power consumption. The low-power 10-bit successive approximation ADC proposed in this thesis is designed and implemented by using TSMC 0.18 μm CMOS p

APA, Harvard, Vancouver, ISO, and other styles

36

Liu, Yu-Hsun, and 劉宇珣. "A Low Power Sub-range Successive-Approximation ADC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/29200334853561401027.

Full text

Abstract:

碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>As a result of rapidly improve in the technology, wireless communication devices become more popular in our daily life. Among various wireless communication systems, Bluetooth system plays an important role in that. Because of requirement of portable electrical products, power consumption becomes an essential criterion in the design of Analog-to-Digital Converter (ADC). This thesis presents a method combine traditional Successive-Approximation architecture with Sub-range concept. By this way, we can relieve accuracy requirement on the MSB array and heaving tot

APA, Harvard, Vancouver, ISO, and other styles

37

Huang, Cheng-Chieh, and 黃政傑. "Study on High-speed Low-power SAR ADC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65587942319732896750.

Full text

Abstract:

碩士<br>國立暨南國際大學<br>電機工程學系<br>98<br>This research proposes a high-speed and low-power DAC, which is apply to Successive Approximation ADC. Compared with general redistribution capacitor DAC which has to charge each capacitor under sampling condition, DAC proposed in this research charges only one capacitor and effectively promotes the speed. As to the reference voltage, DAC takes only half of the general one, and obviously reduces the power consumption. According to the simulation result, the designed SAR ADC can operate at 2MHz. The Signal-to-Noise and Distortion Ratio is 59.95dB when t

APA, Harvard, Vancouver, ISO, and other styles

38

Ahmed, Syed Imran. "A power scaleable and low power pipeline ADC using power resettable opamps." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=95008&T=F.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Wang, Tao. "Low-power high-resolution delta-sigma ADC design techniques." Thesis, 2012. http://hdl.handle.net/1957/29740.

Full text

Abstract:

This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the i

APA, Harvard, Vancouver, ISO, and other styles

40

Hsiao, Ming-Kai, and 蕭名開. "12-Bit low power SAR-ADC for ECG application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05793753502319870096.

Full text

Abstract:

碩士<br>淡江大學<br>電機工程學系碩士在職專班<br>99<br>With the constant improvement on highly advanced technology nowadays, under the development of the microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP) influence, Analog to Digital Converter (ADC) has become a widely used application. The request for ADC specification will therefore be strict, as a result, more research will be conducted aggressively in the industrial and academic field. In order for ADC application become extensively used and correspond to the requirement of the present electronic products, fo

APA, Harvard, Vancouver, ISO, and other styles

41

SHIH, SONG YOU, and 施松佑. "Low-Power SAR ADC Design using Capacitor-Swapping Techniques." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/m6k9x5.

Full text

Abstract:

碩士<br>國立臺灣科技大學<br>電子工程系<br>104<br>This thesis presents a 1.2-V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented and 1.2-V 12-bit 100MS/s successive approximation register analog-to-digital converter. By applying a Capacitor-Swapping Techniques that improve DAC linearity and reduce the area of DAC, so the proposed SAR ADC can achieve lower power consumption. In order to avoid using an external high frequency clock circuit to drive the ADC, asynchronous control logic is used A N-type dynamic latch comparator have high comparison speed. A bootst

APA, Harvard, Vancouver, ISO, and other styles

42

Yang, Mi-Ti, and 楊蜜迪. "Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/bu4g43.

Full text

Abstract:

碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>As the advantage of wireless communication system, the requirement for high speed sampling rate and medium resolution gradually increase. A 10-bit 1GS/s time-interleaved SAR ADC is presented in 40nm general process of CMOS technology in this thesis. This thesis proposes a low-skew bootstrap to solve the timing skew problem between channels without digital calibration. In order to improve the energy-efficiency of the sub-channel, the subranging SAR ADC is used for lowing the FOM. This time-interleaved SAR ADC achieves an ENOB of 7.9 at the conversion r

APA, Harvard, Vancouver, ISO, and other styles

43

Wu, Po-Han, and 吳柏翰. "Low Power Flash ADC With a Gm-enhancement Low-Voltage Dynamic Comparator." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/98191663524753217091.

Full text

Abstract:

碩士<br>國立東華大學<br>電機工程學系<br>103<br>Low supply voltage is a good way to achieve low power consumption. Besides, there are many applications about high-speed low-resolution analog-to-digital converter. For example: Disk Driver Front-end、High-speed Backplane、Ultrawideband Receiver and Millimeter-wave Receiver. The feature of ultra-low power is as needed as possible for portable devices. A Gm-enhancement low-voltage dynamic comparator is proposed. The speed can achieve 100 MHz at 0.6V in 0.18um CMOS process. And we realize a low-voltage low-power Flash ADC in UMC 180nm CMOS Logic &; Mixed Mode 1

APA, Harvard, Vancouver, ISO, and other styles

44

Zhang, Guangzhao. "A Low-power Pipeline ADC with Front-end Capacitor-sharing." Thesis, 2012. http://hdl.handle.net/1807/32294.

Full text

Abstract:

This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-end S/H. This work is a proof-of-concept and it concentrates on the front-end design. A comparison is conducted between a capacitor-sharing ADC and a regular ADC and as a result, the technique reduces the power consumption in the front-end S/H by 39%. At an input frequency of 9.53 MHz and a sampling

APA, Harvard, Vancouver, ISO, and other styles

45

Tsai, Wei-Chin, and 蔡維晉. "Signal-Feature-Aware Low-Power SAR-ADC for Biomedical Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23212178289065880062.

Full text

Abstract:

碩士<br>國立中正大學<br>電機工程研究所<br>100<br>This thesis presented a Signal-Feature-Aware Low-Power SAR-ADC for Biomedical Applications in NTC 0.35μm 2P3M CMOS process. This thesis presented a SAR algorithms use manually or automatically detect the signal type selection algorithm, the algorithm is divided into binary search algorithm and moving binary search algorithm, select the applicable algorithm based on the speed of the signal to achieve low power consumption. Simulation results show that the SNDR and ENOB of the SA-ADC with an input frequency of 139Hz under sampling frequency of 10kHz are 72.01dB

APA, Harvard, Vancouver, ISO, and other styles

46

Chuang, Yu-Wei, and 莊郁暐. "A Low Power Pipeline ADC Using Time-Domain Transfer Technique." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/20038403707009700376.

Full text

Abstract:

碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in advanced process becomes more accuracy. So the time domain signal rather than voltage domain signal is used in the proposed work to do the signal process. Normally, the input signal and reference voltage is subtracted in voltage domain. In this thesis, the subtraction is realized in time domain to avoid

APA, Harvard, Vancouver, ISO, and other styles

47

Meng-FaYang and 楊孟法. "A 10-bit 27-MS/s Low Power SAR ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/10968295848672801404.

Full text

Abstract:

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>98<br>This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed ADC. The average switching energy of the capacitor array can be reduced by 81.3% compared to the conventional switching method. The designed ADC is fabricated in TSMC 0.18-μm 1P6M CMOS technology, and occupies 0.205 mm x 0.31 mm core areas. The total chip draws 1.21 mW from 1.8-V power supply at 27-MS/s s

APA, Harvard, Vancouver, ISO, and other styles

48

Lee, Ying-Ju, and 李映儒. "A low-power low-cost OOK transceiver and a high speed low- power SAR ADC for Powerline communication system." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/23354092905878762006.

Full text

Abstract:

碩士<br>國立臺灣大學<br>電子工程學研究所<br>103<br>This dissertation proposes a pre-switching technique for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs), and a low-power and low-cost On-Off Keying(OOK) transceiver for powerline communication (PLC) system. The pre-switching method speeds up the SAR ADC. The OOK modulation not only save the power consumption but also save the area cost. Furthermore, the OOK transceiver improves the reliability of PLC system. A 10-bit 100MS/s SAR ADC with pre-switching method was implemented in TSMC 90nm CMOS technology.

APA, Harvard, Vancouver, ISO, and other styles

49

Wang, Robert. "A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=95049&T=F.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Liang, Joshua. "A Frequency-scalable 14-bit ADC for Low Power Sensor Applications." Thesis, 2009. http://hdl.handle.net/1807/18802.

Full text

Abstract:

In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, class AB opamps are used. The design was fabricated in 0.18um CMOS and occupies an area of 0.35mm2. Operating at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83uW. In incremental mode, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 89dB peak SNDR while operating from 1.67S/s to 1

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!