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Journal articles on the topic 'Low power ADC'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

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1

Syong Lai, Jyun, and Zhi Ming Lin. "A 6-bit 2GS/s Low Power Flash ADC." International Journal of Engineering and Technology 4, no. 4 (2012): 369–71. http://dx.doi.org/10.7763/ijet.2012.v4.386.

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2

Arias, J., V. Boccuzzi, L. Quintanilla, et al. "Low-power pipeline ADC for wireless LANs." IEEE Journal of Solid-State Circuits 39, no. 8 (2004): 1338–40. http://dx.doi.org/10.1109/jssc.2004.831477.

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3

Quiquempoix, V., P. Deval, A. Barreto, et al. "A Low-Power 22-bit Incremental ADC." IEEE Journal of Solid-State Circuits 41, no. 7 (2006): 1562–71. http://dx.doi.org/10.1109/jssc.2006.873891.

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4

Arifuddin Sohel, Mohammed. "Design of Low Power Sigma Delta ADC." International Journal of VLSI Design & Communication Systems 3, no. 4 (2012): 67–80. http://dx.doi.org/10.5121/vlsic.2012.3407.

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5

Ren, Si Kui, and Zhi Qun Li. "Design of Low Voltage Low Power ADC for WSN Node." Advanced Materials Research 760-762 (September 2013): 561–66. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.561.

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This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

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6

ZHU, ZHANGMING, WEITIE WANG, YUHENG GUAN, et al. "A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC." Journal of Circuits, Systems and Computers 22, no. 07 (2013): 1350061. http://dx.doi.org/10.1142/s0218126613500618.

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A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

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7

Molaei, Hasan, Khosrow Hajsadeghi, and Ata Khorami. "Design of low power comparator-reduced hybrid ADC." Microelectronics Journal 79 (September 2018): 79–90. http://dx.doi.org/10.1016/j.mejo.2018.07.005.

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8

Tauqeer, T., J. Sexton, J. Sly, and M. Missous. "Low power, GHz class ADC for broadband applications." Materials Science in Semiconductor Processing 11, no. 5-6 (2008): 402–6. http://dx.doi.org/10.1016/j.mssp.2008.11.011.

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9

Ajanya, M. P., and George Tom Varghese. "Low Power Wallace Tree Encoder For Flash ADC." IOP Conference Series: Materials Science and Engineering 396 (August 29, 2018): 012042. http://dx.doi.org/10.1088/1757-899x/396/1/012042.

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10

Rohini, Kodidela, AG Vaishibha, and S. Ananiah Durai. "Low Power Self disabling Comparator for Asynchronous ADC." Journal of Physics: Conference Series 1716 (December 2020): 012042. http://dx.doi.org/10.1088/1742-6596/1716/1/012042.

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11

Mithila, Ayyavoo, Lavanya A, Nithyashree A.R., and Mithra T.R. "Design of Efficient Low Power Flash ADC Using TIQ in 45 nm Technology." Indian Journal of Science and Technology 12, no. 43 (2019): 1–4. http://dx.doi.org/10.17485/ijst/2019/v12i43/148901.

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12

Ito, Tomohiko, Takafumi Yamaji, Daisuke Kurose, and Tetsuro Itakura. "Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design." IEICE Electronics Express 1, no. 3 (2004): 63–68. http://dx.doi.org/10.1587/elex.1.63.

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13

Anand, Sunny, and V. Sulochana Verma. "Design a Low Power ADC for Blood-Glucose Monitoring." International Journal of Computer Applications 72, no. 14 (2013): 29–33. http://dx.doi.org/10.5120/12564-9020.

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14

Saberi, Mehdi, Hassan Sepehrian, Reza Lotfi, and Khalil Mafinezhad. "A low-power Successive Approximation ADC for biomedical applications." IEICE Electronics Express 8, no. 4 (2011): 195–201. http://dx.doi.org/10.1587/elex.8.195.

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15

AKÇAKAYA, Feyyaz Melih, and Günhan DÜNDAR. "Low power 3rd order feedforward sigma delta ADC design." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 25 (2017): 155–62. http://dx.doi.org/10.3906/elk-1507-204.

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16

Mukherjee, Sagar, Arka Dutta, Swarnil Roy, and Chandan Kumar Sarkar. "Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 7 (2018): 844–48. http://dx.doi.org/10.1109/tcsii.2017.2728619.

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17

Fan, Hua, Xue Han, Sekedi B. Kobenge, Qi Wei, and Huazhong Yang. "Design considerations for low power time-mode SAR ADC." International Journal of Circuit Theory and Applications 42, no. 7 (2013): 707–30. http://dx.doi.org/10.1002/cta.1885.

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18

Ahmed, Imran, Jan Mulder, and David A. Johns. "A Low-Power Capacitive Charge Pump Based Pipelined ADC." IEEE Journal of Solid-State Circuits 45, no. 5 (2010): 1016–27. http://dx.doi.org/10.1109/jssc.2010.2042524.

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19

ABDINIA, SAHEL, and MOHAMMAD YAVARI. "A LOW-VOLTAGE LOW-POWER 10-BIT 200 MS/S PIPELINED ADC IN 90 NM CMOS." Journal of Circuits, Systems and Computers 19, no. 02 (2010): 393–405. http://dx.doi.org/10.1142/s021812661000613x.

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This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. Accordin

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20

Hong, Hui, Shi Liang Li, and Shuai Liu. "Design of a Low Power Multi-Channel 10Bit SAR ADC." Applied Mechanics and Materials 513-517 (February 2014): 4576–79. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4576.

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To meet the demand of low power multi-channel ADCs, a 10bit 4-channels SAR ADC using CSMC 0.35um 3.3V 2P4M technology was designed. By optimizing the power dissipation of the interior comparator and the interior DAC, the designed ADC costs only 300uW under 2V single supply with a sampling rate as high as 300KS/s. Meanwhile 1024 points FFT was used with MATLAB tools to analysis and calculate the converted results of the SAR ADC and the calculated results shown the SNR is about 60dB, ENOB is 9.6bit, DNL is 0.033LSB and the INL is 0.312LSB.

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21

Oh, Goonseok, and Jintae Kim. "Low Power Discrete-Time Incremental Delta Sigma ADC with Passive Integrator." Journal of the Institute of Electronics and Information Engineers 54, no. 1 (2017): 26–32. http://dx.doi.org/10.5573/ieie.2017.54.1.026.

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22

Cheng, Li, Jiao Xu, Yi Xin Zhang, and Ning Yang. "Design of High-Speed and Low-Power Two-Channel Pipeline ADC." Advanced Materials Research 328-330 (September 2011): 1820–23. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1820.

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This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between t

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23

Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversi

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24

Sarafi, Sahar, Abu Khari Bin Aain, Javad Abbaszadeh Bargoshadi, and Amin Chegini. "Pre-charge solution for low-power, area-efficient SAR ADC." IEICE Electronics Express 12, no. 20 (2015): 20150546. http://dx.doi.org/10.1587/elex.12.20150546.

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25

Venkata Krishna, O., and B. Janardhana Rao. "High-efficiency Low-power Flash ADC for High-speed Transceivers." CVR Journal of Science & Technology 5, no. 1 (2013): 62–70. http://dx.doi.org/10.32377/cvrjst0511.

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26

Li, Shouping, Jianjun Chen, Bin Liang, and Yang Guo. "Low Power SAR ADC Design with Digital Background Calibration Algorithm." Symmetry 12, no. 11 (2020): 1757. http://dx.doi.org/10.3390/sym12111757.

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This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicate

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27

Selasi, Andrew, Ernest Ofosu, and Benjamin Kommey. "A 3-Bit 10-MSps Low Power CMOS Flash ADC." Communications on Applied Electronics 7, no. 22 (2018): 21–26. http://dx.doi.org/10.5120/cae2018652796.

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28

Prasad J M, Ram, Dr B. S. Kariyappa, and Ravishankar Holla. "Design and Implementation of Flash ADC for Low Power Applications." IOSR Journal of VLSI and Signal Processing 4, no. 6 (2014): 41–46. http://dx.doi.org/10.9790/4200-04614146.

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29

Chebli, Robert, Md Hasanuzzaman, Ali Haidar, and Mohamad Sawan. "Successive-divider-line ADC dedicated to low-power medical devices." Microelectronics Journal 43, no. 10 (2012): 670–79. http://dx.doi.org/10.1016/j.mejo.2012.03.010.

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30

Zhang, Chenglong, and Haibo Wang. "Reduction of Parasitic Capacitance Impact in Low-Power SAR ADC." IEEE Transactions on Instrumentation and Measurement 61, no. 3 (2012): 587–94. http://dx.doi.org/10.1109/tim.2011.2172120.

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31

Jung, J., and S. Shin. "Low‐power time‐based ADC with alternating time‐residue amplification." Electronics Letters 52, no. 22 (2016): 1845–47. http://dx.doi.org/10.1049/el.2016.0831.

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32

Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak, and Bang-Sup Song. "A 10-b 20-Msample/s low-power CMOS ADC." IEEE Journal of Solid-State Circuits 30, no. 5 (1995): 514–21. http://dx.doi.org/10.1109/4.384164.

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33

Gonen, Burak, Shoubhik Karmakar, Robert van Veldhoven, and Kofi A. A. Makinwa. "A Continuous-Time Zoom ADC for Low-Power Audio Applications." IEEE Journal of Solid-State Circuits 55, no. 4 (2020): 1023–31. http://dx.doi.org/10.1109/jssc.2019.2959480.

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34

BANIHASHEMI, M. "A Low-Power, Small-Size 10-Bit Successive-Approximation ADC." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 4 (2005): 996–1006. http://dx.doi.org/10.1093/ietfec/e88-a.4.996.

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35

Lee, B. G., and S. G. Lee. "Input-tracking DAC for low-power high-linearity SAR ADC." Electronics Letters 47, no. 16 (2011): 911. http://dx.doi.org/10.1049/el.2011.1642.

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36

Xiumei, Yin, Wei Qi, Xu Lai, and Yang Huazhong. "A low power 12-b 40-MS/s pipeline ADC." Journal of Semiconductors 31, no. 3 (2010): 035006. http://dx.doi.org/10.1088/1674-4926/31/3/035006.

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37

Shakibaee, Fatemeh, Fereshteh Sajedi, and Mehdi Saberi. "Low‐power successive approximation ADC using split‐monotonic capacitive DAC." IET Circuits, Devices & Systems 12, no. 2 (2018): 203–8. http://dx.doi.org/10.1049/iet-cds.2017.0373.

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38

Liang, Yuhua, and Zhangming Zhu. "An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design." Journal of Circuits, Systems and Computers 27, no. 01 (2017): 1850015. http://dx.doi.org/10.1142/s0218126618500159.

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A novel energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is proposed in this paper. The average switching energy of the proposed switching scheme can be reduced by 95.3%, compared with the [Formula: see text]-based scheme. Moreover, the linearity has been also improved significantly. Employing the proposed switching scheme, a 10-bit 100[Formula: see text]kS/s SAR ADC is designed in SMIC 0.18-[Formula: see text]m CMOS process. At a 0.6-V supply, the ADC consumes 43.7[Formula: see text]nW. Consequently, the figure-of-merit (FOM) is

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39

Zhang, Shuo, Zong Min Wang, and Liang Zhou. "An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC." Applied Mechanics and Materials 598 (July 2014): 365–70. http://dx.doi.org/10.4028/www.scientific.net/amm.598.365.

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This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total curr

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40

Tong, Xingyuan, and Tiantian Sun. "Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics." VLSI Design 2016 (August 22, 2016): 1–6. http://dx.doi.org/10.1155/2016/6029254.

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Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectronics. In order to reduce the power of successive-approximation-register (SAR) ADC, an improved energy-efficient capacitor switching scheme of SAR ADC is proposed for implantable bioelectronic applications. With sequence initialization, novel logic control, and capacitive subconversion, 97.6% switching energy is reduced compared to the traditional structure. Moreover, thanks to the top-plate sampling and capacitive subconversion, 87% input-capacitance reduction can be achieved over the conventiona

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41

Babayan-Mashhadi, Samaneh, and Mona Jahangiri-Khah. "A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications." Journal of Circuits, Systems and Computers 27, no. 14 (2018): 1850230. http://dx.doi.org/10.1142/s0218126618502304.

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As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with f

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42

Khan, Sadeque Reza, and M. S. Bhat. "Low Power Data Acquisition System for Bioimplantable Devices." Advances in Electronics 2014 (December 21, 2014): 1–13. http://dx.doi.org/10.1155/2014/394057.

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Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain

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43

Kumar, Manoj, and Raj Kumar. "A Ultra Low Power 12 Bit Successive Approximation Register for Bio-Medical Applications." International Journal of Engineering & Technology 7, no. 3.16 (2018): 98. http://dx.doi.org/10.14419/ijet.v7i3.4.16192.

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Successive Approximation Register (SAR) analog to digital Converters (ADC) is favorable choice for the high resolution. As resolution of ADC increases, the no. of redundant cycles increases which increases power. So the Paper presents clock gated ADC with no redundant cycles/transition cycles for low power requirement and comparison between without Clock Gating and Clock Gated SAR. Using Simulation, Power consumption for Clock gated SAR 736.1nW at 1.8V power supply where as without Clock Gating SAR consumption is 54µW at 1.8 power supply.

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44

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are

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45

Jia, Hua-Yu, Gui-Can Chen, and Hong Zhang. "A high performance low power 12-bit 40MS/s pipelined ADC." IEICE Electronics Express 5, no. 11 (2008): 400–404. http://dx.doi.org/10.1587/elex.5.400.

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46

Kakarla, Hari Kishore. "Design of Reconfigurable Low Power Pipelined ADC for Bio-Impedance Measurement." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 4 (2020): 6760–65. http://dx.doi.org/10.30534/ijatcse/2020/374942020.

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47

Zhang, Shaozhen, Zheying Li, and Bo Ling. "Design of High-Speed and Low-Power Comparator in Flash ADC." Procedia Engineering 29 (2012): 687–92. http://dx.doi.org/10.1016/j.proeng.2012.01.024.

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48

Lange, Heiner, Sebastian Schmale, Benjamin Knoop, Dagmar Peters-Drolshagen, and Steffen Paul. "ADC Topology Based on Compressed Sensing for Low Power Brain Monitoring." Procedia Engineering 120 (2015): 315–19. http://dx.doi.org/10.1016/j.proeng.2015.08.624.

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49

Xin, Xin, Jueping Cai, Ruilian Xie, and Peng Wang. "Ultra‐low power comparator with dynamic offset cancellation for SAR ADC." Electronics Letters 53, no. 24 (2017): 1572–74. http://dx.doi.org/10.1049/el.2017.2916.

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50

Prathiba, G., and M. Santhi. "Design of low power fault tolerant flash ADC for instrumentation applications." Microelectronics Journal 98 (April 2020): 104739. http://dx.doi.org/10.1016/j.mejo.2020.104739.

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