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Dissertations / Theses on the topic 'Low-power application'
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1
Zhou, Shun. "Multi-precision reconfigurable multiplier for low power application /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20ZHOU.
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Srivastava, Amit. "Design of Ultra Low Power Transmitter for Wireless medical Application." Thesis, Linköping University, Electronic Devices, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18408.
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Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life.
In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.
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Roy, Sajib, and Md Murad Kabir Nipun. "Understanding Sub-threshold source coupled logic for ultra-low power application." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69404.
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This thesis work primarily focuses on the applicability of sub-threshold source coupled logic (STSCL) for building digital circuits and systems that run at very low voltage and promise to provide desirable performance with excellent energy savings. Sectors like bio-engineering and smart sensors require the energy consumption to be effectively very low for long battery life. Alongside meeting the ultra-low power specification, the system must also be reliable, robust, and perform well under harsh conditions. In this thesis work, logic gates are designed and analyzed, using STSCL. These gates are further used for implementation of digital subsystems in small-sized smart dust sensors which would operate at very low supply voltages and consume extremely low power. For understanding the performance of STSCL with respect to ultra-low power and energy; a seven-stage ring oscillator, a 4-by-4 array multiplier, a fifth-order FIR filter and finally a fifty-fifth-order FIR filter were designed. The subcircuits and systems have been simulated for different supply voltages, scaling down to 0.2 V, at different temperature values (-20oC and 70oC) in both 45 nm and 65 nm process technologies. The chosen architectures for the FIR filters and array multiplier were conventional and essentially taken from traditional CMOS-based designs. The simulated results are studied, analyzed and compared with same CMOS-based digital circuits. The results show on the advantage of STSCL-based digital systems over CMOS. Simulation results provide an energy consumption of 1.1388 nJ for a fifty-fifth-order FIR filter, at low temperatures (-20oC), using STSCL logic, which is comparatively less than for the corresponding CMOS logic implementation.
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Parsons, David Willard. "Toward the proper application of air power in low-intensity conflict." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA276734.
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Petrov, Peter. "Application specific embedded processor customizations for low power and high performance /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3137218.
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Nouri, Neda. "A low-phase-noise mm-wave oscillator and its application in a low-power polar transmitter." Thesis, University of British Columbia, 2011. http://hdl.handle.net/2429/39476.
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Over the past decade, there have been substantial activities as well as changes in the design of high-speed radio-frequency millimeter-wave (mm-wave) integrated transceivers and their building blocks such as oscillators, mixers, low-noise amplifiers, and power amplifiers. One of the popular mm-wave frequency bands is the 7 GHz unlicensed band available around 60 GHz, which is attractive for a variety of applications including wireless local area networks(WLANs), short-range high data-rate wireless personal area networks (WPANs), and vehicular radar. One of the critical challenges in the design of 60 GHz integrated transceivers is the local oscillator signal generation. One of the main objectives of this thesis is to present and experimentally validate techniques to achieve better phase noise for high frequency oscillators, especially for high data rate applications.
This thesis studies the phase noise performance of a new rotary-wave coupled oscillator. The presented oscillator is a traveling-wave oscillator with a reduced phase distortion. This oscillator hybridizes the standing-wave oscillator and travelling-wave oscillator to take advantage of the benefits of each structure, i.e., low phase noise and low power consumption. The structure of this circuit is based on a travelling-wave oscillator tapped with four standing-wave oscillators along a transmission line to accurately provide multiphase outputs. This oscillator produces eight phases, 45° apart from each other. A proof-of-concept prototype oscillator, fabricated in a 0.13-μm CMOS technology, provides a −17.5 dBm tone at 67 GHz and achieves a 5.2 GHz tuning range (8%) while it consumes 43.2 mW from a 1.2-V supply. The measured phase noise is −87 dBc/Hz (−102 dBc/Hz) at 1 MHz (10 MHz) offset. As an application for this type of oscillator, a circular quadrature-amplitude modulation (QAM) small-signal polar transmitter is proposed and a proof-of-concept 16-level QAM modulator is designed and simulated. In this architecture, the proposed oscillator has been combined with an 8-to-1 multiplexer and four-level variable-gain amplifier to implement the QAM transmitter. Based on the post-layout simulation results, (which are in an excellent agreement with measured results for the oscillator block) the transmitter consumes 25% less power as compared to state-of-the-art 60-GHz transmitters with comparable performance.
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Vilic, Husein. "Development And Analisis OfA Low Power Sensor Network ForA Parking Garage Application." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-378403.
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This study covers the development and analisis of A Low Power Sensor Network, Parking Garage Application. An analisis of the arduino platform is presented with a structural overview as well as the design choices made during the development of the parking garage application. This includes the analisis of power usage, sensor accuracy and sensor network communication. The entire system consists of the sensor nodes, a server and an Android application. The users are, through the application, informed wheather any vacant parking spaces are available.
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Sinangil, Mahmut E. (Mahmut Ersin). "Low-power and application-specific SRAM design for energy-efficient motion estimation." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75650.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 181-189).
Video content is expected to account for 70% of total mobile data traffic in 2015. High efficiency video coding, in this context, is crucial for lowering the transmission and storage costs for portable electronics. However, modern video coding standards impose a large hardware complexity. Hence, energy-efficiency of these hardware blocks is becoming more critical than ever before for mobile devices. SRAMs are critical components in almost all SoCs affecting the overall energy-efficiency. This thesis focuses on algorithm and architecture development as well as low-power and application-specific SRAM design targeting motion estimation. First, a motion estimation design is considered for the next generation video standard, HEVC. Hardware cost and coding efficiency trade-offs are quantified and an optimum design choice between hardware complexity and coding efficiency is proposed. Hardware-efficient search algorithm, shared search range across CU engines and pixel pre-fetching algorithms provide 4.3x area, 56x on-chip bandwidth and 151 x off-chip bandwidth reduction. Second, a highly-parallel motion estimation design targeting ultra-low voltage operation and supporting AVC/H.264 and VC-1 standards are considered. Hardware reconfigurability along with frame and macro-block parallel processing are implemented for this engine to maximize hardware sharing between multiple standards and to meet throughput constraints. Third, in the context of low-power SRAMs, a 6T and an 8T SRAM are designed in 28nm and 45nm CMOS technologies targeting low voltage operation. The 6T design achieves operation down to 0.6V and the 8T design achieves operation down to 0.5V providing ~ 2.8x and ~ 4.8x reduction in energy/access respectively. Finally, an application-specific SRAM design targeted for motion estimation is developed. Utilizing the correlation of pixel data to reduce bit-line switching activity, this SRAM achieves up to 1.9x energy savings compared to a similar conventional 8T design. These savings demonstrate that application-specific SRAM design can introduce a new dimension and can be combined with voltage scaling to maximize energy-efficiency.
by Mahmut Ersin Sinangil.
Ph.D.
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Kallel, Bilel. "Design of Inductive Power Transmission System for Low Power Application with Movable Receiver and Large Air Gap." Universitätsverlag Chemnitz, 2018. https://monarch.qucosa.de/id/qucosa%3A32975.
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Inductive power transmission is very useful, not only for systems where energy transfer should take place in hazardous, humid and wet areas, but also for mobile and very small systems. It finds today a widespread use in several fields, such as industry, automotive, medicine and smart buildings. For a good efficiency and a high-power transmission, the sending and the receiving coils should be perfectly aligned and close to each other. A misalignment between the sender and the receiver becomes unavoidable especially for systems with movable parts.
This thesis aims to improve the transmitted power, the mutual inductance, the power at the load, and consequently the power transmission efficiency in case of lateral misalignment between the sending and receiving coils and at large coil-to-coil distance. For this purpose, we adopt a multi input single output (MISO) coil system able to orientate the issued magnetic field to the receiving coil by powering the neighbouring sending coils of the active ones with a weak current in the opposite direction. Furthermore, an analytical model of the used coils and an accurate three-dimensional model of the system have been developed to calculate the induced voltage, the induced current, and the equivalent mutual inductance. Both simulation and experimental results prove that the proposed multi-coil inductive system having an hexagonal arrangement and the sending coils, which have the half diameter of the receiving coil, is able to improve significantly the transmitted power in case of lateral misalignment and big air gap. The novel MISO system reaches better efficiency beginning with an air gap of 50% of the sending coil diameter, and a misalignment of 28% of the sending coil diameter. It reaches the double of the transmitted power of the conventional two-coil inductive system at 50 mm air gap (corresponding to 166% of the sending coil diameter) and at 10 mm lateral misalignment (corresponding to 33% of the sending coil diameter).
In order to improve the equivalent mutual inductance between the primary and secondary sides and to avoid energy losses, we propose a receiver detection method using the sending coils themselves as detectors. Thereby, only the sending coils, under the receiver, are activated and the others remain switched off. For that, the peak of the AC current of the sending coils, is measured and then compared to a detection threshold. The excitation strategy of the active sending coils is optimized corresponding to the receiving coil position. The novel excitation strategy increases the mutual inductance by 85% and the induced voltage by 13% at perfect alignment and by 30% and 10% respectively at 10 mm lateral misalignment, in comparison to the MISO system without a receiver detector and coil-excitation strategy.
In order to increase the transmitted power by resonance, different system topologies have been investigated, such as series-series SS, series-parallel SP, parallel-series PS, and parallel-parallel PP topologies for different levels of load impedance. The results show that a multi-coil inductive system with parallel-parallel PP topology realizes a higher transmitted power than the other topologies for both high and low load impedance values.
The proposed multi-coil inductive system is suitable for low-power systems, such as wireless sensors and biomedical implants, but can be also applied to higher range of power at a flexible position of the receiver.Die induktive Energieübertragung ist interessant, nicht nur für Systeme, bei denen die Energieübertragung in rauen, feuchten und nassen Bereichen erfolgen soll, sondern auch für mobile und sehr kleine Systeme. Diese Art von Energieübertragung findet heute eine breite Anwendung in verschiedenen Bereichen, wie z.B. Industrie, Automobil, Medizin und intelligente Gebäude. Um eine gute Effizienz und eine hohe Energieübertragungsleistung zu realisieren, sollten die Sende- und Empfangsspulen perfekt ausgerichtet und nahe beieinander sein. Insbesondere bei Systemen mit beweglichen Teilen ist jedoch eine Fehlausrichtung zwischen Sender und Empfänger unvermeidlich. Diese Arbeit zielt darauf ab, die übertragene Leistung, die gegenseitige Induktivität, die Leistung an der Last und damit den Wirkungsgrad der Leistungsübertragung im Falle einer seitlichen Fehlausrichtung zwischen Sende- und Empfangsspule und bei großem Abstand von Spule zu Spule zu verbessern. Zu diesem Zweck wird ein Multi-Input Single-Output (MISO)-Spulensystem vorgeschlagen, das in der Lage ist, das ausgegebene Magnetfeld auf die Empfangsspule auszurichten, indem die benachbarten Spulen der aktiven Sendespulen mit einem schwachen Strom in der entgegengesetzten Richtung versorgt wird. Darüber hinaus wurde ein analytisches Modell für die verwendeten Spulen und ein genaues dreidimensionales Modell für das System entwickelt, um die induzierte Spannung, den induzierten Strom und die äquivalente gegenseitige Induktivität zu berechnen. Sowohl die Simulation als auch die experimentellen Ergebnisse belegen, dass das vorgeschlagene induktive Mehrfachspulensystem mit hexagonaler Anordnung und die Sendespulen, die den halben Durchmesser der Empfangsspule haben, in der Lage sind, die Sendeleistung bei lateraler Fehlausrichtung und großem Luftspalt deutlich zu verbessern. Das neuartige MISO-System erreicht einen besseren Wirkungsgrad, beginnend mit einem Luftspalt von 50% des Sendespulendurchmessers und einer Fehlausrichtung von 28% des Sendespulendurchmessers. Sie erreicht bei 50 mm Luftspalt (entspricht 166% des Sendespulendurchmessers) und bei 10 mm seitlichem Versatz (entspricht 33% des Sendespulendurchmessers) das Doppelte der Sendeleistung des herkömmlichen Zwei-Spulen-Induktivsystems. Um die äquivalente gegenseitige Induktivität zwischen Primär- und Sekundärseite zu verbessern und Energieverluste zu vermeiden, schlagen wir ein Verfahren zur Detektion des Empfängers vor, bei dem die Sendespulen selbst als Detektoren verwendet werden. Dabei werden nur die Sendespulen unter dem Empfänger aktiviert und die anderen bleiben ausgeschaltet. Dazu wird der Scheitelwert des Wechselstroms der Sendespulen gemessen und mit einem vorgegebenem Schwellenwert verglichen. Die Anregungsstrategie der aktiven Spulen wird entsprechend der Position der Empfangsspule optimiert. Die neuartige Anregungsstrategie erhöht die gegenseitige Induktivität um 85% und die induzierte Spannung um 13% bei perfekter Ausrichtung und um 30% bzw. 10% bei 10 mm seitlichem Versatz, im Vergleich zum MISO-System ohne Empfängerdetektor und Spulenanregungsstrategie. Um die übertragene Leistung durch Resonanz zu erhöhen, wurden verschiedene Systemtopologien untersucht, wie z.B. Serien-SS, Serien-Parallel-SP, Parallel-Series-PS und Parallel-Parallel-PP-Topologien für verschiedene Stufen der Lastimpedanz. Die Ergebnisse zeigen, dass ein MISO System mit parallel-paralleler PP-Topologie eine höhere Sendeleistung realisiert als die anderen Topologien für hohe und niedrige Last-Impedanzen. Das vorgeschlagene induktive Mehrspulensystem eignet sich für Systeme mit geringer Leistung, wie drahtlose Sensoren und biomedizinische Implantate, kann aber auch flexibler Position des Empfängers in einen höheren Leistungsbereich angewendet werden.
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Yeh, Chih-Shen. "Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/81722.
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General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary supplies in automobile, industrial and communication systems. Buck converter is a common circuit topology to fulfill step-down conversion, especially in low-power application since it is well-studied and straightforward. However, it suffers from low duty cycle under high step-down condition, and typically operates in continuous conduction mode (CCM) that generates large switching loss. On the other hand, as an extension of the buck converter, tapped-inductor (TI) buck converter has larger duty cycle while maintaining the structural simplicity. Therefore, the main objective of this thesis is to explore the potential of TI buck converter as a wide conversion range, high power density and high efficiency topology for low power application. To achieve high efficiency at switching frequency of MHz-level, synchronous conduction mode (SCM) is applied for turn-on losses elimination.
The operation principle and power stage design of SCM TI buck is first introduced. The design of high switching frequency coupled inductor is emphasized since its size plays a critical role in power density. Loss breakdown is also provided to perform a comprehensive topological study. Secondly, detailed zero-voltage-switching (ZVS) condition of SCM TI buck is derived so that the converter does not experience redundant circulating energy. The experimental results of 15-W SCM TI buck converter prototypes are provided with 90.7% of peak power stage efficiency. The size of coupled inductor is down to 116 mm3. To enhance light-load efficiency, a variable frequency control scheme based on derived ZVS conditions is implemented with the switching frequency ranging from 2 MHz to 2.9 MHz.Master of Science
General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary supplies in automobile, industrial and communication systems. Typically, the ultimate goals of general-purpose step-down converter are versatility, high efficiency and compact size. Recently, tapped-inductor (TI) buck converter is studied since it could overcome the drawback of commonly used buck converter under high step-down conversion. Therefore, the potential of TI buck converter as a general-purpose step-down converter candidate is explored in this thesis, including control method, hardware design, etc. The thesis verifies that TI buck converter could have compact size while remaining efficient and adaptable.
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Sengupta, Dipanjan. "Low power System-on-Chip design using voltage islands : from application to floorplan." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/26639.
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With the continued trend in device scaling and the ever increasing popularity of hand held
mobile devices, power has become a major bottleneck for the development of future
generation System-on-Chip devices. As the number of transistors on the SoC and the
associated leakage current increases with every technology generation, methods for reducing
both active and static power have been aggressively pursued.
Starting with the application for which the SoC is to be designed, the proposed design flow
considers numerous design constraints at different steps of design process and produces a final
floorplanned solution of the cores. Voltage Island Design is a popular method for
implementing multiple supply voltages in a SoC. Use of multiple threshold voltages with
power gating of cores is an attractive method for leakage power reduction. This thesis
addresses the design challenges of implementing multiple supply and threshold voltage on the
same chip holistically with the ultimate goal for maximum power reduction.
Specifically, given the power-state machine (PSM) of an application, the high power and low
power cores are identified first. Based on the activity of the cores, threshold voltage is
assigned to each core. The next step is to identify the suitable range of supply voltage for each
core followed by voltage island generation. A methodology of reducing the large number of
available choices to a useful set using the application PSM is developed. The cores are
partitioned into islands using a cost function that gradually shifts from a power-based
assignment to a connectivity-based one.
Additional design constraints such as power supply noise and floorplan constraints can offset
the possible power savings and thus are considered early in the design phase. Experimental
results on benchmark circuits prove the effectiveness of the proposed methodology. On
average, the use of multiple VT and power gating can reduce almost 20% of power compared
to single VT. A proper choice of supply voltages leads to another 4% reduction in power.
Compared to previous methods, the proposed floorplanning technique on average offers an
additional 10% power savings, 9% area improvement and 2.4X reduction in runtime.
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Mandlekar, Anup Shrikant. "An Application Framework for a Power-Aware Processor Architecture." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34484.
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The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency,
was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software
applications to test the architecture performance. The application framework is integrated
with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable
for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.Master of Science
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Ahn, Minsik. "Design and Analysis of High Power and Low Harmonic for Multi Band Wireless Application." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19712.
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The objective of this research is to demonstrate the feasibility of the implementation of low-cost, small-size, and high power RF front ends using CMOS technology which has been known not to be suitable for high-power applications due to its material characteristic.
One part of this research focuses on developing GaAs switches for multi band and multi mode high power applications.
The development of RF front end switches for high power applications using CMOS technology is very challenging in that the characteristics of CMOS technology such as low breakdown voltages, slow electron mobility and existence of substrate junction diodes are limiting power handling capability of CMOS technology. Various topologies of CMOS switches have been employed in implementing high power RF front end CMOS switches in order to overcome material limitations of CMOS technology in high power applications. Based on measurement data such as power handling capability and S-parameters of fabricated CMOS switches, the feasibility of use of CMOS technology in high power RF antenna switch design has been studied, and novel methods of designing CMOS switches to improve the power handling capability without compensating S-parameter performance are proposed.
As a part of this research, multi-band and multi-mode power switches using GaAs technology are fabricated and tested for use of the commercial applications such as handsets covering GSM, PCS/DCS, and UMTS bands. Current commercial RF switch products demand small size, low cost and low voltage control as the number of wireless standards integrated in a single application increases. This research provides a solution for commercial products which can meet all the specifications as well as needs required in the wireless market.
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Gerlach, Lukas [Verfasser]. "KAVUAKA: A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids / Lukas Gerlach." Hannover : Gottfried Wilhelm Leibniz Universität, 2021. http://d-nb.info/1230550674/34.
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Burrell, Tina R. "An alternating direction search algorithm for low dimensional optimization : an application to power flow /." This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-12162009-020216/.
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Burrell, Tinal R. "An alternating direction search algorithm for low dimensional optimization: an application to power flow." Thesis, Virginia Tech, 1993. http://hdl.handle.net/10919/46240.
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Presented in this paper is a scheme for minimizing the cost function of a three-source technique to arrive at an approximation point (I,J) that is within one unit of the true minimum. The Line-Step algorithm is applied to several systems and is also compared to other minimization techniques, including the Equal Incremental Loss Algorithm. Variations are made on the Line-Step Algorithm for faster convergence and also to handle inequality constraints.Master of Science
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Sami, Abdul Wahab. "Area Efficient ADC for Low Frequency Application." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-117413.
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Analog to digital converters (ADCs) are the fundamental building blocks in communication systems. The need to design ADCs, which are area and/or power efficient, has been common. Various ADC architectures, constrained by resolution capabilities, can be used for this purpose. The cyclic algorithmic architecture of ADC with moderate number of bits comes out to be probably best choice for the minimum area implementation. In this thesis a cyclic ADC is designed using CMOS 65 nm technology. The ADC high-level model is thoroughly explored and its functional blocks are modelled to attain the best possible performance. In particular, the nonlinearities which affect the cyclic/algorithmic converter are discussed. This ADC has been designed for built-in-self-testing (BiST) on a chip. It is only functional during the testing phase, so power dissipation is not a constraint while designing it. As it is supposed to be integrated as an extra circuitry on a chip, its area really matters. The ADC is designed as 10-bit fully differential switch-capacitor (SC) circuit using 65nm CMOS process with 1.2V power supply. A two stage Operational Transconductance Amplifier (OTA) is used in this design to provide sufficient voltage gain. The first stage is a telescopic OTA whereas the second is a common source amplifier. The bottom plate sampling is used to minimize the charge injection effect which is present in the switches.
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Yassin, Yahya H. "ULTRA LOW POWER APPLICATION SPECIFIC INSTRUCTION-SET PROCESSOR DESIGN : for a cardiac beat detector algorithm." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9914.
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High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.
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al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
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Li, X. "Design of the low power stirling engine : Possible application to irrigation in rural areas of China." Thesis, University of Reading, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233701.
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Prince-Pike, Arrian. "Power characterisation of a Zigbee wireless network in a real time monitoring application." Click here to access this resource online, 2009. http://hdl.handle.net/10292/800.
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Zigbee is a relatively new wireless mesh networking standard with emphasis on low cost and energy conservation. It is intended to be used in wireless monitoring and control applications such as sensors and remotely operated switches where the end devices are battery powered. Because it is a recent technology there is not sufficient understanding on how network architecture and configuration affect power consumption of the battery powered devices. This research investigates the power consumption and delivery ratio of Zigbee wireless mesh and star networks for a single sink real time monitoring system at varying traffic rates and the beacon and non beacon mode operation of its underlying standard IEEE 802.15.4 in the star network architecture. To evaluate the performance of Zigbee, the network operation was simulated using the simulation tool NS-2. NS-2 is capable of simulating the entire network operation including traffic generation and energy consumption of each node in the network. After first running the simulation it was obvious that there were problems in the configuration of the simulator as well as some unexpected behaviour. After performing several modifications to the simulator the results improved significantly. To validate the operation of the simulator and to give insight on the operation of Zigbee, a real Zigbee wireless network was constructed and the same experiments that were conducted on the simulator were repeated on the Zigbee network. The research showed that the modified simulator produced good results that were close to the experimental results. It was found that the non beacon mode of operation had the lowest power consumption and best delivery ratio at all tested traffic rates. The operation of Zigbee mesh and star networks were compared to the results for IEEE 802.15.4 star networks in non beacon mode which revealed that the extra routing traffic sent by the Zigbee networking layers does contribute significantly to the power consumption, however even with the extra routing traffic, power consumption is still so low that it the battery life of the device would be limited by the shelf life of the battery, not by the energy consumption of the device. This research has successfully achieved its objectives and identified areas for future development. The simulator model for NS-2 could be improved to further increase the accuracy of the results as well as include the Zigbee routing layers and the experimental results could be improved by a more accurate power consumption data acquisition method.
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Bin, Mohd Rozlan Mohd Helmy Hakimie. "DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications." Thesis, Brunel University, 2017. http://bura.brunel.ac.uk/handle/2438/16009.
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This thesis presents a new DC/AC inverter circuit which is based on a switched-capacitor circuit topology with reduced components (power switch and capacitor) count for low power applications. The proposed circuit has distinct features of both voltage boost-up and near sinusoidal (multi-level/staircase) AC output voltage. The main idea is to utilise a simple circuit technique called resonant-based Double Switch Single Capacitor Switched-Capacitor (DSSC SCC) with variable duty cycle Pulse Width Modulation (PWM) control technique in such a way that multi-level voltage can be realised across a capacitor. In order to show the superiority of the applied technique, comparisons with other techniques/circuits configurations are presented. The circuit technique can significantly reduce the number of multiple stages of switched-capacitor circuit cells of the recent switched-capacitor multi-level inverter topology. The proposed inverter (with integrated DSSC SCC technique) can generate a line-frequency with 13-levels near sinusoidal AC output voltage with low total harmonics distortion. The output voltage can be achieved with the least number of components use and only a single DC source is used as an input. The proposed inverter topology is also reviewed against other inverter-based switched-capacitor circuit topology and the well-known multi-level inverter topology. The proposed inverter has shown a tremendous reduction in the total harmonics distortion and circuit component count in comparison with the recent Switched-Capacitor Boost multi-level inverter and the classical Cascaded H-Bridge multi-level inverter. Mathematical analysis shows the design of the proposed inverter and PSPICE simulation result to verify the design is also presented. The practical experiment implementation of the proposed system is presented and proves the correct operation of the proposed inverter topology by showing consistency between simulation results and practical results.
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Zhang, Zhiye. "Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/28902.
Full textAbstract:
Die attachment is one of the most important processes in the packaging of power semiconductor devices. The current die-attach materials/techniques, including conductive adhesives and reflowed solders, can not meet the advance of power conversation application. Silver paste sintering has been widely used in microelectronics and been demonstrated the superior properties. The high processing temperature, however, prevents its application of interconnecting power semiconductor devices. This research focuses processing and characterization of micron-scale and nanoscale silver paste for power semiconductor devices attachment.
Lowering the processing temperature is the essential to implement sintering silver paste for power semiconductor devices attachment. Two low-temperature sintering techniques - pressure-assisted sintering micro-scale silver paste and sintering nanoscale silver paste without external pressure - were developed. With the large external pressure, the sintering temperature of micro-scale silver paste can be significantly lowered. The experimental results show that by using external pressure (>40MPa), the commercial micro-scale silver paste can be sintered to have eighty percent relative density at 240oC, which is compatible with the temperature of solder reflowing. The measured properties including electrical conductivity, thermal conductivity, interfacial thermal resistance, and the shear strength of sintered silver joints, are significantly better than those of the reflowed solder layer. Given only twenty percent of small pores in the submicron range, the reliability of the silver joints is also better than that of the solder joints under the thermal cycled environment. The large external pressure, however, makes this technique difficult to automatically implement and also has a potential to damage the brittle power semiconductor devices.
Reducing silver particles in the paste from micro-size to nanoscale can increases the sintering driving force and thus lowers the sintering temperature. Several approaches were developed to address sintering challenges of nanoscale silver particles, such as particles aggregation and/or agglomeration, and non-densification diffusion at low temperature. These approaches are : nanoscale silver slurry, instead of dry silver powder, is used to keep silver particles stable and prevent their aggregation. Ultrasonic vibration, instead of conventional ball milling, is applied to disperse nanoscale silver particles in the paste from to avoid from agglomerating. Selected organics in the paste are applied to delay the onset of mass-diffusion and prevent non-densification diffusion at low temperature. The measured results show that with heat-treatment at 300oC within one hour, the sintered nanoscale silver has significantly improved electrical and thermal properties than reflowed solders. The shear strength of sintered silver interconnection is compatible with that of solder.
The low-temperature sinterable nanoscale silver paste was applied to attach the bare Silicon carbide (SiC) schottky barrier diode (SBD) for high temperature application. Limited burn-out path for organics in the silver layer challenges the sintering die-attach. This difficulty was lessened by reducing organics ratio in the silver paste. The effects of die-size and heating rate on sintering die-attach were also investigated. The single chip packaging of SiC SBD was fabricated by sintering die-attach and wire-bonding. The tested results demonstrate that the sintering nanoscale silver paste can be applied as a viable die-attach solution for high-temperature application.Ph. D.
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Gomez, Quinones Jose. "Design and implementation of an application specific multi-channel stimulator for electrokinetically-driven microfluidic devices." Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENT104/document.
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This dissertation presents the design and implementation of a 16-channel sinusoidal generator to stimulate microfluidic devices that use electrokinetic forces to manipulate particles. The generator has both, independent frequency and independent amplitude control for each channel. The stimulation system is based upon a CMOS application specific (ASIC) device developed using 0.35¦Ìm technology. Several generator techniques were compared based on frequency range, total harmonic distortion (THD), and on-chip area. The best alternative for the microfluidic applications is based in a triangle-to-sine converter and presents a frequency range of 8kHz to 21MHz, an output voltage range of 0V to 3.1VPP, and a maximum THD of 5.11%. The fabricated device, has a foot- print of 1560¦Ìm¡Á2030¦Ìm. The amplitude of the outputs is extended using an interface card, achieving voltages of 0V to 15VPP. The generator functionality was tested by performing an experimental set-up with particle trapping. The set-up consisted of a micromachined channel with embedded electrodes configured as two electrical ports located at different positions along the channel. By choosing specific amplitude and frequency values from the generator, different particles suspended in a fluid were simultaneously trapped at different ports. The multichannel stimulator presented here can be used in many microfluidic experiments and devices where particle trapping, separation and characterization is desiredThis dissertation presents the design and implementation of a 16-channel sinusoidal generator to stimulate microfluidic devices that use electrokinetic forces to manipulate particles. The generator has both, independent frequency and independent amplitude control for each channel. The stimulation system is based upon a CMOS application specific (ASIC) device developed using 0.35¦Ìm technology. Several generator techniques were compared based on frequency range, total harmonic distortion (THD), and on-chip area. The best alternative for the microfluidic applications is based in a triangle-to-sine converter and presents a frequency range of 8kHz to 21MHz, an output voltage range of 0V to 3.1VPP, and a maximum THD of 5.11%. The fabricated device, has a foot- print of 1560¦Ìm¡Á2030¦Ìm. The amplitude of the outputs is extended using an interface card, achieving voltages of 0V to 15VPP. The generator functionality was tested by performing an experimental set-up with particle trapping. The set-up consisted of a micromachined channel with embedded electrodes configured as two electrical ports located at different positions along the channel. By choosing specific amplitude and frequency values from the generator, different particles suspended in a fluid were simultaneously trapped at different ports. The multichannel stimulator presented here can be used in many microfluidic experiments and devices where particle trapping, separation and characterization is desired
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Ma, Ning. "Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing." Doctoral thesis, KTH, Industriell och Medicinsk Elektronik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174896.
Full textAbstract:
The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lowering supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific integrated circuits (ASICs) obtain high energy efficiency at the cost of low flexibility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency. To provide both high energy efficiency and flexibility, this dissertation explores the ultra-low-power design of application-specific instruction-set processors (ASIP) for ubiquitous sensing and computing. Two application scenarios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are implemented in the proposed ASIPs. Multimedia stream processing for human-computer interaction is always featured with high data throughput. To design processors for networked multimedia streams, customizing application-specific accelerators controlled by the embedded processor is exploited. By abstracting the common features from multiple coding algorithms, video decoding accelerators are implemented for networked multi-standard multimedia stream processing. Fabricated in 0.13 $\mu$m CMOS technology, the processor running at 216 MHz is capable of decoding real-time high-definition video streams with power consumption of 414 mW. When even higher throughput is required, such as in multi-view video coding applications, multiple customized processors will be connected with an on-chip network. Design problems are further studied for selecting the capability of single processors, the number of processors, the capacity of communication network, as well as the task assignment schemes. In the IoT scenario, low processing throughput but high energy efficiency and adaptability are demanded for a wide spectrum of devices. In this case, a tile processor including a multi-mode router and dual cores is proposed and implemented. The multi-mode router supports both circuit and wormhole switching to facilitate inter-silicon extension for providing on-demand performance. The control-centric dual-core architecture uses control words to directly manipulate all hardware resources. Such a mechanism avoids introducing complex control logics, and the hardware utilization is increased. Programmable control words enable reconfigurability of the processor for supporting general-purpose ISAs, application-specific instructions and dedicated implementations. The idea of reducing global data transfer also increases the energy efficiency. Finally, a single tile processor together with network of bare dies and network of packaged chips has been demonstrated as the result. The processor implemented in 65 nm low leakage CMOS technology and achieves the energy efficiency of 101.4 GOPS/W for each core.QC 20151009
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Zhou, Yang. "Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation." Thesis, Strasbourg, 2014. http://www.theses.fr/2014STRAE021/document.
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Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux élevé. Un nouveauconcept pour l’identification de l’espèce des particules proposé dans la présente étude, est basésur l'analyse des amas de particules déclenchés. Pour valider ce nouveau concept, un capteur detaille complet, qui comprend la matrice de pixel sensible aux particules ionisés signal, une chaînede traitement du signal analogique, un convertisseur analogue numérique de 3 bits, et untraitement du signal numérique a été conçu dans un processus de 0.35 μm. Le capteur sortiedirectement des informations de flux à travers 4 canaux avec un débit de données très faible(80 bps) et dissipation d’énergie minimale (~ 100 mW). Chaque canal représente particules avecdifférentes espèces et les énergies. La densité maximum de flux mesurable est jusqu'à 108particules/cm2/s (coups s'accumulent < 5%). Un prototype à échelle réduite a été fabriqué et testéavec trois types d'illumination de rayonnement (rayons X, les électrons et laser infrarouge). Tousles résultats obtenus valident le nouveau concept proposé. Un moniteur de rayonnement spatialtrès miniaturisé basé sur un capteur de pixel CMOS peut être prévu. Le moniteur peut présente lesmêmes performances que les compteurs actuels, mais avec une dissipation de puissance réduited'un ordre de grandeur qu'un poids, un volume d'encombrement et un coût moindre. En outre, enraison de ses sorties de haut niveau et faible débit de données, aucune traitement supplémentairedu signal dehors du capteur est nécessaire, ce qui le rend particulièrement attrayant pour desapplications dan les petits satellitairesThis thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0.35μm process. The sensor directly output particles flux information through 4 channels with a verylow data rate (80 bps) and minimal power dissipation (~ 100mW). Each channel representsparticles with different species and energies. The highest measurable flux density is up to 108particles/cm2/s (hits pile up < 5%). A reduced scale prototype was fabricated and tested with 3types of radiation illumination (X-ray, electrons and infrared laser). All the results obtained validatethe proposed new concept and a highly miniaturized space radiation monitor based on a singleCMOS pixel sensor could be foreseen. The monitor could provide measurements of comparable orbetter quality than existing instruments, but at around an order of magnitude lower powerconsumption, mass and volume and a lower unit cost. Moreover, due to its high level and low datarate outputs, no signal treatment power aside the sensor is required which makes it especiallyattractive for small satellite application
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Hsieh, Ya-Jen, and 謝雅蓁. "Low-Power Low-Distortion Preamplifier Systems for Cochlear Prosthesis Application." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/52p3jw.
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碩士國立交通大學
生醫工程研究所
104
For deaf people, to restore hearing is their long-term goals. The invention of cochlear implant, which is an auxiliary device implanted in the inner ear, can offer the sense of the sound to deaf people by electrical stimulation. After post-operative training, they will be able to perceive environmental sounds, obtain better verbal comprehension, and improve communication abilities. This thesis presents fully differential preamplifiers for cochlear prosthesis application that can reduce effect of noise and amplify signals in the audio band. The non-ideal effects, such as the flicker noise and thermal noise, have been considered in the design of the fully differential two-stage OPAMP. The signal-to-noise ratio (SNR) of the proposed preamplifier is improved and this preamplifier offers a high resolution for the audio signals. Designing the input pair of the first stage in the weak-inversion region can reduce the low-frequency noise and power consumption in the two-stage OPAMP. The proposed preamplifier is applied for audio application, so the group delay is needed to take into account in design. In view of the group delay, the system bandwidth is designed from 10 Hz to 200 kHz to ensure that the audio signals from 100 Hz to 20 kHz have the same group delay. In order to achieve the first pole at 10 Hz, the systems need a huge resistor or capacitor which cost a lot of chip area. The resistors applied in the preamplifier are implemented by pseudo-resistor and switched-capacitor resistor, respectively. The passband bandwidth of the proposed system is designed from 10 Hz to 200 kHz and the programmable gain of the system is designed as 15.6/6/3.5/0 dB. When the gain is 0 dB, the total harmonic distortion plus noise (THD+N) of two architectures is -81 dB and -82 dB for 1 kHz input frequency, respectively. The proposed systems have been designed and fabricated by standard 0.18 µm CMOS process in chip areas of 0.7 mm^2 and 2.68 mm^2. The power dissipation is 42μW and 173 µW from a 1.8 V supply, respectively.
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Chaturvedi, Vikram. "Low Power and Low Area Techniques for Neural Recording Application." Thesis, 2012. http://hdl.handle.net/2005/3167.
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Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed.
An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems.
ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology.
Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.
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Huang, Yu-Chi, and 黃榆棊. "Low Power DSP Chip with Audio Application." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/szcgmq.
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碩士國立中正大學
電機工程研究所
92
Recently, SOC design has the properties of high arithmetic operation capa-bility, low cost and low power. Especially in portable product, the power dis-passion of chips influences greatly on operation time, battery life and weight. In low power techniques, dynamic power manager is very effective to re-duce power dispassion. It includes precomputation, guarded evaluation, gated-clock finite state machines, FSM decomposition and other techniques. Each technique uses different approach to identify input data which circuit can be disable to archive power saving. These techniques have similar properties that the circuit only used is enabled and the circuit does not used is disabled. The tech-niques can provide some low power effort. In this Thesis we propose a data flow manager method. This method is a mechanism based on data flow to create finite state machine owing to produce control signal of control unit, and archives lowdown power dissipation. The method is implemented at instruction-level in low power CCU DSP and a five stage pipeline low power MAC. This DSP is compatible with TI TMS320 C54x DSP chip. We compared power dissipation with the method and low power MAC, low power MAC only, the method only, and original DSP in 4 experiment targets. Finally, audio programs have been tested on the DSP. As the experiment result, we can get about 30% powers saving in FIR, IDCT, Echo programs.
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Tsai, Chien-Chung, and 蔡建忠. "Low-power Circuits Design in RF Transmitter Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/66152312629178997948.
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碩士國立交通大學
電子工程系所
98
The implantable biomedical devices and portable 3C equipments necessitate low power consumption to lengthen the battery lifetime. In this thesis, two low-power circuits in RF transmitter front-end are realized and designed using TSMC 180 nm CMOS technology. The first topic is a frequency tripler with fundamental cancelling which provides more than 35 dB harmonic rejection ratio. The voltage conversion gain is -4.2 dB under 11.5 mW dynamic power consumption. In addition, this frequency tripler features quadrature signal both at input and output, it therefore can be used in communication systems which require I/Q signals for image rejection. The other topic is an outphasing power amplifier which deals with the trade-off between linearity and efficiency. The circuit is implemented by a pair of class-D power amplifiers and a transformer. According to simulation results, the power consumption is 14 mW under 1.2 V supply voltage at 1.4 GHz input frequency. The drain efficiency and power added efficiency (PAE) achieve 38 % and 29 % at input 1-dB compression point, and the average efficiency is 33.16%.
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Shu, Jang-Yee, and 徐贊翼. "Low Power/Low Voltage All Digital Down Converter for Wireless Communication Application." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/11951252972406097896.
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Yeh, Yu-Ying, and 葉又穎. "Design of Low Power High Gain Low Noise Amplifiers for Wideband Application." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/m3dcj6.
Full textAbstract:
碩士國立東華大學
電機工程學系
104
Receiver design is one of the most challenging aspects in the implementation wireless communication systems. Low noise amplifiers (LNAs) are the key blocks of receivers for amplifying weak signals from antenna. The design goal of LNAs are high gain, low noise figure (NF), good input and output matching, high linearity, small die area and low power consumption. In this thesis, two LNAs are proposed with low power and high gain for different wireless communication system applications. The first chip is an ultra-wide band (UWB) LNA with wireless local area network (WLAN) band rejection. UWB systems are operated at frequency band from 3.1 to 10.6GHz with very low transmission power. Within UWB band, there are signals of 5.725-5.825GHz from WLAN systems, which the signal strength is larger than the transmission power of UWB systems. Such signals are called in-band interference. The designed UWB LNA with 5.8GHz notch filter can avoid interference signal from WLAN system. The input stage is based on common gate amplifier. Also, the proposed UWB LNA uses the stagger tuning technique for extending the bandwidth with a flat gain. The notch filter with extremely high quality factor provides high band rejection ratio. The second chip is a low power high gain low noise amplifier for Long Term Evolution (LTE) system application. The complementary feedback amplifier is used in the first stage. A body-biased architecture is added to lower supply voltage so as to save the power consumption. The second stage is a cascade amplifier which provides high gain. The output stage is common-drain amplifier to achieve output impedance matching. The proposed LNAs were simulated and fabrication by using 0.18m CMOS process technology which is provided by Chip Implementation Center of National Applied Research Laboratory. The simulation results show that the proposed low power UWB LNA with WLAN band rejection. The power consumption is 9.6mW at 1V supply voltage. The maximum power gain and minimum noise figure is 15.4 and 4.9dB, respectively. The input reflection coefficient and output reflection coefficient are both less than -10dB. The maximum interference rejection (IRR) is 40.5dB. The chip size is 1.164×0.905mm2. The second chip is a low power high gain LNA for LTE application. The simulation results of the second chip are obtained by the same process as that of the first one. The power consumption is 4.87mW at 1V supply voltage. The maximum power gain is 19.9dB. The minimum noise figure is 2.55dB. The input reflection coefficient and the output reflection coefficient are both less than -10dB. The chip size is 1.185×0.776mm2. ¬The EM simulation results show that both LNAs achieved characteristics of low power and high gain.
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LIN, CHIH-YUNG, and 林志勇. "Low Power DA Design and its Application to DFT." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87347751726154060832.
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碩士國立聯合大學
電子工程學系碩士班
96
In this research, based on genetic algorithm, we propose a methodology to optimize the content arrangement of memory in group distributed arithmetic (GDA) architecture with low power consumption. Beginning with the chosen parent, the operations of reproduction, crossover, and mutation are performed iteratively to produce the offsprings better and better in GA. And then the solution with the optimal partial product combination for the data bus of the memory with minimum transition activity in GDA design is appeared after two or more generations. With the different properties of content in image frames, we have searched for the optimal solution to reduce power consumption of memory with minimum Hamming distance on the data bus in GDA. The simulation result shows that the hamming distance on the memory output of GDA design can be reduced around 17.57%. Applied with the same solutions, the hamming distances are also reduced significantly by 15.13% on the other test images with the similar property of image content. As to the application of the proposed low power approach, we apply the low power GDA design to the implementation of 1-D DFT hardware. We verify the proposed DFT design with behavior model in MATLAB and Verilog model respectively. The Verilog model is targeted to ASIC with cell-based design flow and 0.18um cell-library. Compared with the original GDA design without power optimization, with the different test benches, the power consumption of memory in the proposed low power DFT design is reduced by 6.44% averagely.
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Tsai, Cheng-Chun, and 蔡政君. "Low Power Noise Reduction Design for Hearing Aids Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19215618108211328365.
Full textAbstract:
碩士國立交通大學
電子工程系所
98
For hearing aids application, the amplification of input sound is needed in order to compensate the hearing loss of the patient. Thus noise reduction is required to improve speech quality and intelligibility under noisy environments. For integrated hearing aids system, low-power design is necessary such that the battery life can be expended and the system volume can be minimized. In this thesis, we propose a low power noise reduction design for hearing aids application with entropy-based voice activity detection and filter bank-based spectral subtraction. The entropy-based voice activity detection distinguishes the speech period from the silence period in noisy environment and makes the decision whether it is voice active or not. The filter bank-based spectral subtraction estimates noise level and performs different spectral subtraction schemes based on the result carried out by the entropy-based voice activity detection. Off mechanism turns off the spectral subtraction process if noise level lies below a fixed threshold in order to reduce power consumption. The proposed algorithm is optimized for low power hardware design by minimizing the calculation complexity. From simulation results, the average segment SNR improvement is 6.27dB and the average PESQ score is elevated by 0.316. The final design is implemented by UMC 90nm CMOS technology with high VT cell library. The clock frequency is 6MHz. For the hardware architecture, folding technique is adopted to save area and to reduce power consumption. For data storage, 1.536K Bytes of SRAM is utilized. The total estimated gate count is 101,697 including SRAM and 80,628 excluding SRAM. The total power consumption is 292.7μW.
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Chang, Te-Hung, and 張德宏. "Study of Low Power Wireless Communication System and Application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26089244664736025265.
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碩士國立東華大學
資訊工程學系
99
This thesis presents a practical study on integrated architecture between traditional wired telephone systems and wireless communication systems. The purpose of this integration is to attain complementary function toward each system limitations to evaluate feasible electromagnetic interference level in power plant system. Personal Handy-phone System (PHS) is proposed for this integration due to its feature of low power wireless technology and its compactness of network implementation. PHS and traditional wired telephone integration indicate low power digital wireless communication system in achieving proper electromagnetic interference level to support safety operation, maintenance efficiency, and at the same time obtain networks flexibility. To enhance the operation safety and maintenance efficiency in power plant, we have installed low power digital wireless communication system The usage of wired or wireless telecommunication devices will produce electromagnetic interference which may affect the digital instrumentations and control equipment. If the devices are not able to tolerance the interference levels, unit trip problem will occur and lead to significant equipment damage. Therefore conducting test evaluation for telecommunication devices on the electromagnetic interference compliance issues is very important. The proposed testing architecture meets the standards issued by United States Nuclear Regulatory Commission (USNRC) guidelines for electromagnetic compatibility (EMC) testing requirements. The pervaded standard requirements are power plant development and deployment, testing compatibility, and control method evaluation. The verified testing result and standard evaluations can be useful as references for telecommunication systems implementation concerning EMC issues.
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Hsiao, Ming-Kai, and 蕭名開. "12-Bit low power SAR-ADC for ECG application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05793753502319870096.
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碩士淡江大學
電機工程學系碩士在職專班
99
With the constant improvement on highly advanced technology nowadays, under the development of the microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP) influence, Analog to Digital Converter (ADC) has become a widely used application. The request for ADC specification will therefore be strict, as a result, more research will be conducted aggressively in the industrial and academic field. In order for ADC application become extensively used and correspond to the requirement of the present electronic products, four conditions need to be concerned: Speed, Resolution, Power, and Area. However, under the restriction of the factual conditions, in the process of designing, none of the ADC models was able to entirely correspond to the four conditions, thus trade-off was made for several application. This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system. It is aimed for capturing the probability of arrhythmia through monitoring and recording ECG for a long period of time. Consequently, the power voltage was defined in 1V for low power consumption purpose. The chip was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The sample rate is 600Hz in 150Hz signal bandwidth. Simulation results show that the SNDR and ENOB of the SAR-ADC with an input frequency of 24Hz are 67.53dB and 10.92dB. The power dissipation is 20.28μW under 1V power supply.
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Liao, Hsueh-Chih, and 廖學志. "A Low Power Signal Driver for TFT-LCD Application." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/59279052372249371988.
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碩士國立暨南國際大學
電機工程學系
93
There are two types of source drivers for TFT-LCD applications are proposed in the thesis. The first type is for the application of a large panel and SXGA TFT-LCD and the second is for the portable small-scale TFT-LCD. The first source driver contains a 6-bits ripple adder and some digital circuit with tradition source driver. This architecture improves circuit settling time. Enable the voltage to reach its goal in a short period of time and thus result a display spec of high resolution. The second source driver controls reference voltage buffers by switching on and off according to the selected number of colors in order to achieve static power control. The five-level seven-phase charge-recycling method is also used to reduce the dynamic power consumption.
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WU, YUN-HUAN, and 吳昀寰. "Low Static Power DC-DC Converter for Car Application." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/fyu28k.
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Pan, Yan-Cheng, and 潘彥成. "Chip Design of a Low Voltage and Low Power Mixer for WiMAX Application." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/37995222580748343810.
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碩士國立彰化師範大學
積體電路設計研究所
98
In this thesis design a low power consumption mixer for WiMAX receiver system application. We use a new transconductor stage and folded structure to design a low supply voltage and low power consumption mixer core, by using the RLC matching network we can achieve the return loss for all three terminal are less than -10dB. And change the connect point for current injection technique to the mixer output use for enhance conversion gain. The frequency includes input RF signal for 2 to 11 GHz and output IF signal for 20 MHz, the total power consumption is only 4.33 mW for 1V supply voltage in the measured result. The mixer is simulated by Agilgent EDA (Electronic Design Automatic) - ADS (Advance Design System) with TSMC 0.18 μm RF CMOS technology.
40
"Low voltage and low power circuit techniques for CMOS RF frequency synthesizer application." 2013. http://library.cuhk.edu.hk/record=b5549762.
Full textAbstract:
在過去的幾十年中，無線通信已經歷了顯著的發展，並成為日常生活中必不可少的一部分。隨著對可移動便攜式電子設備的需求不斷增加，功耗已经成為射頻前端電路設計的一個最關鍵參數。在便攜式無線消費類電子中，頻率綜合器在收发机设计中提供本地振盪器（LO），它又是一個高功耗的子系統之一。降低頻率綜合器的功耗將會直接影响電池的使用時間。為了驗證進來新型的低功耗技术，本文基於低成本的0.18微米三阱CMOS工藝，設計並實現了三個不同的電路模塊和一個頻率綜合器系統。第一個設計是一個低壓正交壓控振盪器(QVCO)和除肆分頻器的電流復用電路。在沒有損耗電壓餘量的情況下，兩個高頻模塊通過電流復用的方式，從而降低了功耗。測試結果顯示當電源電壓為1.3V ，電流消耗電流為2.7毫安。在2.2 GHz載波附近1MHz頻偏位置上的相位噪聲為 -114 dBc/Hz。第二個設計是應用於SDR的變壓器和電流復用的壓控振盪器/分頻器的電路。該電路通過調整偏置電壓，僅用一個分頻器就可以實現可變分頻比（2，3，…,9）的功能。實驗結果表明，分頻器的輸出頻率範圍從0.58至3.11 GHz，在5.72 GHz載波附近1MHz頻偏位置上的相位噪聲為-112.5 dBc / Hz，電源電壓為1.8V時，電流為4.7mA。第三個設計是應用於UWB的變壓器和電流復用的QVCO / SSBM電路。這個全新的結構電路面積為0.8平方毫米，在1.6V電源電壓下，消耗功耗約為11 mA。測量結果表明，帶外雜散抑制小於43dBc，頻率偏移1MHz位置處的相位噪聲小於-112 dBc/Hz。最後一個設計是應用於 MB-OFDM UWB的頻率綜合器。這個新結構只用了一個電感在不犧牲主要性能的情況下，可以實現小的芯片尺寸和低的功耗。測試結果全部基於UWB的頻段，相位噪聲為-119 dBc/Hz@10 MHz，電源電壓1.2 V，總電流消耗為24.7mA。
Over the past decades, wireless communication has experienced a remarkable development and become an essential part of daily life. With the rapid increasing demand for mobile and portable electronic devices, the power dissipation has become one of the most critical design parameters, especially for RF front-ends. In portable wireless consumer electronics, the RF frequency synthesizer is one of the most power-consuming subsystems, which serves as local oscillator (LO) in transceiver design. Any power saving in frequency synthesizer will directly affect the running time of battery.
To demonstrate recent innovation in low power techniques, three different circuit blocks and one frequency synthesizer have been developed and fabricated in low-cost 0.18μm triple-well CMOS process. The first design is a low-voltage current reused quadrature VCO and divider-by-4 frequency divider circuit. By the novel sharing of transistors between the two high frequency blocks, the power consumption of the overall design can be reduced with little penalty on voltage headroom. Experimental results show a phase noise level of -114 dBc/Hz at 1 MHz offset from 2.2 GHz carrier and consumes 2.7 mA from a 1.3V power supply. The second design is a transformer-based current reused VCO/ILFD circuits for SDR application. By the adoption of bias tuning techniques, variable division ratios (2,3,…,9) can be achieved with a single divider circuit. Experimental results show an output frequency ranging from 0.58 to 3.11 GHz and a phase noise level of -112.5 dBc/Hz at 1 MHz offset from 5.72 GHz carrier, with a consumed current of 4.7 mA from a 1.8V power supply. The third design is a transformer-based current-reused QVCO/SSBM circuit for UWB application. The prototype is the first of its kind, while occupies a core area of 0.8 mm² and consumes roughly 11 mA from 1.6V power supply. Measurement results show that the out-of-band spurious rejection and phase noise at 1 MHz offset are better than 43 dBc and -112 dBc/Hz respectively. The final design is a frequency synthesizer for MB-OFDM UWB application. It uses a single inductor approach and novel system architecture to realize compact die size and low power consumption without sacrificing major performance. Experimental results show a phase noise level of -119 dBc/Hz@10 MHz offset for all UWB bands and consumes 24.7 mA from a 1.2 V power supply.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Li, Wei.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Abstract --- p.i
Acknowledgement --- p.v
Table of Contents --- p.vi
List of Figures --- p.xi
List of Table --- p.xvi
Chapter CHAPTER 1 --- INTRODUCTION --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Outline of Dissertation --- p.3
References --- p.5
Chapter CHAPTER 2 --- A NOVEL LOW-VOLTAGE CURRENT REUSED, QUADRATURE VCO AND DIVIDE-BY-4 FREQUENCY DIVIDER --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.2 --- Oscillation Principle of VCO --- p.9
Chapter 2.3 --- Circuit Implementation --- p.14
Chapter 2.3.1 --- Back-gate Coupled QVCO --- p.14
Chapter 2.3.2 --- Divider-by-4 Frequency Divider --- p.20
Chapter 2.3.3 --- Current Reuse QVCO and Frequency Divider --- p.24
Chapter 2.3.3.1 --- Voltage Headroom --- p.25
Chapter 2.3.3.2 --- Startup Condition --- p.26
Chapter 2.3.3.3 --- Operating Range --- p.27
Chapter 2.3.3.4 --- Phase Noise --- p.28
Chapter 2.3.3.5 --- Transient Response --- p.30
Chapter 2.4 --- Experimental Result --- p.31
Chapter 2.4.1 --- Frequency Tuning Range --- p.32
Chapter 2.4.2 --- Phase Noise --- p.33
Chapter 2.4.3 --- Transient Response --- p.34
Chapter 2.4.4 --- Performance Comparison --- p.34
Chapter 2.5 --- Summary --- p.36
Reference --- p.36
Chapter CHAPTER 3 --- A TRANSFORMER BASED CURRENT REUSED VCO/ILFD CIRCUIT WITH VARIABLE DIVIDING RATIOS --- p.41
Chapter 3.1 --- Introduction --- p.41
Chapter 3.2 --- Transformer Design --- p.43
Chapter 3.2.1 --- Ideal Transformer --- p.43
Chapter 3.2.2 --- Transformer Tank --- p.45
Chapter 3.3 --- Design of Current Reused VCO/ILFD --- p.49
Chapter 3.3.1 --- Transformer Implement --- p.50
Chapter 3.3.2 --- VCO Implement --- p.52
Chapter 3.3.3 --- ILFD Implement --- p.54
Chapter 3.4 --- Experiment Results --- p.60
Chapter 3.4.1 --- Phase Noise --- p.61
Chapter 3.4.2 --- Frequency Tuning Range --- p.62
Chapter 3.4.3 --- Transient Response --- p.64
Chapter 3.4.4 --- Performance Comparison --- p.65
Chapter 3.5 --- Summary --- p.66
Reference --- p.66
Chapter CHAPTER --- 4 CURRENT REUSED QVCO/SSBM CIRCUIT FOR MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.70
Chapter 4.1 --- Introduction --- p.70
Chapter 4.2 --- Proposed solution for UWB frequency synthesizer --- p.72
Chapter 4.3 --- Bimodal Oscillation Phenomenon --- p.74
Chapter 4.4 --- Design of Current Reused QVCO/SSBM Circuit --- p.81
Chapter 4.4.1 --- Transformer Implementation --- p.82
Chapter 4.4.2 --- QVCO Implementation --- p.85
Chapter 4.4.3 --- SSBM Implementation --- p.88
Chapter 4.5 --- Experimental Results --- p.89
Chapter 4.5.1 --- Phase Noise --- p.91
Chapter 4.5.2 --- Spur Suppression --- p.92
Chapter 4.5.3 --- Performance Comparison --- p.93
Chapter 4.6 --- Summary --- p.94
Reference --- p.95
Chapter CHAPTER 5 --- A SINGLE INDUCTOR APPROACH TO THE DESIGN OF LOW-VOLTAGE MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.98
Chapter 5.1 --- Introduction --- p.98
Chapter 5.2 --- Frequency Synthesizer Background --- p.101
Chapter 5.2.1 --- General Consideration --- p.101
Chapter 5.2.1.1 --- Frequency Requirement --- p.102
Chapter 5.2.1.2 --- Phase Noise --- p.103
Chapter 5.2.1.3 --- Spurious Tones --- p.104
Chapter 5.2.1.4 --- Switching Time --- p.105
Chapter 5.2.2 --- Overview of MB-OFDM UWB Frequency Synthesizer --- p.105
Chapter 5.3 --- Frequency Synthesizer System Design --- p.109
Chapter 5.3.1 --- Proposed Frequency synthesizer Architecture --- p.109
Chapter 5.3.2 --- Stability Analysis --- p.111
Chapter 5.3.3 --- Phase Noise Contribution --- p.115
Chapter 5.4 --- Circuit Implementation --- p.121
Chapter 5.4.1 --- Current Reused Multiplier/SSBM --- p.121
Chapter 5.4.2 --- 12-Phase Cross-coupled Ring VCO --- p.128
Chapter 5.4.3 --- Regenerative Frequency Divider --- p.131
Chapter 5.4.4 --- Tri-mode Phase Calibration Buffer --- p.132
Chapter 5.4.5 --- Phase-Frequency Detector(PFD) --- p.134
Chapter 5.4.6 --- Charge Pump --- p.135
Chapter 5.4.7 --- CML Divider --- p.136
Chapter 5.5 --- Experimental Result --- p.137
Chapter 5.5.1 --- Frequency Tuning Range --- p.139
Chapter 5.5.2 --- Phase Noise --- p.140
Chapter 5.5.3 --- Spur Suppression --- p.141
Chapter 5.5.4 --- Performance Comparison --- p.142
Chapter 5.6 --- Summary --- p.143
Reference --- p.143
Chapter CHAPTER 6 --- CONCLUSIONS AND FUTURE WORKS --- p.147
Chapter 6.1 --- Conclusions --- p.147
Chapter 6.2 --- Future Works --- p.149
List of Publication --- p.150
41
Hsieh, Cheng-Ting, and 謝政廷. "Design of the Low-Power Low-Noise Analog Front End for Biomedical Application." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/49esjr.
Full textAbstract:
碩士國立交通大學
電機工程學系
108
With the advance of technology recently, the traditional electrical engineering together with medical industry improves the biomedical industry. Doctors can treat patients more efficiently and let patients have a better life quality with the aid of electrical engineering. Integrated circuits are popular in the electrical industry, which can help doctors minimize the size of the wound and hence decrease the physical damage on human body when implanting chips into patients. This thesis is to propose an analog front end for cochlear implant application and an analog front end for Parkinson’s disease treatment. The former is to amplify the audio signal and filter out the noise and the latter is to detect the local field potential related to Parkinson’s disease. To acquire a better quality of signals, it is an important issue to reduce the noise of the circuits. For the reduction of Flicker noise in low frequency, the input pairs of the first stage fully differential operational amplifier have to be of the large size and operate in the weak inversion region. Besides, the proposed circuits also use the chopping technology to obtain a better noise performance. In the preamplifier design for cochlear implant application, it must take group delay into account because of the audio signals. If it has different delays with different frequency, it will be a serious problem to understand the signal contents. To deal with the issue, the bandwidth of the system has been extended to 10Hz - 200kHz. In the preamplifier design for Parkinson’s disease treatment, the input terminals will have a large DC offset voltage because of the direct contact between input electrodes and tissue. If the problem can not be solved, the output terminals of the amplifier will be saturated and fail to acquire the desired signal. For the two designs, the extreme large resistance is necessary because there are ultra-low frequency poles. The large resistors will be implemented by pseudo-resistors instead of the conventional poly resistors, which can satisfy the ultra-low frequency pole and save the chip area simultaneously. The preamplifier for cochlear implant application achieves a bandwidth of 10Hz-200kHz, a programmable gain of 240, 800, 2400, and 8000, and the noise of 3.34μVrms in TSMC 0.18um standard CMOS 1P6M process. The preamplifier for Parkinson’s disease treatment achieves a bandwidth of 0.5Hz-100Hz, a programmable gain of 1000,3000,10000, and 30000, and the noise of 1.38μVrms in TSMC 0.18um standard CMOS 1P6M process.
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Wu, Yen-Ting, and 吳彥廷. "Design of High Linearity Low Power Low Noise Amplifiers for vehicle radar system Application." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/2dxwv3.
Full textAbstract:
碩士國立東華大學
電機工程學系
106
This thesis mainly Research and production low noise amplifiers for wireless communication systems, and then to proposes two low noise amplifiers for different frequency band systems. The first chip is proposed a high gain single to differential low noise amplifier using gm-boost technique for LTE systems that the system is operated at frequency 0.7-2.7 GHz. There is a circuit design with single to differential circuit, and increased the gain by gm-boosting technology, and then the bandwidth have 3 dB bandwidth. The second chip is proposed a high linearity low power LNA using passive positive feedback technology from FMCW system that the system is operated at 24 GHz. The first stage uses a capacitor for gm-boosting to increase the gain, while in the second stage, make the gain in the high point at 24 GHz by feedback technology and the base bias technology is used to reduce the power consumption of the overall circuit.
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Huang, Yu-Hua, and 黃禹華. "Low-Power CMOS BandPass Filter for Application of Cochlear Prosthesis." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/zca96n.
Full textAbstract:
碩士國立交通大學
電機學院電信學程
101
In this thesis, a CMOS Gm-C filter based on operational transconductance amplifiers (OTAs) with low power and tuning ability for biomedical applications is proposed. The OTA works in the weak-inversion region. The transconductance can be tuned by changing its bias current. A Fourth-Order Butterworth LC ladder Gm-C bandpass filter implemented with the OTAs was fabricated by TSMC 0.18-μm Mixed Signal 1P6M CMOS process. The supply voltage of the OTA-C filter can be as low as 0.65V for minimum power. The power consumption of the first IC is 225nW for a sinusoidal input signal of 300 Hz 100 mVPP with 1V supply voltage. Its Total Harmonic Distortion (THD) is -48.58 dB. The power consumption of the second IC is 61nW for a sinusoidal input signal of 300 Hz 100 mVPP with 1V supply voltage. The THD is -50.23 dB. They both have the same active area of 0.04mm2.
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Laio, Chou-Mine, and 廖秋明. "Implementation of a new Architecture SRAM and Low Power Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/03656620585337890239.
Full textAbstract:
碩士南台科技大學
電子工程系
97
With the development of semiconductor, the demand of low power as well as low cost is the primary claim in all electronic products. Nowadays, more and more transistors are integrated into the core of modern chips which requires more demand in memory circuits, too. Thus, we choose memory as research target. Device sizes shrinks in deep-submicron process causes some problems like noise and parasite effects. All those effects consumes more and more power which can not be neglected at all. In addition, static power consumption is also more and more obvious. Hence, we try to propose new SRAM (Static Random Access Memory) to overcome power consumption problems caused by leakage current. The result can be more power efficient. Besides, it will also reduce the problems caused in deep-submicron process. According to our comparison, the proposed design posesses the advantages in dynamic power consumption, static power consumption and operating speed. Besides the mentioned problems, the circuit is causing extra power consumption in charging/discharging operation. In order to inhibit unwanted power consumption of the bit lines, we add selectable charge bit line design to reduce power consumption. We also add GLSENAD address sense circuit in address sense circuit. In short, we provide a new architecture of SRAM design. The proposed design is realized by TSMC (Taiwan Semiconductor Manufacturing Company) 0.18 um CMOS process. The simulation is done by HSpice.
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Lee, Chien-Hsun, and 李建勳. "Wide-Range Low-Power CMOS BandPass Filter for ECG Application." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/23207365873915380282.
Full textAbstract:
碩士國立交通大學
電機學院電信學程
104
Nowadays, in the aging society with fewer children, people need more medical services, especially health management, and all aspects of home care has become a common trend in the world, in which the heart signal monitoring system is a combination of medicine and technology. In this thesis, a CMOS Gm-C filter based on operational transconductance amplifiers (OTAs) with low power and center frequency tuning ability for Bio-analytical applications is proposed. The OTA uses source degeneration to increase the linearity. In order to achieve low power consumption, MOSFETs are designed to work in the weak inversion region. The transconductance and center frequency of the filter can be tuned by changing its bias current. A Fourth-Order Butterworth LC ladder Gm-C bandpass filter implemented with the OTAs was fabricated by TSMC 0.18-μm 1P6M CMOS process. The total power consumption is 410nW and Total Harmonic Distortion is -59.60dB when the Gm-C filter operates at 1.8V power supply. The active area is 0.064mm2.
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Lin, Tzu-Chieh, and 林子傑. "High Linearity Low-Power CMOS Bandpass Filter for Cochlear Application." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/48654793950226696271.
Full textAbstract:
碩士國立交通大學
電機工程學系
104
With the advance in cochlear implant, cochlear allows hearing-impaired people to regain hearing and enhance their communication skills. This technology can benefit many people, but how to reduce the power consumption plays an important role in today’s science and technology development. This thesis presents a gm-c filter with high linearity and low power consumption. The gm-c filter with low power and tuning ability for biomedical applications is proposed. To achieve the demands of low power consumption, MOSFETs are designed to work in the weak inversion region. The transconductance amplifier (OTA) uses an equivalent resistor to implement the circuit. Source degeneration is utilized to increase the linearity of the OTA. The center frequency of the filter is tunable by changing its bias current. A Fourth-Order Butterworth LC ladder Gm-C bandpass filter is implemented by the OTAs. The chip was fabricated by Taiwan Semiconductor Manufacturing Company （TSMC） 0.18μm 1P6M 1.8V mixed‐signal CMOS process.
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Cho, Yu-Ru, and 卓育儒. "Design and application of low power pulse-triggered flip-flops." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/42558328998390817052.
Full textAbstract:
碩士國立雲林科技大學
電子與資訊工程研究所
97
Low power design of VLSI circuits has been identified as a critical technological need. The power consumption of the clock system, which consists of the clock distribution networks and storage elements, is estimated as about 20% to 45% of the total system power. As a result, reducing the power consumed by flip flops has a huge impact on the total power consumption. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF rich modules such as register file, shift register and FIFO. FFs thus contribute a significant portion of gate count and power consumption to the overall system design. In this thesis, a novel low power pulse-triggered based flip-flop is presented. By using a 2-transistor AND gate to control the pulse generation, the critical path of the design is effectively shortened. A conditional pulse enhancement technique is further incorporated to achieve a faster discharging along the critical path. Both design measures facilitate smaller transistor sizes in delay inverter and pulse generation circuit, which lead to better power performance against rival designs. Various post-layout simulation results based on UMC CMOS 90nm process technology reveal that, the proposed design can achieve over 17% saving in term of power and power-delay-product when compared with previous pulse-triggered based flip-flop designs. The reduction in leakage power consumption is as high as a factor of 2.4 due to the shrunken transistor size.
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Ho, Shin-Wei, and 侯信維. "Design of Low Power Voltage Controlled Oscillator for WLAN Application." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/74871288960949910358.
Full textAbstract:
碩士國立臺北科技大學
機電整合研究所
92
With the substantial improvement on the RF technology, cell phones and WLAN applications have became indispensable parts of our lives and create huge amount commercial markets. The design in the thesis, in order to obtain higher negative impedance and to prevent the common mode noise, the VCO is accomplished using complementary cross-coupled pair MOSFETs. Specially, tail current source of VCO is omitted and the current is provided by negative cell itself. With this topology, the major noise source of VCO is cancelled and the phase noise performance can be improved. Also, the headroom can be compressed for the low-power requirement. The quadrature signals are generated using the third order polyphase filter for smaller chip area and better symmetry. Considering on-chip probe, the layout of this design is laid in G-S-G type. This design is implemented by TSMC 0.25um process supplied by CIC. The chip is operated in 1.2V DC supply, simulation results show frequency range among 2.363~2.557GHz, -124.6dBc/Hz@1MHz phase noise, -183.6dBc/Hz FOM, 4.78mW power consumption. Chip size is 0.99X0.96mm2.
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Pao, Chien-Yuan, and 包建元. "Low-Power Fully-Parallel Content Addressable Memory - Analysis, Design, and Application." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/05060476658569781202.
Full textAbstract:
碩士國立中正大學
電機工程研究所
87
A partial-current-mode fully-parallel CAM is proposed in this thesis. The proposed fully-parallel CAM performs current-mode operation when either for both read data and write data, but when match data is still performed by voltage-mode. This thesis also describes several different CAM structures using different CAM cells in published paper and re-implement these CAM structures to analyze their operation and power dissipation. A 512x15-bits CAM was designed and implemented in a 0.6-mm CMOS technology, and then this design is automatically converted to a design using a 0.35-mm CMOS technology by a technology migration technique developed by the VLSI GROUP of EE/CCU. The design of the 0.35-mm version has also been submitted for fabrication. This CAM design is really used in a CCMAC control chip We have implemented a CCMAC ASIC to verify the hardware feasibility of this new architecture and also to verify the performance of the new content addressable memory. This ASIC will also be installed in a backer-upper control system.
50
Chang, Feng-Kai, and 張峰榿. "Low Power Wireless Data Transmission for Implantable Neural Sensing Microsystems Application." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/7fyg56.
Full textAbstract:
碩士國立交通大學
電子研究所
105
This thesis, aims to design and implement a low power-consumption, less area, low process variation and temperature sensitivity to voltage controlled oscillator (VCO) and wide swing of output on wireless data transmission chip. The wireless data transmission system receives wireless data by the data which passes the OOK modulator, then it passes the inductive coupling via an on-interposer of receive terminal inductor which is out of the chip. Then it passes the OOK demodulator to recover the data. In this thesis, only the open-loop circuit is used to solve the problem that the oscillation frequency is drifted a lot by the process variation. The chip is used only all-MOS element, and we do not use any passive component on chip, rather than the general use of the special phase-locked loop to solve the problem, thus it can save a lot of power and area. In this thesis, the CMOS bandgap reference circuit is used to eliminate the MOS threshold voltage in the subthreshold region to reduce the VCO oscillation frequency deviation caused by the process variation. This method requires no additional compensation or calibration circuits. Hence it can reduce the area and the power of those circuits. Circuits operate in the subthreshold region can also reduce the power and operating voltage of the bias circuits. In this thesis, the purposed VCO with voltage reference provides stable current to oscillate at a fixed frequency against process and temperature variations, and the circuit is low power consumption, low area, and wide output swing design, and the purposed VCO with current reference is also less susceptible to against supply noise variation than the purposed VCO with voltage reference. We use the current-starved method and gain-boost method to against supply noise variation. In this thesis , the VCO and OOK modulator of wireless transmission chip are used differential input and differential output which can reduce the input signal noise, and increase the output swing. This thesis through the National Chip Implementation Center to tape out the chip with TSMC 180nm CMOS process. The simulation results show that the chip power consumption of the purposed wireless data transmission system with the purposed voltage reference is 382μW.The total area of the chip is 0.027 mm2.The oscillation frequency of the VCO is 256MHz.The variation of the VCO oscillation frequency is 4.3% at 0~50℃. The variation of the VCO oscillation frequency caused by the process variation is 29%. The chip power consumption of the purposed wireless data transmission system with the purposed current reference is 354μW.The total area of the chip is 0.036 mm2.The oscillation frequency of the VCO is 400MHz. The variation of the VCO oscillation frequency is 4.2% at 0~50℃. The variation of the VCO oscillation frequency caused by the process variation is 27%. The variation of the VCO oscillation frequency caused by the supply variation at plus or minus 10% supply variation is 3.3%.