Relevant bibliographies by topics / Low-power CMOS

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Low-power CMOS'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Low-power CMOS"

1

GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipol
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Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

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Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply
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Xu, Ni, Woogeun Rhee, and Zhihua Wang. "Semidigital PLL Design for Low-Cost Low-Power Clock Generation." Journal of Electrical and Computer Engineering 2011 (2011): 1–9. http://dx.doi.org/10.1155/2011/235843.

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.
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Blair, G. M. "Designing low-power digital CMOS." Electronics & Communication Engineering Journal 6, no. 5 (1994): 229–36. http://dx.doi.org/10.1049/ecej:19940505.

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Chandrakasan, A. P., S. Sheng, and R. W. Brodersen. "Low-power CMOS digital design." IEEE Journal of Solid-State Circuits 27, no. 4 (1992): 473–84. http://dx.doi.org/10.1109/4.126534.

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Ismail, A. M., and A. M. Soliman. "Low-power CMOS current conveyor." Electronics Letters 36, no. 1 (2000): 7. http://dx.doi.org/10.1049/el:20000129.

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Wu, Xiang, and Fang Ming Deng. "A Capacitive Humidity Sensor for Low-Cost Low-Power Application." Applied Mechanics and Materials 556-562 (May 2014): 1847–51. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1847.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface employs a fully-digital architecture based on phase locked loop, which results in low pow dissipation. The proposed humidity sensor is fabricated in TSMC 0.18μm CMOS process and the chip occupies an area of 0.05mm2. The measurement result shows that the sensor value exhibits good linearity within the range of 10-90%RH and the interface circuit consumes only 1.0
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Srilakshmi, K., A. V. S. Karthikeya Chowdary, D. Lakshmi Soumya, Ch Hemasri, and G. Pavan Kumar. "Performance Analysis of High Speed Low Power BCD Adder using CMOS and Dynamic logic." Indian Journal Of Science And Technology 18, no. 21 (2025): 1703–15. https://doi.org/10.17485/ijst/v18i21.700.

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Background: In the field of high-speed digital circuits, the efficiency of Binary Coded Decimal (BCD) adders consists of significant importance in optimizing the speed of arithmetic operations in computing systems. BCD arithmetic is crucial in scientific and financial computing systems that require decimal accuracy. Objectives: This study examines the performance of BCD adders as designed using two different logic families, Complementary Metal Oxide Semiconductor (CMOS) and dynamic logic. CMOS logic which is meant to have low static power dissipation and dynamic logic which is meant to have hi
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Elwan, H. O., and A. M. Soliman. "Low-voltage low-power CMOS current conveyors." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 44, no. 9 (1997): 828–35. http://dx.doi.org/10.1109/81.622987.

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Radhakrishnan, D. "Low-voltage low-power CMOS full adder." IEE Proceedings - Circuits, Devices and Systems 148, no. 1 (2001): 19. http://dx.doi.org/10.1049/ip-cds:20010170.

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Dissertations / Theses on the topic "Low-power CMOS"

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Park, Byeong-Ha. "A low-voltage, low-power, CMOS 900MHZ frequency synthesizer." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/16686.

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Yeh, David Alexander. "Multi-gigabit low-power wireless CMOS demodulator." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41168.

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This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) a
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Di, Pede Luigi. "A 1 V low-power CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/MQ34130.pdf.

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Zuber, Paul. "Wire topology optimisation for low power CMOS." kostenfrei, 2007. http://mediatum2.ub.tum.de/doc/618152/document.pdf.

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Shepherd, Leila Maryam. "Low-power computational interfacing for CMOS ISFETs." Thesis, Imperial College London, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.497646.

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Leistad, Tor Erik. "Delay-Fault BIST in Low-Power CMOS Devices." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8877.

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<p>Devices such as microcontrollers are often required to operate across a wide range of voltage and temperature. Delay variation in different temperature and voltage corners can be large, and for deep submicron geometries delay faults are more likely than for larger geometries. This has made delay fault testing necessary. Scan testing is widely used as a method for testing, but it is slow due to time spent on shifting test vectors and responses, and it also needs modification to support delay testing. This assignment is divided into three parts. The first part investigates some of the effe
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Ardalan, Kasra. "A low-power CMOS fractional-N frequency synthesizer." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0003/MQ40932.pdf.

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Chan, Wai Pan. "Robust low power CMOS methodologies for ISFETs instrumentation." Thesis, Imperial College London, 2010. http://hdl.handle.net/10044/1/6056.

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I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a vol
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Chan, Tat Fu. "Low power low phase noise CMOS LC quadrature voltage-controlled oscillators /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHANT.

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Shiah, Jack Chih-Chieh. "Design techniques for low-power low-noise CMOS capacitive-sensor readout circuits." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54529.

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In recent years, the demand for low-cost, high performance, and miniature sized MEMS capacitive inertial sensors (accelerometer/gyroscope) has been steadily increasing. Use MEMS capacitive accelerometer as an example, for high precision applications, the resolution needs to be in the μg range at the frequency of interest. These high performance sensors are now been used in numerous applications that require more demanding specifications. For instance, they found their use in active suspension, adaptive brakes, alarm systems, tilt control, vibration, shock measurements, platform stabilization,
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Books on the topic "Low-power CMOS"

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P, Chandrakasan Anantha, and Brodersen Robert W. 1945-, eds. Low-power CMOS design. IEEE Press, 1998.

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Sheng, Samuel, and Robert Brodersen. Low-Power CMOS Wireless Communications. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8.

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Chandrakasan, Anantha P., and Robert W. Brodersen. Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3.

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Chandrakasan, Anantha P. Low Power Digital CMOS Design. Springer US, 1995.

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1945-, Brodersen Robert W., ed. Low power digital CMOS design. Kluwer Academic Publishers, 1995.

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Yeo, Kiat Seng. CMOS/BiCMOS ULSI: Low voltage, low power. Prentice Hall PTR, 2002.

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C, Guerrini Nicola, ed. Low-voltage low-power CMOS current conveyors. Kluwer Academic Publishers, 2003.

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Itoh, Kiyoo, Thomas Lee, Takayasu Sakurai, Willy M. C. Sansen, and Doris Schmitt-Landsiedel, eds. Low Power VCO Design in CMOS. Springer-Verlag, 2006. http://dx.doi.org/10.1007/3-540-29256-x.

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Soudris, Dimitrios, Christian Piguet, and Costas Goutis, eds. Designing CMOS Circuits for Low Power. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-3530-7.

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Roy, Kaushik. Low-power CMOS VLSI circuit design. Wiley, 2000.

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Book chapters on the topic "Low-power CMOS"

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Saini, Sandeep. "CMOS Buffer." In Low Power Interconnect Design. Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4614-1323-3_2.

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Athas, William C. "Energy-Recovery CMOS." In Low Power Design Methodologies. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4615-2307-9_4.

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Bellaouar, Abdellatif, and Mohamed I. Elmasry. "VLSI CMOS Subsystem Design." In Low-Power Digital VLSI Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2355-0_7.

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Srivastava, Mani B. "Low Power Programmable Computation." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_10.

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Kim, Hyejung, and Hoi-Jun Yoo. "Low Power Bio-Medical DSP." In Bio-Medical CMOS ICs. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6597-4_6.

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Chandrakasan, Anantha P., and Robert W. Brodersen. "Sources of Power Consumption." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_3.

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Meindl, James D. "Hierarchy of Limits of Power." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_2.

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Sheng, Samuel, and Robert Brodersen. "Introduction." In Low-Power CMOS Wireless Communications. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8_1.

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Sheng, Samuel, and Robert Brodersen. "Conclusions and Future Directions." In Low-Power CMOS Wireless Communications. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8_10.

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Sheng, Samuel, and Robert Brodersen. "Modulation, Multiple Access, and How Radio Waves Behave Indoors." In Low-Power CMOS Wireless Communications. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8_2.

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Conference papers on the topic "Low-power CMOS"

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Kumar, Kaushal, Dhruv Kumar Sachdev, Mahima Tyagi, Ajay Kumar, Aditya Jain, and Vinay Kumar. "Beyond CMOS: Unlocking Low-Power with TFETs." In 2024 International Conference on Computer, Electronics, Electrical Engineering & their Applications (IC2E3). IEEE, 2024. https://doi.org/10.1109/ic2e362166.2024.10827587.

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Bagri, Manju, Manoj Kumar, and Ramnish Kumar. "Design of CMOS based Low Power DCO using MT-CMOS technique." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012317.

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Gassouma, Hajer, Thouraya Ettaghzouti, Mounira Bchir, and Néjib Hassen. "A High-Speed Low-voltage Low-power CMOS Dynamic Comparator." In 2025 IEEE 22nd International Multi-Conference on Systems, Signals & Devices (SSD). IEEE, 2025. https://doi.org/10.1109/ssd64182.2025.10989829.

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Dokic, Branko L., Tatjana Pesic-Brdanin, and Drago Cavka. "Low-voltage low-power CMOS design." In 2016 International Symposium on Industrial Electronics (INDEL). IEEE, 2016. http://dx.doi.org/10.1109/indel.2016.7797813.

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Schoebinger, Matthias, and Tobias G. Noll. "Low power CMOS design strategies." In the 31st annual conference. ACM Press, 1994. http://dx.doi.org/10.1145/196244.196574.

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Chen, An. "Low-power beyond-CMOS devices." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021204.

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Kováč, Martin, Miroslav Potočný, Daniel Arbet, Róbert Ondica, Richard Ravasz, and Viera Stopjaková. "Low-Power CMOS Frequency Comparator." In 2023 46th MIPRO ICT and Electronics Convention (MIPRO). IEEE, 2023. http://dx.doi.org/10.23919/mipro57284.2023.10159783.

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Gabriel, Koubar, Sadek Sawsan, Haddad Fayrouz, and Rahajandraibe Wenceslas. "Low power CMOS bridge Rectenna." In 2022 IEEE Conference on Antenna Measurements and Applications (CAMA). IEEE, 2022. http://dx.doi.org/10.1109/cama56352.2022.10002549.

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Yang, Xiao, Jing Yang, Li-fen Lin, and Chao-dong Ling. "Low-power low-noise CMOS chopper amplifier." In 2010 International Conference on Anti-Counterfeiting, Security and Identification (2010 ASID). IEEE, 2010. http://dx.doi.org/10.1109/icasid.2010.5551831.

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Hill, C. "Design of a low power HF CMOS filter." In IEE Seminar Low Power IC Design. IEE, 2001. http://dx.doi.org/10.1049/ic:20010014.

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