Relevant bibliographies by topics / Low-power CMOS

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Low-power CMOS'

Author: Grafiati
Published: 4 June 2021
Last updated: 14 June 2025

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Journal articles on the topic "Low-power CMOS"

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GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.
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Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

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Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.
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Blair, G. M. "Designing low-power digital CMOS." Electronics & Communication Engineering Journal 6, no. 5 (1994): 229–36. http://dx.doi.org/10.1049/ecej:19940505.

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Chandrakasan, A. P., S. Sheng, and R. W. Brodersen. "Low-power CMOS digital design." IEEE Journal of Solid-State Circuits 27, no. 4 (1992): 473–84. http://dx.doi.org/10.1109/4.126534.

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Ismail, A. M., and A. M. Soliman. "Low-power CMOS current conveyor." Electronics Letters 36, no. 1 (2000): 7. http://dx.doi.org/10.1049/el:20000129.

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Xu, Ni, Woogeun Rhee, and Zhihua Wang. "Semidigital PLL Design for Low-Cost Low-Power Clock Generation." Journal of Electrical and Computer Engineering 2011 (2011): 1–9. http://dx.doi.org/10.1155/2011/235843.

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.
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Elwan, H. O., and A. M. Soliman. "Low-voltage low-power CMOS current conveyors." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 44, no. 9 (1997): 828–35. http://dx.doi.org/10.1109/81.622987.

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Radhakrishnan, D. "Low-voltage low-power CMOS full adder." IEE Proceedings - Circuits, Devices and Systems 148, no. 1 (2001): 19. http://dx.doi.org/10.1049/ip-cds:20010170.

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Wu, Xiang, and Fang Ming Deng. "A Capacitive Humidity Sensor for Low-Cost Low-Power Application." Applied Mechanics and Materials 556-562 (May 2014): 1847–51. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1847.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface employs a fully-digital architecture based on phase locked loop, which results in low pow dissipation. The proposed humidity sensor is fabricated in TSMC 0.18μm CMOS process and the chip occupies an area of 0.05mm2. The measurement result shows that the sensor value exhibits good linearity within the range of 10-90%RH and the interface circuit consumes only 1.05μW at 0.5V supply voltage.
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Song, Ming Xin, Shan Shan Wang, and Guo Dong Sun. "CMOS Low Power Ring VCO Design." Advanced Materials Research 981 (July 2014): 70–73. http://dx.doi.org/10.4028/www.scientific.net/amr.981.70.

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A design project of voltage controlled oscillator which is the central component of the low voltage phase locked loop (PLL) is proposed in this paper. The VCO adopted the folding differential voltage controlled oscillator.Simulation results in Cadence Hspice indicate that the VCO proposed behaves in good linearity, simple structure, small phase noise.The frequency range from 125 to 787 MHz, the power consumption of this oscillator is only 6mW at central frequency is 480MHz with 3V power supply.
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Dissertations / Theses on the topic "Low-power CMOS"

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Park, Byeong-Ha. "A low-voltage, low-power, CMOS 900MHZ frequency synthesizer." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/16686.

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Yeh, David Alexander. "Multi-gigabit low-power wireless CMOS demodulator." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41168.

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This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.
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Di, Pede Luigi. "A 1 V low-power CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/MQ34130.pdf.

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Zuber, Paul. "Wire topology optimisation for low power CMOS." kostenfrei, 2007. http://mediatum2.ub.tum.de/doc/618152/document.pdf.

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Shepherd, Leila Maryam. "Low-power computational interfacing for CMOS ISFETs." Thesis, Imperial College London, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.497646.

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Leistad, Tor Erik. "Delay-Fault BIST in Low-Power CMOS Devices." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8877.

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Devices such as microcontrollers are often required to operate across a wide range of voltage and temperature. Delay variation in different temperature and voltage corners can be large, and for deep submicron geometries delay faults are more likely than for larger geometries. This has made delay fault testing necessary. Scan testing is widely used as a method for testing, but it is slow due to time spent on shifting test vectors and responses, and it also needs modification to support delay testing. This assignment is divided into three parts. The first part investigates some of the effects in deep submicron technologies, then it looks at different fault models, and at last different techniques for delay testing and BIST approaches are investigated. The second part suggests a design for a test chip, including a circuit under test (CUT) and BIST logic. The final part investigates how the selected BIST logic can be used to reduce test time and what considerations needs to be made to get a optimal solution. The suggested design is a co-processor with SPI slave interface. Since scan based testing is commonly used today, STUMPS was selected as the BIST solution to use. Assuming that scan already is used, STUMPS will have little impact on the performance of the CUT since it is based on scan testing. During analysis it was found that several aspects of the CUT design affects the maximum obtainable delay fault coverage. It was also found that careful design of the BIST logic is necessary to get the best fault coverage and a solution that will reduce the overall cost. The results shows that a large amount of time can be saved during test by using BIST, but since the area of the circuit increases due to the BIST logic it necessarily don’t mean that one will reduce cost on the overall design. Whether or not a BIST solution will result in reduced cost will depend on the complexity of the circuit that is tested, how well the BIST logic fits this circuit, how many internal scan chains can be used, and how fast scan vectors can be applied under BIST. In this case it looks like the BIST logic is not well suited to detect the random hard to detect faults. This results in a large amount of top up patterns. This combined with the large area of the BIST logic makes it unlikely that BIST will reduce cost of this design.

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Ardalan, Kasra. "A low-power CMOS fractional-N frequency synthesizer." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0003/MQ40932.pdf.

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Chan, Wai Pan. "Robust low power CMOS methodologies for ISFETs instrumentation." Thesis, Imperial College London, 2010. http://hdl.handle.net/10044/1/6056.

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I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing.
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Chan, Tat Fu. "Low power low phase noise CMOS LC quadrature voltage-controlled oscillators /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHANT.

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Naik, Priti M. (Priti Manher) 1973. "Low voltage, low power CMOS operational amplifier design for switched capacitor circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9948.

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Books on the topic "Low-power CMOS"

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1945-, Brodersen Robert W., ed. Low power digital CMOS design. Kluwer Academic Publishers, 1995.

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Chandrakasan, Anantha P. Low Power Digital CMOS Design. Springer US, 1995.

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Chandrakasan, Anantha P., and Robert W. Brodersen. Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3.

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Sheng, Samuel, and Robert Brodersen. Low-Power CMOS Wireless Communications. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8.

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C, Guerrini Nicola, ed. Low-voltage low-power CMOS current conveyors. Kluwer Academic Publishers, 2003.

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Yeo, Kiat Seng. CMOS/BiCMOS ULSI: Low voltage, low power. Prentice Hall PTR, 2002.

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Roy, Kaushik. Low-power CMOS VLSI circuit design. Wiley, 2000.

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Soudris, Dimitrios, Christian Piguet, and Costas Goutis, eds. Designing CMOS Circuits for Low Power. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-3530-7.

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Itoh, Kiyoo, Thomas Lee, Takayasu Sakurai, Willy M. C. Sansen, and Doris Schmitt-Landsiedel, eds. Low Power VCO Design in CMOS. Springer-Verlag, 2006. http://dx.doi.org/10.1007/3-540-29256-x.

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João, Goes, and Steiger-Garção Adolfo, eds. Low power UWB CMOS radar sensors. Springer, 2008.

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Book chapters on the topic "Low-power CMOS"

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Saini, Sandeep. "CMOS Buffer." In Low Power Interconnect Design. Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4614-1323-3_2.

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Athas, William C. "Energy-Recovery CMOS." In Low Power Design Methodologies. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4615-2307-9_4.

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Bellaouar, Abdellatif, and Mohamed I. Elmasry. "VLSI CMOS Subsystem Design." In Low-Power Digital VLSI Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2355-0_7.

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Srivastava, Mani B. "Low Power Programmable Computation." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_10.

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Kim, Hyejung, and Hoi-Jun Yoo. "Low Power Bio-Medical DSP." In Bio-Medical CMOS ICs. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6597-4_6.

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Chandrakasan, Anantha P., and Robert W. Brodersen. "Sources of Power Consumption." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_3.

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Meindl, James D. "Hierarchy of Limits of Power." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_2.

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Chandrakasan, Anantha P., and Robert W. Brodersen. "Introduction." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_1.

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Chandrakasan, Anantha P., and Robert W. Brodersen. "Conclusions." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_11.

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Chandrakasan, Anantha P., and Robert W. Brodersen. "Voltage Scaling Approaches." In Low Power Digital CMOS Design. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_4.

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Conference papers on the topic "Low-power CMOS"

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Dokic, Branko L., Tatjana Pesic-Brdanin, and Drago Cavka. "Low-voltage low-power CMOS design." In 2016 International Symposium on Industrial Electronics (INDEL). IEEE, 2016. http://dx.doi.org/10.1109/indel.2016.7797813.

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Schoebinger, Matthias, and Tobias G. Noll. "Low power CMOS design strategies." In the 31st annual conference. ACM Press, 1994. http://dx.doi.org/10.1145/196244.196574.

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Chen, An. "Low-power beyond-CMOS devices." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021204.

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Yang, Xiao, Jing Yang, Li-fen Lin, and Chao-dong Ling. "Low-power low-noise CMOS chopper amplifier." In 2010 International Conference on Anti-Counterfeiting, Security and Identification (2010 ASID). IEEE, 2010. http://dx.doi.org/10.1109/icasid.2010.5551831.

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Hill, C. "Design of a low power HF CMOS filter." In IEE Seminar Low Power IC Design. IEE, 2001. http://dx.doi.org/10.1049/ic:20010014.

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Sakphrom, Siraporn, and Apinunt Thanachayanont. "A low-power CMOS RF power detector." In 2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012). IEEE, 2012. http://dx.doi.org/10.1109/icecs.2012.6463771.

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Steyaert, M. "Single Chip CMOS RF Transceivers: wishful thinking or reality." In IEE Seminar Low Power IC Design. IEE, 2001. http://dx.doi.org/10.1049/ic:20010007.

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Lee, J. "Linear Bi-CMOS transconductor for gm-C filter applications." In IEE Seminar Low Power IC Design. IEE, 2001. http://dx.doi.org/10.1049/ic:20010015.

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Calvo, B., M. Sanz, and S. Celma. "Low-voltage Low-power CMOS Programmable Gain Amplifier." In 2006 International Caribbean Conference on Devices, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/iccdcs.2006.250844.

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Bonteanu, Gabriel, and Arcadie Cracan. "Low Power and Low Area CMOS Capacitance Multiplier." In 2018 International Semiconductor Conference (CAS). IEEE, 2018. http://dx.doi.org/10.1109/smicnd.2018.8539846.

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