Log in

Relevant bibliographies by topics / Low power comparator ADC SAR ADC / Journal articles

To see the other types of publications on this topic, follow the link: Low power comparator ADC SAR ADC.

Journal articles on the topic 'Low power comparator ADC SAR ADC'

Author: Grafiati

Published: 4 June 2025

Last updated: 15 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Low power comparator ADC SAR ADC.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Sajja, Amrita, and S. Rooban. "Design of Low Power SAR ADC with Novel Regenerative Comparator." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (December 31, 2023): 166–72. http://dx.doi.org/10.37394/23201.2023.22.19.

Full text

Abstract:

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded c

APA, Harvard, Vancouver, ISO, and other styles

2

Et.al, Yarlagadda Archana. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3046–54. http://dx.doi.org/10.17762/turcomat.v12i3.1339.

Full text

Abstract:

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The

APA, Harvard, Vancouver, ISO, and other styles

3

Kakarla Hari Kishore, Yarlagadda Archana,. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 144–52. http://dx.doi.org/10.17762/turcomat.v12i5.806.

Full text

Abstract:

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The

APA, Harvard, Vancouver, ISO, and other styles

4

Prasanna, P. Durga. "Implementation of 8-Bit Asynchronous SAR ADC." International Journal for Research in Applied Science and Engineering Technology 13, no. 2 (2025): 979–83. https://doi.org/10.22214/ijraset.2025.67010.

Full text

Abstract:

This study analyses the design of SAR ADC that is suitable for implementing in low power applications. The designed SAR ADC minimizes the complexities associated with its design using higher frequencies by avoiding the usage of oversampled clock. A Bootstrap circuit is designed for a sampling and holding which improves increased linearity. Another aspect of the low power is designing a comparator such that it does not require a pre-amplifier. Successive Approximation register (SAR) ADC is implemented using a charge redistribution DAC. The SAR logic block generates the digital code thus reducin

APA, Harvard, Vancouver, ISO, and other styles

5

Xu, Daiguo, Kaikai Xu, Shiliu Xu, Lu Liu, and Tao Liu. "A System-Level Correction SAR ADC with Noise-Tolerant Technique." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850202. http://dx.doi.org/10.1142/s021812661850202x.

Full text

Abstract:

A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed smal

APA, Harvard, Vancouver, ISO, and other styles

6

Hong, Hui, Shi Liang Li, and Shuai Liu. "Design of a Low Power Multi-Channel 10Bit SAR ADC." Applied Mechanics and Materials 513-517 (February 2014): 4576–79. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4576.

Full text

Abstract:

To meet the demand of low power multi-channel ADCs, a 10bit 4-channels SAR ADC using CSMC 0.35um 3.3V 2P4M technology was designed. By optimizing the power dissipation of the interior comparator and the interior DAC, the designed ADC costs only 300uW under 2V single supply with a sampling rate as high as 300KS/s. Meanwhile 1024 points FFT was used with MATLAB tools to analysis and calculate the converted results of the SAR ADC and the calculated results shown the SNR is about 60dB, ENOB is 9.6bit, DNL is 0.033LSB and the INL is 0.312LSB.

APA, Harvard, Vancouver, ISO, and other styles

7

Lee, Sang-Hun, and Won-Young Lee. "A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction." Sensors 22, no. 16 (2022): 6078. http://dx.doi.org/10.3390/s22166078.

Full text

Abstract:

This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampli

APA, Harvard, Vancouver, ISO, and other styles

8

Lakshmi, Posani Vijaya, Sarada Musala, Avireni Srinivasulu, and Cristian Ravariu. "Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices." Electronics 12, no. 22 (2023): 4691. http://dx.doi.org/10.3390/electronics12224691.

Full text

Abstract:

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC.

APA, Harvard, Vancouver, ISO, and other styles

9

Amrita, Sajja, and Rooban S. "Design of 10 Bit ADC of SAR Type to Increase the Accuracy for Biomedical Applications." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 2291–94. https://doi.org/10.35940/ijeat.C5309.029320.

Full text

Abstract:

In this paper a low power consuming 10 bit SAR ADC which is suitable for Biomedical applications is presented. It was designed with 180nm technology using cadence tool. SAR ADC is made of dynamic comparator, sample and hold circuit, SAR logic, and DAC block. The designed circuit works on a supply voltage of 1V. The proposed SAR design, with the use of dynamic comparator circuit will help to reduce power and even at the same time with the use of binary weighted CDAC also provides low power dissipation. In order to decide the next significant bit by the knowledge of previous bits the successive

APA, Harvard, Vancouver, ISO, and other styles

10

Julie, Roslita Rusli, Shafie Suhaidi, Mohd Sidek Roslina, Abdul Majid Hasmayadi, Z. Wan Hassan W., and Mustafa M.A. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 17, no. 2 (2020): 783–92. https://doi.org/10.11591/ijeecs.v17.i2.pp783-792.

Full text

Abstract:

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 1

APA, Harvard, Vancouver, ISO, and other styles

11

Vasudeva, G., and B. V. Uma. "Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (January 3, 2022): 1–15. http://dx.doi.org/10.37394/23203.2022.17.1.

Full text

Abstract:

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logi

APA, Harvard, Vancouver, ISO, and other styles

12

Verma, Deeksha, Khuram Shehzad, Danial Khan, et al. "A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application." Electronics 9, no. 7 (2020): 1100. http://dx.doi.org/10.3390/electronics9071100.

Full text

Abstract:

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To

APA, Harvard, Vancouver, ISO, and other styles

13

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

Full text

Abstract:

CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

APA, Harvard, Vancouver, ISO, and other styles

14

Faheem, Muhammad Yasir, Shun'an Zhong, Xinghua Wang, and Muhammad Basit Azeem. "Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology." Circuit World 46, no. 3 (2020): 183–92. http://dx.doi.org/10.1108/cw-09-2019-0127.

Full text

Abstract:

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main ide

APA, Harvard, Vancouver, ISO, and other styles

15

R, Yashaswini, and Kumar N. Krishna Murthy. "Design and Simulation of 16 Bit ADC." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 1017–24. http://dx.doi.org/10.22214/ijraset.2023.54790.

Full text

Abstract:

Abstract: In this study, it was looked into how a 16-bit architecture might be used to develop an Analog-to-Digital Converter (ADC) Successive Approximation Register (SAR). The SAR ADC architecture is widely adopted for high-resolution applications because to its ease of use and minimal power requirements. The design also includes a voltage reference, a comparator, a successive approximation register, a sample-and-hold circuit, an analog-to-digital converter (DAC), and other components. A range of design approaches and circuit topologies are employed to maximize performance and satisfy the req

APA, Harvard, Vancouver, ISO, and other styles

16

Silpa, Kesav Velagaleti, K. S. Nayanathara, and B. K. Madhavi. "A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system." TELKOMNIKA Telecommunication, Computing, Electronics and Control 19, no. 2 (2021): pp. 547~555. https://doi.org/10.12928/TELKOMNIKA.v19i2.18318.

Full text

Abstract:

In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch

APA, Harvard, Vancouver, ISO, and other styles

17

Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

Full text

Abstract:

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementa

APA, Harvard, Vancouver, ISO, and other styles

18

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

Full text

Abstract:

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are

APA, Harvard, Vancouver, ISO, and other styles

19

Bechen, B., D. Weiler, T. v. d. Boom, and B. J. Hosticka. "A 10 bit very low-power CMOS SAR-ADC for capacitive micro-mechanical pressure measurement in implants." Advances in Radio Science 4 (September 6, 2006): 243–46. http://dx.doi.org/10.5194/ars-4-243-2006.

Full text

Abstract:

Abstract. This paper presents the development of a 10 bit very low-power CMOS SAR-ADC to be used in medical implants. The first part discusses the principle schematic and the requirements for component matching and the comparator of the ADC. Additionally, the measurement results of a fabricated test chip will be given. The second part of this paper discusses the possibility of direct on-chip implementation of a capacitive pressure sensor in a switched-capacitor SAR-ADC.

APA, Harvard, Vancouver, ISO, and other styles

20

Xin, Xin, Jueping Cai, Ruilian Xie, and Peng Wang. "Ultra‐low power comparator with dynamic offset cancellation for SAR ADC." Electronics Letters 53, no. 24 (2017): 1572–74. http://dx.doi.org/10.1049/el.2017.2916.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Chen, Yushi, Yiqi Zhuang, and Hualian Tang. "An Ultra-Low Power Consumption High-Linearity Switching Scheme for SAR ADC." Journal of Circuits, Systems and Computers 29, no. 06 (2019): 2050086. http://dx.doi.org/10.1142/s0218126620500863.

Full text

Abstract:

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in li

APA, Harvard, Vancouver, ISO, and other styles

22

Song, Zheng, Zhi-Hua Ma, Yao Yao, Ren-fei Zou та Jian-Guo Hu. "A ENOB 10.3 bit, 103 μW ON-CHIP CALIBRATION SAR ADC". Journal of Physics: Conference Series 2524, № 1 (2023): 012019. http://dx.doi.org/10.1088/1742-6596/2524/1/012019.

Full text

Abstract:

Abstract Across the board, the performance of ADCs has been under increasing scrutiny because of the rapid growth of portable electronic devices and biomedical sensors. As part of the sensor’s long-term work, its power consumption should also be as low as possible. Sensors benefit from SAR ADCs’ small size and low power consumption, making them an ideal fit for ADCs. To overcome the limitations of accuracy and linearity of ADCs caused by manufacturing process deviations, a 12-bit, 1 MS/s low-power SAR ADC based on 180 nm CMOS technology is presented. The front-end analog calibration system ens

APA, Harvard, Vancouver, ISO, and other styles

23

Chen, Yanbo, Qiong Nie, Chaowei Zhong, et al. "A 24 nW 10-bit 10 kS/s ultra-low-power SAR ADC for biomedical devices." AIP Advances 13, no. 2 (2023): 025351. http://dx.doi.org/10.1063/5.0138835.

Full text

Abstract:

This paper proposed an ultra-low-power successive approximation register analog to digital converter (ADC) for medical implant devices. To reduce power consumption, the novel techniques presented in this paper are a tri-state capacitor unit, a novel switch scheme, and a new low static power comparator. Tri-state capacitor unit reduces down power without the use of middle voltage reference. The proposed switch scheme can complete the most-significant bit 3-bit conversion without any power consumption. The offset of the low static power comparator is only optimized by physical design. This ADC i

APA, Harvard, Vancouver, ISO, and other styles

24

Yang, Hongyuan, Jiahao Cheong, and Cheng Liu. "A 13.44-Bit Low-Power SAR ADC for Brain–Computer Interface Applications." Applied Sciences 15, no. 10 (2025): 5494. https://doi.org/10.3390/app15105494.

Full text

Abstract:

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power consumption at a supply voltage of 1.8 V, enabled by a piecewise monotonic switching scheme and dynamic logic architecture. The ADC supports a high input range of ±500 mV, making it suitable for neural signal acquisition. Through an optimized capacitive digital-to-analog co

APA, Harvard, Vancouver, ISO, and other styles

25

Baek, Jihyun, Juyong Lee, Jintae Kim, and Hyungil Chae. "2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure." Electronics 11, no. 19 (2022): 3072. http://dx.doi.org/10.3390/electronics11193072.

Full text

Abstract:

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling

APA, Harvard, Vancouver, ISO, and other styles

26

Lee, Juyong, Seungjun Lee, Kihyun Kim, and Hyungil Chae. "A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier." Electronics 10, no. 16 (2021): 1968. http://dx.doi.org/10.3390/electronics10161968.

Full text

Abstract:

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power

APA, Harvard, Vancouver, ISO, and other styles

27

Ahmadi, Muhammad, and Won Namgoong. "Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 11 (2015): 2384–94. http://dx.doi.org/10.1109/tvlsi.2014.2362545.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

ZHU, ZHANGMING, YU XIAO, LIANG LIANG, LIANXI LIU та YINTANG YANG. "A 3.03 μW 10-BIT 200 KS/s SAR ADC IN 0.18 μM CMOS". Journal of Circuits, Systems and Computers 22, № 04 (2013): 1350026. http://dx.doi.org/10.1142/s0218126613500266.

Full text

Abstract:

Based on TSMC 0.18 μm 1.8 V CMOS process, a low power 10-bit 200 KS/s successive approximation register (SAR) analog-to-digital (ADC) is realized. This paper mainly considers the improvement of linearity and the optimization of power consumption. And a novel switching sequence is proposed which allows both to achieve a better compromise. Moreover, the fully dynamic comparator, which consumes no static power, and the optimization of SAR control logic, further reduce power consumption. The simulation results show that at 1.0 V supply and 200 KS/s, the ADC achieves an signal-to-noise and distorti

APA, Harvard, Vancouver, ISO, and other styles

29

Gao, Bo, Xin Li, Jie Sun, and Jianhui Wu. "Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM." Electronics 9, no. 1 (2020): 137. http://dx.doi.org/10.3390/electronics9010137.

Full text

Abstract:

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise

APA, Harvard, Vancouver, ISO, and other styles

30

An, Shengbiao, Shuang Xia, Yue Ma, et al. "A Low Power Sigma-Delta Modulator with Hybrid Architecture." Sensors 20, no. 18 (2020): 5309. http://dx.doi.org/10.3390/s20185309.

Full text

Abstract:

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a

APA, Harvard, Vancouver, ISO, and other styles

31

Huang, Yajie, Chao Luo, and Guoping Guo. "A Cryogenic 8-Bit 32 MS/s SAR ADC Operating down to 4.2 K." Electronics 12, no. 6 (2023): 1420. http://dx.doi.org/10.3390/electronics12061420.

Full text

Abstract:

This paper presents a cryogenic 8-bit 32 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) which operates down to 4.2 K. This work uses a modified liquid helium temperature (LHT) SMIC 0.18 μm CMOS technology to support the post-layout simulation. The proposed architecture adopts an offset-promoted dynamic comparator, waveform shaping circuit and true single-phase clock (TSPC) based sar logic circuit to achieve high realizing frequency and low power dissipation. At 1.8-V supply, 1.7 V input amplitude and 32 MS/s sampling frequency, the ADC achieves a power consumpti

APA, Harvard, Vancouver, ISO, and other styles

32

Jung, Hoyong, Eunji Youn, and Young-Chan Jang. "An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration." Electronics 11, no. 22 (2022): 3654. http://dx.doi.org/10.3390/electronics11223654.

Full text

Abstract:

An 11-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for low-power and small-area applications. A 10-bit differential capacitor–resistor (C–R) digital-to-analog converter (DAC) is used to minimize the area of a DAC. The use of a C–R DAC reduces the capacitor area of a SAR ADC used CDAC by 75%. A capacitor calibration for the upper 5-bit capacitors of the C–R DAC is proposed to increase the linearity of the C–R DAC. To evaluate the proposed SAR ADC, an 11-bit 10 MS/s SAR ADC is implemented using a 180 nm 1-poly six-metal CMOS process with a sup

APA, Harvard, Vancouver, ISO, and other styles

33

Huang, Chong-Cheng, Guo-Ming Sung, Xiong Xiao, Shan-Hao Sung, and Chao-Hung Huang. "Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive." Electronics 10, no. 7 (2021): 830. http://dx.doi.org/10.3390/electronics10070830.

Full text

Abstract:

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multipl

APA, Harvard, Vancouver, ISO, and other styles

34

INANLOU, REZA, and MOHAMMAD YAVARI. "A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450026. http://dx.doi.org/10.1142/s0218126614500261.

Full text

Abstract:

In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digita

APA, Harvard, Vancouver, ISO, and other styles

35

Zghoul, Fadi Nessir, Yousra Hussein Al-Bakrawi, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 4 (2024): 3830. http://dx.doi.org/10.11591/ijece.v14i4.pp3830-3854.

Full text

Abstract:

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide se

APA, Harvard, Vancouver, ISO, and other styles

36

Hu, Yunfeng, Qingming Huang, Bin Tang, et al. "A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications." Micromachines 14, no. 12 (2023): 2244. http://dx.doi.org/10.3390/mi14122244.

Full text

Abstract:

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic com

APA, Harvard, Vancouver, ISO, and other styles

37

Jung, Inseok, Kyung Ki Kim, and Yong-Bin Kim. "A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC." Journal of Integrated Circuits and Systems 10, no. 3 (2015): 187–200. http://dx.doi.org/10.29292/jics.v10i3.422.

Full text

Abstract:

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The contro

APA, Harvard, Vancouver, ISO, and other styles

38

Hwang, Young‐Ha, and Deog‐Kyoon Jeong. "Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC." Electronics Letters 54, no. 24 (2018): 1370–72. http://dx.doi.org/10.1049/el.2018.6340.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Al-Naamani, Yahya Mohammed Ali, K. Lokesh Krishna, and A. M. Guna Sekhar. "A Successive Approximation Register Analog to Digital Converter for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 1 (2020): 451–55. http://dx.doi.org/10.1166/jctn.2020.8689.

Full text

Abstract:

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in t

APA, Harvard, Vancouver, ISO, and other styles

40

Bekal, Anush, Shabi Tabassum, and Manish Goswami. "Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750077. http://dx.doi.org/10.1142/s0218126617500773.

Full text

Abstract:

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of t

APA, Harvard, Vancouver, ISO, and other styles

41

Xu, Daiguo, Hequan Jiang, Dongbin Fu, et al. "A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique." Journal of Circuits, Systems and Computers 29, no. 06 (2019): 2050084. http://dx.doi.org/10.1142/s021812662050084x.

Full text

Abstract:

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the

APA, Harvard, Vancouver, ISO, and other styles

42

Wang, Deming, Jing Hu, Xin Huang, and Qinghua Zhong. "Design of a 12-Bit SAR ADC with Calibration Technology." Electronics 13, no. 3 (2024): 548. http://dx.doi.org/10.3390/electronics13030548.

Full text

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply

APA, Harvard, Vancouver, ISO, and other styles

43

Hu, Yunfeng, Bin Tang, Lexing Hu, et al. "A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications." Micromachines 13, no. 12 (2022): 2110. http://dx.doi.org/10.3390/mi13122110.

Full text

Abstract:

This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CVref2, achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of Vcm and complexity of DAC control logic and DAC driver circuit. Mo

APA, Harvard, Vancouver, ISO, and other styles

44

Nessir, Zghoul Fadi, Al-Bakrawi Yousra Hussein, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology 14, no. 4 (2024): 3830–54. https://doi.org/10.11591/ijece.v14i4.pp3830-3854.

Full text

Abstract:

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked

APA, Harvard, Vancouver, ISO, and other styles

45

Zhang, Yu, Yilin Pu, Bin Wu, Taishan Mo, and Tianchun Ye. "A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems." Applied Sciences 13, no. 12 (2023): 7040. http://dx.doi.org/10.3390/app13127040.

Full text

Abstract:

This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, a 4-reference voltage method to minimize capacitive digital-to-analog converter (CDAC) mismatch, a kickback-canceling comparator to eliminate kick-back noise, and redundant design-assisted window-opening SAR logic to decrease conversion time. Expe

APA, Harvard, Vancouver, ISO, and other styles

46

Kim, Kihyun, Sein Oh, and Hyungil Chae. "Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC." Electronics 10, no. 20 (2021): 2545. http://dx.doi.org/10.3390/electronics10202545.

Full text

Abstract:

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference

APA, Harvard, Vancouver, ISO, and other styles

47

Liu, K., S. Fang, Y. Wang, and Z. Huang. "Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones." Journal of Physics: Conference Series 2740, no. 1 (2024): 012044. http://dx.doi.org/10.1088/1742-6596/2740/1/012044.

Full text

Abstract:

Abstract A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hi

APA, Harvard, Vancouver, ISO, and other styles

48

A. Jyotsna, K., P. Satish Kumar, B. K. Madhavi, and I. Swaroopa. "Implementation of 16 Bit SAR ADC in CMOS and sub threshold cml techniques." International Journal of Engineering & Technology 7, no. 2.12 (2018): 257. http://dx.doi.org/10.14419/ijet.v7i2.12.11298.

Full text

Abstract:

The trends of the VLSI technology is advancing, due to this majority of the industry players are showing interest in development of the devices with ultra low power applications. Analog-to-Digital converters are getting extensively used in Medical implant machines and in lots of Sensor machines, because it is serving an imperative role in interfacing between analog signal and digital signal. This paper presents a modernistic technique called as Sub threshold Current Mode Logic (CML) for ultra low power digital components. Here 16 bit SAR ADC is designed and compared with the techniques like CM

APA, Harvard, Vancouver, ISO, and other styles

49

Shehzad, Khuram, Deeksha Verma, Danial Khan, et al. "Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator." Electronics 9, no. 5 (2020): 872. http://dx.doi.org/10.3390/electronics9050872.

Full text

Abstract:

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic p

APA, Harvard, Vancouver, ISO, and other styles

50

Hu, Yunfeng, Chaoyi Chen, Qingming Huang, et al. "A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications." Micromachines 15, no. 1 (2023): 60. http://dx.doi.org/10.3390/mi15010060.

Full text

Abstract:

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the diffic

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!