Relevant bibliographies by topics / Low-power design and verification

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Low-power design and verification'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "Low-power design and verification"

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Liu, Guo Feng, Xi Liu, and Xing Guo Tian. "Design of low-power 2FSK demodulation circuit." MATEC Web of Conferences 232 (2018): 04069. http://dx.doi.org/10.1051/matecconf/201823204069.

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Aiming at the complex structure and high power consumption of the existing 2FSK demodulation circuit, this paper designs a simple structure and low power 2FSK demodulation circuit. A CMOS transistor matrix circuit is used to demodulate the 2FSK signals of 1200HZ and 2200HZ. The function model is established by using Matlab, and the number of sampling points is determined according to the simulation results and design requirements, and then the size of CMOS transistor matrix circuit is determined. The circuit uses Cadence software for functional verification, and HSPICE software is used for power consumption analysis. The simulation results meet the design requirements of low power consumption and achieve the desired demodulation effect.
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Potočný, Miroslav, Viera Stopjaková, and Martin Kováč. "Design and verification of a low-power AC/DC converter." Journal of Electrical Engineering 72, no. 2 (2021): 113–18. http://dx.doi.org/10.2478/jee-2021-0015.

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Abstract This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.
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Haripriya, K. R., Ajay Somkuwar, and Laxmi Kumre. "Low Power Checks in Multi Voltage Designs." WSEAS TRANSACTIONS ON ELECTRONICS 11 (July 1, 2020): 105–11. http://dx.doi.org/10.37394/232017.2020.11.13.

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Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.
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Kapoor, Bhanu, and Shireesh Verma. "Power Management Design and Verification." Journal of Low Power Electronics 7, no. 1 (2011): 41–48. http://dx.doi.org/10.1166/jolpe.2011.1115.

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Mankar, Pranav J., Ajinkya M. Pund, Kunal P. Ambhore, and Shubham C. Anjankar. "Design and Verification of Low Power DA-Adaptive Digital FIR Filter." Procedia Computer Science 79 (2016): 367–73. http://dx.doi.org/10.1016/j.procs.2016.03.048.

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Asha Devi, Dharmavaram, Chintala Sandeep, and Sai Sugun L. "Design of Power Efficient 32-Bit Processing Unit." International Journal of Engineering & Technology 7, no. 2.16 (2018): 52. http://dx.doi.org/10.14419/ijet.v7i2.16.11415.

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The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit. The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.
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DHURY, S. CHOU, G. K. SINGH, and R. M. ME HRA. "Design and Verification Serial Peripheral Interface (SPI) Protocol for Low Power Applications." International Journal of Innovative Research in Science, Engineering and Technology 03, no. 10 (2014): 16750–58. http://dx.doi.org/10.15680/ijirset.2014.0310048.

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Rahman, Nahid, and B. P. Singh. "Design and Verification of Low Power SRAM using 8T SRAM Cell Approach." International Journal of Computer Applications 67, no. 18 (2013): 11–15. http://dx.doi.org/10.5120/11494-7201.

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Verma, Shireesh. "A Special Issue on Low Power Design and Verification Techniques." Journal of Low Power Electronics 7, no. 1 (2011): 1. http://dx.doi.org/10.1166/jolpe.2011.1111.

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Yadlapati, Avinash, and K. Hari Kishore. "Low power synthesis for asynchronous FIFO using unified power format (UPF)." International Journal of Engineering & Technology 7, no. 2.8 (2018): 7. http://dx.doi.org/10.14419/ijet.v7i2.8.10315.

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Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.
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Dissertations / Theses on the topic "Low-power design and verification"

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Andersson, Johan, and Adam Schelander. "Design and verification of automotive power supply." Thesis, Linköpings universitet, Fysik och elektroteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-150147.

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In the current and next generation automotive telematic platforms, high demands are put on high efficiency power supplies. This thesis investigates different switch mode power converter solutions that operates with high efficiency for both low and high power loads. A market survey was conducted alongside meetings with ACTIA Nordic and their subcontractors. Three solutions from the market survey were selected for further investigation. One solution from the investigation was selected and implemented as a demonstration platform for further testing. The result shows a full test sequence for the designed power supply solution.
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Sun, Jin. "Conquering Variability for Robust and Low Power Designs." Diss., The University of Arizona, 2011. http://hdl.handle.net/10150/145458.

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As device feature sizes shrink to nano-scale, continuous technology scaling has led to a large increase in parameter variability during semiconductor manufacturing process. According to the source of uncertainty, parameter variations can be classified into three categories: process variations, environmental variations, and temporal variations. All these variation sources exert significant influences on circuit performance, and make it more challenging to characterize parameter variability and achieve robust, low-power designs. The scope of this dissertation is conquering parameter variability and successfully designing efficient yet robust integrated circuit (IC) systems. Previous experiences have indicated that we need to tackle this issue at every design stage of IC chips. In this dissertation, we propose several robust techniques for accurate variability characterization and efficient performance prediction under parameter variations. At pre-silicon verification stage, a robust yield prediction scheme under limited descriptions of parameter uncertainties, a robust circuit performance prediction methodology based on importance of uncertainties, and a robust gate sizing framework by ElasticR estimation model, have been developed. These techniques provide possible solutions to achieve both prediction accuracy and computation efficiency in early design stage. At on-line validation stage, a dynamic workload balancing framework and an on-line self-tuning design methodology have been proposed for application-specific multi-core systems under variability-induced aging effects. These on-line validation techniques are beneficial to alleviate device performance degradation due to parameter variations and extend device lifetime.
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Hornæs, Daniel. "Low-Cost FPU : Specification, Implementation and Verification." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-11145.

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This report aims to provide a complete specification of an IEEE-754 1985 compliantdesign, as well as a working, synthesizable implementation in Verilog HDL. Thereport is based on a preliminary project, which analyzed the IEEE-754 standardand suggested a set of algorithms suitable for a compact realization.Through traditional methods of both algorithmic analysis and dataanalysis,requirements of functional units are derived, and operations are scheduled.A set of functional simulations assert the correctness of the design, while areaand performance analysis provides information on the speedup gained, versus thehardware cost.Finally, the results obtained are compared to existing implementations, bothhardware and software.
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Hu, Xin. "RF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency and Controllable Bandwidth: Design Sythesis and Verification." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright149572725296626.

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Piiroinen, M. (Mika). "Design and verification of bonded GaN power amplifier for the 5G." Master's thesis, University of Oulu, 2017. http://urn.fi/URN:NBN:fi:oulu-201710132996.

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In this thesis a bonded Gallium nitride (GaN) power amplifier (PA) is designed using 3D modeling tool to design layout for the gate and drain matching elements for the GaN PA including bondwires. 1D circuit simulator is used to simulate the PA operation with 3D simulated matching blocks and large signal GaN device model. GaN device used in this design is Qorvo’s TGF2023-2-02. 3D simulated drain and gate matching layouts are based on the TGF2023-2-02 datasheet’s loadpull data and the large signal simulations. The target operational frequency for the power amplifier is from 5.6 GHz to 6.0 GHz. The main design goal is to achieve 60% drain efficiency, 36 dBm maximum output power and over 12 dB gain in the operational band. With simulations, 59.2% drain efficiency, 41.5 dBm output power and 15.8 dB gain is achieved using 28 V drain voltage. According to the measurements, the highest drain efficiency is 59.2% using lower 18 V drain voltage. With measurements, 37.04 dBm drain efficiency and 14.2 dB gain were achieved using the lower drain voltage. This means that the fabricated power amplifier achieves the designed output power and gain targets while the drain efficiency is only 0.8 pp lower than the target<br>Tässä diplomityössä suunnitellaan bondattu galliumnitridi (GaN) RF-tehovahvistin käyttäen 3D mallinnustyökalua GaN tehovahvistimen hilan ja nielun impedanssi sovituksien suunnitteluun ja mallintamiseen. Mallinnus sisältää myös bondauslangat. 1D piirisimulaattorilla simuloitiin tehovahvistimen toimintaa käyttäen 3D simuloituja sovituksia ja GaN vahvistimen suursignaalimallia. Tässä työssä käytetty GaN tehovahvistin on Qorvon valmistama TGF2023-2-02. Simuloidut nielun ja hilan sovituselementit perustuvat suursignaali simulointeihin sekä TGF2023-2-02:n datalehden loadpull-dataan. Tehovahvistin suunnitellaan 5,6–6,0 GHz taajuusalueelle. Tavoitteena on saavuttaa 60% nieluhyötysuhde, 36 dBm lähtöteho ja yli 12 dB vahvistus. Simuloinneissa saavutetaan 59,2 % nieluhyötysuhde, 41,5 dBm lähtöteho ja 15,8 dB vahvistus käyttäen 28 V nielujännitettä. Mittauksissa suurin nieluhyötysuhde, 59,2% saavutetaan alemmalla, 18 V nielujännitteellä. Alemmalla nielujännitteellä suurin lähtöteho on 37,04 dBm ja vahvistus 14,2 dB. Tämä tarkoittaa sitä, että lähtöteho ja vahvistus tavoitteisiin päästään. Nielun hyötysuhde on vain 0,8 prosenttiyksikköä alle tavoitteen
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Li, Qiong. "Developing Modeling and Simulation Methodology for Virtual Prototype Power Supply System." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/27462.

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This dissertation develops a modeling and simulation methodology for design, verification, and testing (DVT) power supply system using a virtual prototype. The virtual prototype is implemented before the hardware prototyping to detect most of the design errors and circuit deficiencies that occur in the later stage of a standard hardware design verification and testing procedure. The design iterations and product cost are reduced significantly by using this approach. The proposed modeling and simulation methodology consists of four major parts: system partitioning, multi-level modeling of device/function block, hierarchical test sequence, and multi-level simulation. By applying the proposed methodology, the designer can use the virtual prototype effectively by keeping a short simulation CPU time as well as catching most of the design problems. The proposed virtual prototype DVT procedure is demonstrated by simulating a 5 V power supply system with a main power supply, a bias power supply, and other protection, monitoring circuitry. The total CPU time is about 8 hours for 780 tests that include the basic function test, steady stage analysis, small-signal stability analysis, large-signal transient analysis, subsystem interaction test, and system interaction test. By comparing the simulation results with the measurements, it shows that the virtual prototype can represent the important behavior of the power supply system accurately. Since the proposed virtual prototype DVT procedure verifies the circuit design with different types of the tests over different line and load conditions, many circuit problems that are not obvious in the original circuit design can be detected by the simulation. The developed virtual prototype DVT procedure is not only capable of detecting most of the design errors, but also plays an important role in design modifications. This dissertation also demonstrates how to analyze the anomalies of the forward converter with active-clamp reset circuit extensively and facilitate the design and improve the circuit performances by utilizing the virtual prototype. With the help of the virtual prototype, it is the first time that the designer is able to analyze the dynamic behavior of the active-clamp forward converter during large-signal transient and optimize the design correspondingly.<br>Ph. D.
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HOLMÉR, NIKLAS. "Design and Verification of MIL for Linear Actuator." Thesis, KTH, Skolan för industriell teknik och management (ITM), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-278895.

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In a world where development of new technology moves rapidly towards renewable energy resources, it is important to implement new technology for efficiency improvement on existing products. This is Cascade Drives ambition, to enable a shift from hydraulic usage in heavy vehicles to a solution that is completely electromechanical driven, to improve energy efficiency.  Currently, Cascade Drives are developing electromechanical linear actuators to replace hydraulic driven actuators in heavy vehicles such as forklifts, both for lifting and steering applications.  These actuators are designed with a rack and pinion setup where multiple pinions are placed on a single rack and by using a patented flexible solution, an otherwise overdetermined system can share the load evenly over the pinions. This significantly reduce the size of each pinion and the overall package.  This master thesis aims at investigating the power losses in this electromechanical actuator and implement a model in the loop (MIL) to predict the efficiency and how this alters for different speeds and loads applied on the actuator.  A model to predict the efficiency was implemented in Simulink software and two different verification tests on physical prototypes were conducted. The results showed that the predicted load dependent losses corresponded well to the measured values. The speed dependent losses proved harder to predict.<br>I en värld där utveckling av ny teknik rör sig snabbt mot förnybara energikällor är det viktigt att implementera ny teknik för effektivisering av befintliga produkter. Detta är Cascade Drives ambition, att möjliggöra en övergång från användandet av hydraulik i tunga applikationer till en lösning som är elektromekaniskt driven, för att förbättra energieffektiviteten.  För närvarande utvecklar Cascade Drives elektromekaniska ställdon för att ersätta hydrauliskt drivna ställdon i tunga fordon så som gaffeltruckar, både för lyft- och styrapplikationer.  Dessa ställdon är utformade med en rack- och kugghjulsuppsättning där flera kugghjul är i ingrepp med ett enda rack och genom att använda en patenterad flexibel lösning kan ett annars överbestämt system dela belastningen över alla kugghjul. Detta leder till att storleken på varje hjul kan minskas och även den totala storleken på produkten blir mindre.  Detta examensarbete syftar till att undersöka effektförlusterna i detta elektromekaniska ställdon och implementera en så kallad ”Model In the Loop” (MIL) för att förutsäga verkningsgraden och hur denna förändras för olika hastigheter och krafter som appliceras på ställdonet.  En modell för att prediktera verkningsgraden implementerades i Simulink programvara och två olika verifieringstester på fysiska prototyper genomfördes. Resultaten visade att prediktionen för de lastberoende förlusterna motsvarade de uppmätta värdena. De hastighetsberoende förlusterna visade sig svårare att förutsäga.
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Ralston, Parrish Elaine. "Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/36169.

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There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0â 40V) and high voltage (40â 5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed.<br>Master of Science
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Lipscomb, Melissa Anne. "A versatile simulation tool for the design and verification of military vehicle power systems." Thesis, Texas A&M University, 2005. http://hdl.handle.net/1969.1/2577.

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The design of the electric platform in military vehicles requires the ability to determine the best combination of power system components that support the desired operational abilities, while minimizing the size, weight, cost, and impact of the overall power system. Because prototypes are both time consuming, rigid, and costly, they have become inadequate for verifying system performance. By using simulations, engineers can best plan for and observe the associations between missions (including modes of operation and system scenarios) and system performance in a dynamic, realistic environment. This thesis proposes a new tool to analyze and design military vehicle platforms: the Advanced Mobile Integrated Power System (AMPS). This tool is useful for design and design verification of military vehicles due to its unique incorporation of mission-specific functionality. It allows the user ease of design with the ability to customize the vehicle power system architecture and components, while permitting full control over source and load input parameters. Simulation of programmed mission sequences allows the user to ensure that the chosen vehicle architecture can provide all of the electrical power and energy needed to support the mission, thus providing adequate design verification. The present thesis includes an introduction to vehicle power systems and an outline of the need for simulation, a description of the AMPS project and vehicle specifications, analytical and numerical models of the simulated vehicle, explanation of the power management system, description of the graphical user interface, and a simulation performed with the AMPS tool.
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Moynahan, Nathan A. "Development of a vehicle road load model for ECU broadcast power verification in on-road emissions testing." Morgantown, W. Va. : [West Virginia University Libraries], 2005. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=4454.

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Thesis (M.S.)--West Virginia University, 2005.<br>Title from document title page. Document formatted into pages; contains xi, 117 p. : ill. (some col.), col. map. Includes abstract. Includes bibliographical references (p. 75-77).
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Books on the topic "Low-power design and verification"

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Khondkar, Progyna. Low-Power Design and Power-Aware Verification. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-66619-8.

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Verification methodology manual for low power. Synopsys, 2009.

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Islam, Mohammed M. Shipboard Power Systems Design and Verification Fundamentals. John Wiley & Sons, Inc., 2018. http://dx.doi.org/10.1002/9781119084136.

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Design and verification of electrical installations. 8th ed. Routledge, 2012.

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Larsen, Gunner C. Verification of Design Basis Program 2: A coupled aeroelastic wind turbine model. Risø National Laboratory, 1994.

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Rabaey, Jan M. Low Power Design Methodologies. Springer US, 1996.

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Rabaey, Jan M. Low power design essentials. Springer, 2009.

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Segars, Simon Anthony. Low power microprocessor design. University of Manchester, 1996.

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Rabaey, Jan M., and Massoud Pedram, eds. Low Power Design Methodologies. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4615-2307-9.

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Rabaey, Jan. Low Power Design Essentials. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-71713-5.

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Book chapters on the topic "Low-power design and verification"

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Mehta, Ashok B. "Low-Power Verification." In ASIC/SoC Functional Design Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59418-7_9.

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Khondkar, Progyna. "UPF Based Power Aware Static Verification." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_7.

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Khondkar, Progyna. "Background." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_2.

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Khondkar, Progyna. "Introduction." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_1.

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Khondkar, Progyna. "Modeling UPF." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_3.

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Khondkar, Progyna. "Power Aware Standardization of Library." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_4.

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Khondkar, Progyna. "UPF Based Power Aware Dynamic Simulation." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_5.

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Khondkar, Progyna. "Power Aware Dynamic Simulation Coverage." In Low-Power Design and Power-Aware Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66619-8_6.

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Ahuja, Sumit, Avinash Lakshminarayana, and Sandeep Kumar Shukla. "Applying Verification Collaterals for Accurate Power Estimation." In Low Power Design with High-Level Power Estimation and Power-Aware Synthesis. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0872-7_9.

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Hedrich, Lars, and Walter Hartong. "Approaches to Formal Verification of Analog Circuits." In Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits. Springer US, 2001. http://dx.doi.org/10.1007/0-306-48089-1_8.

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Conference papers on the topic "Low-power design and verification"

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Kalil, Nadeem, and Sathyam Pattanam. "A low power design and verification API." In 2010 International Conference on Energy Aware Computing (ICEAC). IEEE, 2010. http://dx.doi.org/10.1109/iceac.2010.5702282.

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Shi-Hao Chen and Jiing-Yuan Lin. "Experiences of low power design implementation and verification." In 2008 Asia and South Pacific Design Automation Conference (ASPDAC). IEEE, 2008. http://dx.doi.org/10.1109/aspdac.2008.4484050.

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Nizam, M., F. N. Najm, and A. Devqan. "Power grid voltage integrity verification." In ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design. IEEE, 2005. http://dx.doi.org/10.1109/lpe.2005.195521.

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Pangrle, B., J. Biggs, C. Clavel, O. Domerego, and K. Just. "Beyond UPF & CPF: Low-power design and verification." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763051.

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Kapoor, B., and K. Just. "Embedded tutorial: Addressing critical power management verification issues in low power designs." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763029.

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Macko, Dominik, Katarina Jelemenska, and Pavel Cicak. "Early-stage verification of power-management specification in low-power systems design." In 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2016. http://dx.doi.org/10.1109/ddecs.2016.7482449.

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An-Yeu Wu, K. J. Ray Liu, Zhongying Zhang, Kazuo Nakajima, Arun Raghupathy, and Shang-Chieh Liu. "Algorithm-based low-power DSP system design: methodology and verification." In VLSI Signal Processing, VIII. IEEE, 1995. http://dx.doi.org/10.1109/vlsisp.1995.527499.

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Lescot, Jérôme, Vincent Bligny, Dina Medhat, et al. "Static low power verification at transistor level for SoC design." In the 2012 ACM/IEEE international symposium. ACM Press, 2012. http://dx.doi.org/10.1145/2333660.2333694.

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Sreevidya, S., Ravishankar Holla, and Roopaka Raghu. "Low Power Physical Design and Verification in 16nm FinFET Technology." In 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2019. http://dx.doi.org/10.1109/iceca.2019.8822211.

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Kalyanam, Vijay Kiran, Martin Saint-Laurent, and Jacob A. Abraham. "Power-aware multi-voltage custom memory models for enhancing RTL and low power verification." In 2015 33rd IEEE International Conference on Computer Design (ICCD). IEEE, 2015. http://dx.doi.org/10.1109/iccd.2015.7357080.

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Reports on the topic "Low-power design and verification"

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Wang, Guanyi, Cezary Bojanowski, Akshay Dave, David Jaluvka, Erik Wilson, and Lin-wen Hu. MITR Low-Enriched Uranium Conversion Fluid-Structure Interaction Preliminary Design Verification. Office of Scientific and Technical Information (OSTI), 2021. http://dx.doi.org/10.2172/1809226.

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Stepinski, Dominique, Amanda Youker, and George Vandegrift. VERIFICATION OF COLUMN DESIGN FOR RECOVERY OF Mo FROM LOW-ENRICHED URANIUM TARGET USING IRRADIATED TARGET TRACER SOLUTION. Office of Scientific and Technical Information (OSTI), 2014. http://dx.doi.org/10.2172/1157511.

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Beech, Russell, and Robert Sinclair. Low Power 256K MRAM Design. Defense Technical Information Center, 2006. http://dx.doi.org/10.21236/ada449576.

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Johnson, G., W. Determan, and W. Otting. NASA low power DIPS [Dynamic Isotope Power System] conceptual design requirements document. Office of Scientific and Technical Information (OSTI), 1990. http://dx.doi.org/10.2172/721000.

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Maumder, Pinaki. Ultra - Low - Power Asynchronous Processor and FPGA Design using Straintronics Nanomagnets. Defense Technical Information Center, 2013. http://dx.doi.org/10.21236/ada584514.

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SCHROEPPEL, RICHARD C., CHERYL L. BEAVER, TIMOTHY J. DRAELOS, RITA A. GONZALES, and RUSSELL D. MILLER. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip. Office of Scientific and Technical Information (OSTI), 2002. http://dx.doi.org/10.2172/802030.

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Jeon, Kanghoon. Band-to-Band Tunnel Transistor Design and Modeling for Low Power Applications. Defense Technical Information Center, 2012. http://dx.doi.org/10.21236/ada561676.

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Kim, E., and D. Kaspar. Design and Application Spaces for IPv6 over Low-Power Wireless Personal Area Networks (6LoWPANs). RFC Editor, 2012. http://dx.doi.org/10.17487/rfc6568.

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Stettenheim, Joel, Troy McBride, Oliver Brambles, and Leif Johnson. Design and Field Testing of Manufacturable Advanced Low-Cost Receiver for Parabolic Trough Solar Power. Office of Scientific and Technical Information (OSTI), 2019. http://dx.doi.org/10.2172/1508360.

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Kintner-Meyer, Michael CW, Brion J. Burghard, and Larry D. Reid. Final Report Providing the Design for Low-Cost Wireless Current Transducer and Electric Power Sensor Prototype. Office of Scientific and Technical Information (OSTI), 2005. http://dx.doi.org/10.2172/15020679.

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