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Andersson, Johan, and Adam Schelander. "Design and verification of automotive power supply." Thesis, Linköpings universitet, Fysik och elektroteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-150147.
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In the current and next generation automotive telematic platforms, high demands are put on high efficiency power supplies. This thesis investigates different switch mode power converter solutions that operates with high efficiency for both low and high power loads. A market survey was conducted alongside meetings with ACTIA Nordic and their subcontractors. Three solutions from the market survey were selected for further investigation. One solution from the investigation was selected and implemented as a demonstration platform for further testing. The result shows a full test sequence for the designed power supply solution.
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Sun, Jin. "Conquering Variability for Robust and Low Power Designs." Diss., The University of Arizona, 2011. http://hdl.handle.net/10150/145458.
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As device feature sizes shrink to nano-scale, continuous technology scaling has led to a large increase in parameter variability during semiconductor manufacturing process. According to the source of uncertainty, parameter variations can be classified into three categories: process variations, environmental variations, and temporal variations. All these variation sources exert significant influences on circuit performance, and make it more challenging to characterize parameter variability and achieve robust, low-power designs. The scope of this dissertation is conquering parameter variability and successfully designing efficient yet robust integrated circuit (IC) systems. Previous experiences have indicated that we need to tackle this issue at every design stage of IC chips. In this dissertation, we propose several robust techniques for accurate variability characterization and efficient performance prediction under parameter variations. At pre-silicon verification stage, a robust yield prediction scheme under limited descriptions of parameter uncertainties, a robust circuit performance prediction methodology based on importance of uncertainties, and a robust gate sizing framework by ElasticR estimation model, have been developed. These techniques provide possible solutions to achieve both prediction accuracy and computation efficiency in early design stage. At on-line validation stage, a dynamic workload balancing framework and an on-line self-tuning design methodology have been proposed for application-specific multi-core systems under variability-induced aging effects. These on-line validation techniques are beneficial to alleviate device performance degradation due to parameter variations and extend device lifetime.
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Hornæs, Daniel. "Low-Cost FPU : Specification, Implementation and Verification." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-11145.
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This report aims to provide a complete specification of an IEEE-754 1985 compliantdesign, as well as a working, synthesizable implementation in Verilog HDL. Thereport is based on a preliminary project, which analyzed the IEEE-754 standardand suggested a set of algorithms suitable for a compact realization.Through traditional methods of both algorithmic analysis and dataanalysis,requirements of functional units are derived, and operations are scheduled.A set of functional simulations assert the correctness of the design, while areaand performance analysis provides information on the speedup gained, versus thehardware cost.Finally, the results obtained are compared to existing implementations, bothhardware and software.
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Hu, Xin. "RF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency and Controllable Bandwidth: Design Sythesis and Verification." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright149572725296626.
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Piiroinen, M. (Mika). "Design and verification of bonded GaN power amplifier for the 5G." Master's thesis, University of Oulu, 2017. http://urn.fi/URN:NBN:fi:oulu-201710132996.
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In this thesis a bonded Gallium nitride (GaN) power amplifier (PA) is designed using 3D modeling tool to design layout for the gate and drain matching elements for the GaN PA including bondwires. 1D circuit simulator is used to simulate the PA operation with 3D simulated matching blocks and large signal GaN device model. GaN device used in this design is Qorvo’s TGF2023-2-02. 3D simulated drain and gate matching layouts are based on the TGF2023-2-02 datasheet’s loadpull data and the large signal simulations. The target operational frequency for the power amplifier is from 5.6 GHz to 6.0 GHz. The main design goal is to achieve 60% drain efficiency, 36 dBm maximum output power and over 12 dB gain in the operational band. With simulations, 59.2% drain efficiency, 41.5 dBm output power and 15.8 dB gain is achieved using 28 V drain voltage. According to the measurements, the highest drain efficiency is 59.2% using lower 18 V drain voltage. With measurements, 37.04 dBm drain efficiency and 14.2 dB gain were achieved using the lower drain voltage. This means that the fabricated power amplifier achieves the designed output power and gain targets while the drain efficiency is only 0.8 pp lower than the target<br>Tässä diplomityössä suunnitellaan bondattu galliumnitridi (GaN) RF-tehovahvistin käyttäen 3D mallinnustyökalua GaN tehovahvistimen hilan ja nielun impedanssi sovituksien suunnitteluun ja mallintamiseen. Mallinnus sisältää myös bondauslangat. 1D piirisimulaattorilla simuloitiin tehovahvistimen toimintaa käyttäen 3D simuloituja sovituksia ja GaN vahvistimen suursignaalimallia. Tässä työssä käytetty GaN tehovahvistin on Qorvon valmistama TGF2023-2-02. Simuloidut nielun ja hilan sovituselementit perustuvat suursignaali simulointeihin sekä TGF2023-2-02:n datalehden loadpull-dataan. Tehovahvistin suunnitellaan 5,6–6,0 GHz taajuusalueelle. Tavoitteena on saavuttaa 60% nieluhyötysuhde, 36 dBm lähtöteho ja yli 12 dB vahvistus. Simuloinneissa saavutetaan 59,2 % nieluhyötysuhde, 41,5 dBm lähtöteho ja 15,8 dB vahvistus käyttäen 28 V nielujännitettä. Mittauksissa suurin nieluhyötysuhde, 59,2% saavutetaan alemmalla, 18 V nielujännitteellä. Alemmalla nielujännitteellä suurin lähtöteho on 37,04 dBm ja vahvistus 14,2 dB. Tämä tarkoittaa sitä, että lähtöteho ja vahvistus tavoitteisiin päästään. Nielun hyötysuhde on vain 0,8 prosenttiyksikköä alle tavoitteen
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Li, Qiong. "Developing Modeling and Simulation Methodology for Virtual Prototype Power Supply System." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/27462.
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This dissertation develops a modeling and simulation methodology for design, verification, and testing (DVT) power supply system using a virtual prototype. The virtual prototype is implemented before the hardware prototyping to detect most of the design errors and circuit deficiencies that occur in the later stage of a standard hardware design verification and testing procedure. The design iterations and product cost are reduced significantly by using this approach.
The proposed modeling and simulation methodology consists of four major parts: system partitioning, multi-level modeling of device/function block, hierarchical test sequence, and multi-level simulation. By applying the proposed methodology, the designer can use the virtual prototype effectively by keeping a short simulation CPU time as well as catching most of the design problems.
The proposed virtual prototype DVT procedure is demonstrated by simulating a 5 V power supply system with a main power supply, a bias power supply, and other protection, monitoring circuitry. The total CPU time is about 8 hours for 780 tests that include the basic function test, steady stage analysis, small-signal stability analysis, large-signal transient analysis, subsystem interaction test, and system interaction test. By comparing the simulation results with the measurements, it shows that the virtual prototype can represent the important behavior of the power supply system accurately. Since the proposed virtual prototype DVT procedure verifies the circuit design with different types of the tests over different line and load conditions, many circuit problems that are not obvious in the original circuit design can be detected by the simulation.
The developed virtual prototype DVT procedure is not only capable of detecting most of the design errors, but also plays an important role in design modifications. This dissertation also demonstrates how to analyze the anomalies of the forward converter with active-clamp reset circuit extensively and facilitate the design and improve the circuit performances by utilizing the virtual prototype. With the help of the virtual prototype, it is the first time that the designer is able to analyze the dynamic behavior of the active-clamp forward converter during large-signal transient and optimize the design correspondingly.<br>Ph. D.
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HOLMÉR, NIKLAS. "Design and Verification of MIL for Linear Actuator." Thesis, KTH, Skolan för industriell teknik och management (ITM), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-278895.
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In a world where development of new technology moves rapidly towards renewable energy resources, it is important to implement new technology for efficiency improvement on existing products. This is Cascade Drives ambition, to enable a shift from hydraulic usage in heavy vehicles to a solution that is completely electromechanical driven, to improve energy efficiency. Currently, Cascade Drives are developing electromechanical linear actuators to replace hydraulic driven actuators in heavy vehicles such as forklifts, both for lifting and steering applications. These actuators are designed with a rack and pinion setup where multiple pinions are placed on a single rack and by using a patented flexible solution, an otherwise overdetermined system can share the load evenly over the pinions. This significantly reduce the size of each pinion and the overall package. This master thesis aims at investigating the power losses in this electromechanical actuator and implement a model in the loop (MIL) to predict the efficiency and how this alters for different speeds and loads applied on the actuator. A model to predict the efficiency was implemented in Simulink software and two different verification tests on physical prototypes were conducted. The results showed that the predicted load dependent losses corresponded well to the measured values. The speed dependent losses proved harder to predict.<br>I en värld där utveckling av ny teknik rör sig snabbt mot förnybara energikällor är det viktigt att implementera ny teknik för effektivisering av befintliga produkter. Detta är Cascade Drives ambition, att möjliggöra en övergång från användandet av hydraulik i tunga applikationer till en lösning som är elektromekaniskt driven, för att förbättra energieffektiviteten. För närvarande utvecklar Cascade Drives elektromekaniska ställdon för att ersätta hydrauliskt drivna ställdon i tunga fordon så som gaffeltruckar, både för lyft- och styrapplikationer. Dessa ställdon är utformade med en rack- och kugghjulsuppsättning där flera kugghjul är i ingrepp med ett enda rack och genom att använda en patenterad flexibel lösning kan ett annars överbestämt system dela belastningen över alla kugghjul. Detta leder till att storleken på varje hjul kan minskas och även den totala storleken på produkten blir mindre. Detta examensarbete syftar till att undersöka effektförlusterna i detta elektromekaniska ställdon och implementera en så kallad ”Model In the Loop” (MIL) för att förutsäga verkningsgraden och hur denna förändras för olika hastigheter och krafter som appliceras på ställdonet. En modell för att prediktera verkningsgraden implementerades i Simulink programvara och två olika verifieringstester på fysiska prototyper genomfördes. Resultaten visade att prediktionen för de lastberoende förlusterna motsvarade de uppmätta värdena. De hastighetsberoende förlusterna visade sig svårare att förutsäga.
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Ralston, Parrish Elaine. "Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/36169.
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There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0â 40V) and high voltage (40â 5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed.<br>Master of Science
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Lipscomb, Melissa Anne. "A versatile simulation tool for the design and verification of military vehicle power systems." Thesis, Texas A&M University, 2005. http://hdl.handle.net/1969.1/2577.
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The design of the electric platform in military vehicles requires the ability to determine the best combination of power system components that support the desired operational abilities, while minimizing the size, weight, cost, and impact of the overall power system. Because prototypes are both time consuming, rigid, and costly, they have become inadequate for verifying system performance. By using simulations, engineers can best plan for and observe the associations between missions (including modes of operation and system scenarios) and system performance in a dynamic, realistic environment. This thesis proposes a new tool to analyze and design military vehicle platforms: the Advanced Mobile Integrated Power System (AMPS). This tool is useful for design and design verification of military vehicles due to its unique incorporation of mission-specific functionality. It allows the user ease of design with the ability to customize the vehicle power system architecture and components, while permitting full control over source and load input parameters. Simulation of programmed mission sequences allows the user to ensure that the chosen vehicle architecture can provide all of the electrical power and energy needed to support the mission, thus providing adequate design verification. The present thesis includes an introduction to vehicle power systems and an outline of the need for simulation, a description of the AMPS project and vehicle specifications, analytical and numerical models of the simulated vehicle, explanation of the power management system, description of the graphical user interface, and a simulation performed with the AMPS tool.
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Moynahan, Nathan A. "Development of a vehicle road load model for ECU broadcast power verification in on-road emissions testing." Morgantown, W. Va. : [West Virginia University Libraries], 2005. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=4454.
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Thesis (M.S.)--West Virginia University, 2005.<br>Title from document title page. Document formatted into pages; contains xi, 117 p. : ill. (some col.), col. map. Includes abstract. Includes bibliographical references (p. 75-77).
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Botes, Jan Adriaan. "Development, characterisation and verification of an integrated design tool for a power source of a soya business unit / J.A. Botes." Thesis, North-West University, 2007. http://hdl.handle.net/10394/1943.
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Bodnar, Maxwell J. "The Creation, Analysis, and Verification of a Comprehensive Model of a Micro Ion Thruster." DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1565.
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A computational model of the micro-ion thruster MiXI has been developed, analyzed, and partially verified. This model includes submodels that govern the physical, magnetic, electrostatic, plasma physics, and power deposition of the thruster. Over the past few years, theses have been conducted with the goal of running tests and analyzing the results; this model is used to understand how the thruster components interact so as to make predictions about, and allow for optimization of, the thruster operation. Testing is then performed on the thruster and the results are compared to the output of the code. The magnetic structure of the thruster was analyzed and numerous different configurations generated which were also evaluated by the optimizer and tested. Using the different configurations, models, and optimization tools, the total efficiency of the thruster is theoretically able to reach 69.4%. Operational testing of the thruster at many different throttle settings demonstrated a maximum total efficiency of 45.9 ±24.6%, discharge loss values as low as 109 ±25 eV/ion, and total power required as low as 50.5 ±0.1W to maintain thruster operation with beam extraction. Measurements of the plasma were taken using a Langmuir probe and the interpretation of the tests are used to verify the plasma physics submodel. Power draw measurements and analysis of the throttle inputs during testing are compared to the performance model outputs but were not accurate or consistent enough to fully verify the power deposition and plasma physics models. Analysis of the models and operational testing in this study have led to an increased understanding of the performance and operation of the MiXI-CP-V3 thruster, furthering the effort to create an efficient, flight capable micro-ion thruster.
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Berry, David W. "Design, Analysis and Experimental Verification of a Mechanically Compliant Interface for Fabricating Reliable, Double-Side Cooled, High Temperature, Sintered Silver Interconnected Power Modules." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/64898.
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This research developed a double-side power electronics packaging scheme for high temperature applications exemplified by 1200 V, 150 A silicon devices. The power modules, based on both quarter and half-bridge topologies, were assembled using sintered silver device attachment rather than conventional solder alloys. Thermomechanical stresses in the double-side architecture were mitigated with a compliant layer fabricated from elliptical silver tubes.
This research presents an introduction to conventional packaging techniques and their weaknesses. These shortcomings provide the basis for a module design which improves upon module thermal management while also addressing electrical and reliability requirements. The optimum package design enhances heat dissipation with the addition of a substrate bonded to the top electrical pads of the semiconductor devices. The use of sintered silver also increases the useful application temperature by avoiding the creep failure mechanisms of solder alloys.
The modules were characterized extensively to quantify thermal and electrical performance. In the case of thermal characterization, the double-side architecture required multiple testing configurations to fully understand the parallel heat flow paths. These results were compared to models constructed using finite element analysis (FEA). The FEA models were also utilized for measurement of strains in multiple package designs to better determine the effects of increased compliance on the relative package cycling lifetime. These lifetimes were then assessed, in part, using experimental passive and cycling tests on functional double-side packages.
The resulting power modules exhibited significant decreases in thermal resistance when they are cooled, as designed, from both sides of the module. Even single sided cooling options reveal significant advantages and transient thermal impedance was found to be significantly lower. Power module models revealed the compliant layer was successful in reducing the device shear stresses which was experimentally validated through the use of DC power stage testing. It was found, through double pulse testing and electrical modeling, that parasitic inductances were reduced by utilizing planar bonding and planar symmetrical traces. Finally, modeling of the double-side package with added tube compliance revealed a decrease in plastic and shear strains when compared to other single and double-side package designs. This reduction directly translates to increased cycling lifetime using well known strain based fatigue models.<br>Ph. D.
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Xia, Bo. "Analog-to-digital interface design in wireless receivers." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3260.
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As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues.
A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode.
In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.
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Mbarek, Ons. "Une approche de modélisation au niveau système pour la conception et la vérification de systèmes sur puce à faible consommation." Phd thesis, Université Nice Sophia Antipolis, 2013. http://tel.archives-ouvertes.fr/tel-00837662.
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Une solution de gestion de puissance d'un système sur puce peut être définie par une architecture de faible puissance composée de multiples domaines d'alimentation et de leur stratégie de gestion. Si ces deux éléments sont économes en énergie, une solution efficace en énergie peut être obtenue. Cette approche nécessite l'ajout d'éléments structurels de puissance et de leurs comportements. Une stratégie de gestion doit respecter les dépendances structurelles et fonctionnelles dues au placement physique des domaines d'alimentation. Cette relation forte entre l'architecture et sa stratégie de gestion doit être analysée tôt dans le flot de conception pour trouver la solution de gestion de puissance la plus efficace. De récentes normes de conception basse consommation définissent des sémantiques pour la spécification, simulation et vérification d'architecture de faible puissance au niveau transfert de registres (RTL). Mais elles manquent une sémantique d'interface de gestion des domaines d'alimentation réutilisable ce qui alourdit l'exploration. Leurs sémantiques RTL ne sont pas aussi utilisables au niveau transactionnel pour une exploration plus rapide et facile. Pour combler ces lacunes, cette thèse étend ces normes et fournit une étude complète des possibilités d'optimisation de puissance basées sur la composition et la gestion des domaines d'alimentation pour des modèles fonctionnels transactionnels utilisant un environnement commun USLPAF. USLPAF comprend une méthodologie alliant conception et vérification des modèles transactionnels de faible consommation, ainsi qu'une bibliothèque de techniques de modélisation et fonctions prédéfinies pour appliquer cette méthodologie.
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Zhou, Yu Computer Science & Engineering Faculty of Engineering UNSW. "Low power processor design." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/42608.
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Power consumption is a critical design issue in embedded processors. As part of our low power processor design project, this thesis work aims to reduce power consumption on two typical processor components: Register File (RF), and Arithmetic and Logic Unit (ALU). Register File is one of the most power hungry components in the processor, consuming about 20% of the processor power. The ALU is the working horse in the processor, responsible for almost all basic computing operations. Although ALU does not consume as high power as the register file, we observe that it can be power intensive in terms of power dissipation per silicon area unit and may result in a thermal hot spot in the processor. Existing approaches to reduce power on the register file and ALU are effective. However, most of them either entail extensive hardware design efforts, or require a significant amount of work on post-compilation software code modification. The approaches proposed in this thesis avoid such problems. We only customize the internal structure of the processor components and keep the components interface to other system parts intact, so that the customization to a component is transparent to its external hardware design and no modification/alteration to other hardware components or to the software code is required. This customization strategy is well suitable to our whole low power processor design project and can be applied to any customization of an existing system for a given application. We have applied our customization approaches to a set of benchmarks in a variety of application domains. Our experimental results show that the power savings on register file are in a range from 18.8% to 45.5%, an average of 29.7% register file power can be saved. For the arithmetic and logic unit, the power savings are from 43.5% to 49.6% and the average saving is 46.9% as compared to the original designs. We also combine the customization of both the ALU and the register file. With the customizing of the ALU and the register file simultaneously, the processor power consumption can be reduced from 3.9% to 10.1%; on average, 6.44% processor power can be saved. Most importantly, the power saving achievement is at the cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward and can be easily incorporated into a processor design environment, such as ASIPMeister (a design tool, to automatically generate a VHDL model for application specificinstruction set processors) used in our research.
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Classon, Viktor. "Low Power Design Using RNS." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110176.
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Power dissipation has become one of the major limiting factors in the design of digital ASICs. Low power dissipation will increase the mobility of the ASIC by reducing the system cost, size and weight. DSP blocks are a major source of power dissipation in modern ASICs. The residue number system (RNS) has, for a long time, been proposed as an alternative to the regular two's complement number system (TCS) in DSP applications to reduce the power dissipation. The basic concept of RNS is to first encode the input data into several smaller independent residues. The computational operations are then performed in parallel and the results are eventually decoded back to the original number system. Due to the inherent parallelism of the residue arithmetics, hardware implementation results in multiple smaller design units. Therefore an RNS design requires low leakage power cells and will result in a lower switching activity. The residue number system has been analyzed by first investigating different implementations of RNS adders and multipliers (which are the basic arithmetic functions in a DSP system) and then deriving an optimal combination of these. The optimum combinations have been used to implement an FIR filter in RNS that has been compared with a TCS FIR filter. By providing different input data and coefficients to both the RNS and TCS FIR filter an evaluation of their respective performance in terms of area, power and operating frequency have been performed. The result is promising for uniform distributed random input data with approximately 15 % reduction of average power with RNS compared to TCS. For a realistic DSP application with normally distributed input data, the power reduction is negligible for practical purposes.
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Zhu, Haikun. "High-performance low-power VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3250072.
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Thesis (Ph. D.)--University of California, San Diego, 2007.<br>Title from first page of PDF file (viewed April 4, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 97-101).
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Svensson, Linus. "Low-power embedded internet system design /." Luleå, 2004. http://epubl.ltu.se/1402-1757/2004/76/.
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Yu, Yue. "Low-power low-phase-noise voltage-controlled oscillator design." The Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=osu1413475974.
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Kim, Dongho. "Power estimation for combinational logic and low power design /." Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008367.
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Ahmed, Naveed. "Design options for low cost, low power microsatellite based SAR." Thesis, University of Surrey, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.580317.
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This research aims at providing a system design that reduces the mass and cost of spaceborne Synthetic Aperture Radar (SAR) missions by a factor of two compared to current (TecSAR - 300 kg, - £ 127 M) or planned (NovaSAR-S - - 400 kg, - £ 50 M) mission. This would enable the cost of a SAR constellation to approach that of the current optical constellation such as Disaster Monitoring Constellation (DMC). This research has identified that the mission cost can be reduced significantly by: focusing on a narrow range of applications (forestry and disasters monitoring); ensuring the final design has a compact stowage volume, which facilitates a shared launch; and building the payload around available platforms, rather than the platform around the payload. The central idea of the research has been to operate the SAR at a low instantaneous power level-a practical proposition for a micro-satellite based SAR. The use of a simple parabolic reflector with a single horn at L-band means that a single, reliable and efficient Solid State Power Amplifier (SSPA) can be used to lower the overall system cost, and to minimise the impact on the spacecraft power system. A detailed analysis of basic pulsed (- 5 - 10 % duty cycle) and Continuous Wave (CW) SAR (100 % duty cycle) payloads has shown their inability to fit directly into existing microsatellite buses without involving major changes, or employing more than one platform. To circumvent the problems of pulsed and CW techniques, two approaches have been formulated. The first shows that a CW SAR can be implemented in a mono-static way with a single antenna on a single platform. In this technique, the SAR works in an Interrupted CW (ICW) mode, but these interruptions introduce periodic gaps in the raw data. On processing, these gapped data result in artefacts in the reconstructed images. By applying data based statistical estimation techniques to "fill in the gaps" in the simulated raw SAR data, this research has shown the possibility of minimising the effects of these artefacts. However, once the same techniques are applied to the real SAR data (in this case derived from RADARSAT-l), the artefacts are shown to be problematic. Because of this the ICW SAR design technique it is-set aside. The second shows that an extended chirp mode pulsed (ECMP) SAR (- 20 - 54 % duty cycle) can be designed with a lowered peak power level which enables a single SSPA to feed a parabolic Cas se grain antenna. The detailed analysis shows the feasibility of developing a micro satellite based SAR design at a comparable price to those of optical missions.
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Sharifkhani, Mohammad. "Design and Analysis of Low-power SRAMs." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2870.
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The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. Owing to high bitline voltage swing during write operation, the write power consumption is dominated the dynamic power consumption. The static power consumption is mainly due to the leakage current associated with the SRAM cells distributed in the array. Moreover, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent years. <br /><br /> To reduce the write power consumption, several schemes such as row based sense amplifying cell (SAC) and hierarchical bitline sense amplification (HBLSA) have been proposed. However, these schemes impose architectural limitations on the design in terms of the number of words on a row. Beside, the effectiveness of these methods is limited to the dynamic power consumption. Conventionally, reduction of the cell supply voltage and exploiting the body effect has been suggested to reduce the cell leakage current. However, variation of the supply voltage of the cell associates with a higher dynamic power consumption and reduced cell data stability. Conventionally qualified by Static Noise Margin (SNM), the ability of the cell to retain the data is reduced under a lower supply voltage conditions. <br /><br /> In this thesis, we revisit the concept of data stability from the dynamic perspective. A new criteria for the data stability of the SRAM cell is defined. The new criteria suggests that the access time and non-access time (recovery time) of the cell can influence the data stability in a SRAM cell. The speed vs. stability trade-off opens new opportunities for aggressive power reduction for low-power applications. Experimental results of a test chip implemented in a 130 <em>nm</em> CMOS technology confirmed the concept and opened a ground for introduction of a new operational mode for the SRAM cells. <br /><br /> We introduced a new architecture; Segmented Virtual Grounding (SVGND) to reduce the dynamic and static power reduction in SRAM units at the same time. Thanks to the new concept for the data stability in SRAM cells, we introduced the new operational mode of Accessed Retention Mode (AR-Mode) to the SRAM cell. In this mode, the accessed SRAM cell can retain the data, however, it does not discharge the bitline. The new architecture outperforms the recently reported low-power schemes in terms of dynamic power consumption, thanks to the exclusive discharge of the bitline and the cell virtual ground. In addition, the architecture reduces the leakage current significantly since it uses the back body biasing in both load and drive transistors. <br /><br /> A 40Kb SRAM unit based on SVGND architecture is implemented in a 130 <em>nm</em> CMOS technology. Experimental results exhibit a remarkable static and dynamic power reduction compared to the conventional and previously reported low-power schemes as expect from the simulation results.
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Wang, Yan. "Low power design for wireless communication system /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WANG.
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Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2003.<br>Includes bibliographical references (leaves 171-179). Also available in electronic version. Access restricted to campus users.
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Gopalan, Sriram. "A method of low power SRAM design /." Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1546779941&sid=19&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Heo, Seongmoo 1977. "A low-power 32 bit datapath design." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86624.
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Scartezzini, Gerson. "Low-power design using networks of transistors." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/127453.
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Em circuitos integrados complexos, potência e desempenho têm caminhado em direções opostas tornando o desenvolvimento de dispositivos de baixo consumo uma tarefa altamente custosa. Tradicionalmente, empresas de desenvolvimento de circuitos integrados utilizam variadas técnicas para garantir os requisitos de potência, no entanto, técnicas baseadas em biblioteca de células tem se tornado um gargalo para o processo de desenvolvimento. À medida que os projetos aumentam de complexidade e densidade, maior tende a ser a potência dissipada por estes dispositivos, e assim, mais importante torna-se sua redução. Buscando aumentar a capacidade de redução de potência, projetistas tem aplicado diferentes técnicas para cada nível de abstração do fluxo de projeto. No nível físico, de maneira a contornar os limites das bibliotecas de células, o desenvolvimento de células especificamente projetadas tem se tornado uma rotina em projetos com grandes restrições de potência. Observando este requisito, este trabalho visa pesquisar a implementação e otimização de células digitais CMOS (Complementary Metal-Oxide-Semiconductor) estática em nível de transistores, e o emprego de metodologia de projeto livre de biblioteca como um recurso para a concepção de sistemas de baixa potência. De um modo geral, menos transistores são desejáveis para reduzir a dissipação de potência, no entanto, longas cadeias de transistores, necessários para implementar funções lógicas específicas, conduz ao aumento do tempo de transição, e, portanto, maior dissipação de energia. A fim de evitar este efeito, construímos uma função de mapeamento, com base no tamanho dos transistores, de forma a evitar um tempo de transição lento e minimizar o número de transistores. O uso deste método demonstrou ser eficaz para o ajuste fino de circuitos de baixa potência, resultando em uma redução média de 6.35% no consumo dinâmico e de 8.26% no consumo estático em comparação com a metodologia baseada em biblioteca de células. Como trabalho adicional, é apresentado um fluxo automatizado de mapeamento lógico e capaz de gerar redes de transistores específicas para cada projeto, tornando possível sua utilização em ferramentas de desenvolvimento tradicionais.<br>In complex integrated circuits, power and performance have moved in opposite directions making the design of low-power devices a highly costly task. Traditionally, integrated circuit design companies adopt many techniques to ensure power requirements, however, techniques based on cell library has become a bottleneck for the development process. As the design complexity and density increase, greater will be the power dissipated, and thus its reduction becomes more important. Seeking to increase the power reduction capability, designers have applied different techniques for each level of the design flow abstraction. At the physical level, so as to bypass the limits of cell libraries, the development of specifically designed cells has become a routine for designs with large power constraints. Observing this requirement, this work aims to investigate the implementation and optimization of digital static CMOS (Complementary Metal-Oxide-Semiconductor) cell at transistors level, and the use of library free design methodology as a resource for designing low power systems. In general, fewer transistors are desirable to reduce power dissipation, however, long chains of transistors, necessary for implementing specific logical functions, leads to the increase of the transition time, and hence greater energy dissipation. In order to avoid this effect, we constructed a mapping function, based on transistor size, in order to avoid slow transition time and minimize the number of transistors. The use of this method has proven effective for fine adjustment low power circuits, resulting in an average reduction of 6.35% in dynamic power and 8.26% in static power as compared with the cell library based methodology. As further work, an automated flow set is presented for the logical mapping able to generate specific networks of transistors for each design, making possible their use in traditional design tools.
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Willingham, David John. "Asynchrobatic logic for low-power VLSI design." Thesis, University of Westminster, 2010. https://westminsterresearch.westminster.ac.uk/item/9087w/asynchrobatic-logic-for-low-power-vlsi-design.
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In this work, Asynchrobatic Logic is presented. It is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways. The term “Asynchrobatic” is a new word that can be used to describe these types of systems, and is derived from the concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis introduces the concept and theory behind Asynchrobatic Logic. It first provides an introductory background to both underlying parent technologies (asynchronous logic and adiabatic logic). The background material continues with an explanation of a number of possible methods for designing complex data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then introduced as a comparison between asynchronous and Asynchrobatic buffer chains, showing that for wide systems, it operates more efficiently. Two more-complex sub-systems are presented, firstly a layout implementation of the substitution boxes from the Twofish encryption algorithm, and secondly a front-end only (without parasitic capacitances, resistances) simulation that demonstrates a functional system capable of calculating the Greatest Common Denominator (GCD) of a pair of 16-bit unsigned integers, which under typical conditions on a 0.35μm process, executed a test vector requiring twenty-four iterations in 2.067μs with a power consumption of 3.257nW. These examples show that the concept of Asynchrobatic Logic has the potential to be used in real-world applications, and is not just theory without application. At the time of its first publication in 2004, Asynchrobatic Logic was both unique and ground-breaking, as this was the first time that consideration had been given to operating large-scale adiabatic logic in an asynchronous fashion, and the first time that Asynchronous Stepwise Charging (ASWC) had been used to drive an adiabatic data-path.
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pang, chang chien, and 江建邦. "Design and Verification of Low Voltage Low Power 8-bits Micro Controller." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/13364054964663055143.
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碩士<br>國立中正大學<br>電機工程研究所<br>89<br>Abstract
In this thesis, a low power and low voltage 8-bits Micro-controller compatible with Intel8051 is proposed. The Architecture of 8-bits Micro-controller inherits the last version. Because some instructions cannot work normally, we change some design of control unit. Besides, we add UART to compensate the application in communication of CCU51.
In lowering the power consumption, using different operating mode and lowering the operating voltage are both the method of lowering the power consumption. we add a sleep mode for CCU51. We can choose to enter sleep mode when we do not use for a long time.
Besides, we design a cell library suitable for working at low voltage and its feature is as follow：
1.Using two power line(0.9v/0.5v)
2.Using MTCMOS process
3.In combinational circuit, we use SCCMOS technique to control the leakage current
4.In sequential circuit ：
·Flip Flop ：use modified SAFF
·Latch：use Latch with level converter
We have finished the design and experiment in TSMC 0.25μ technique process. The post-layout simulation show it can work at 15-M frequency and the power consumption is only 1.473m Watt at 0.9v/0.5v.
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Viswanath, Vinod. "Correct low power design transformations for hardware systems." 2013. http://hdl.handle.net/2152/21409.
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We present a generic proof methodology to automatically prove correctness of design transformations introduced at the Register-Transfer Level (RTL) to achieve lower power dissipation in hardware systems. We also introduce a new algorithm to reduce switching activity power dissipation in microprocessors. We further apply our technique in a completely different domain of dynamic power management of Systems-on-Chip (SoCs). We demonstrate our methodology on real-life circuits. In this thesis, we address the dual problem of transforming hardware systems at higher levels of abstraction to achieve lower power dissipation, and a reliable way to verify the correctness of the afore-mentioned transformations. The thesis is in three parts. The first part introduces Instruction-driven Slicing, a new algorithm to automatically introduce RTL/System level annotations in microprocessors to achieve lower switching power dissipation. The second part introduces Dedicated Rewriting, a rewriting based generic proof methodology to automatically prove correctness of such high-level transformations for lowering power dissipation. The third part implements dedicated rewriting in the context of dynamically managing power dissipation of mobile and hand-held devices. We first present instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level in order to achieve lower power dissipation. Our technique automatically annotates existing RTL code to optimize the circuit for lowering power dissipated by switching activity. Our technique can be applied at the architectural level as well, achieving similar power gains. We first demonstrate our technique on architectural and RTL models of a 32-bit OpenRISC pipelined processor (OR1200), showing power gains for the SPEC2000 benchmarks. These annotations achieve reduction in power dissipation by changing the logic of the design. We further extend our technique to an out-of-order superscalar core and demonstrate power gains for the same SPEC2000 benchmarks on architectural and RTL models of PUMA, a fixed point out-of-order PowerPC microprocessor. We next present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level. We guarantee the correctness of any low power transformation by providing a functional equivalence proof of the hardware design before and after the transformation. Dedicated rewriting is a highly automated deductive verification technique specially honed for proving correctness of low power transformations. We provide a notion of equivalence and establish the equivalence proof within our dedicated rewriting system. We demonstrate our technique on a non-trivial case study. We show equivalence of a Verilog RTL implementation of a Viterbi decoder, a component of the DRM System-On-Chip (SoC), before and after the application of multiple low power transformations. We next apply dedicated rewriting to a broader context of holistic power management of SoCs. This in turn creates a self-checking system and will automatically flag conflicting constraints or rules. Our system will manage power constraint rules using dedicated rewriting specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform. Finally, we give a proof of instruction-driven slicing. We first prove that the annotations automatically introduced in the OR1200 processor preserve the original functionality of the machine using the ACL2 theorem prover. Then we establish the same proof within our dedicated rewriting system, and discuss the merits of such a technique and a framework. In the context of today's shrinking hardware and mobile internet devices, lowering power dissipation is a key problem. Verifying the correctness of transformations which achieve that is usually a time-consuming affair. Automatic and reliable methods of verification that are easy to use are extremely important. In this thesis we have presented one such transformation, and a generic framework to prove correctness of that and similar transformations. Our methodology is constructed in a manner that easily and seamlessly fits into the design cycle of creating complicated hardware systems. Our technique is also general enough to be applied in a completely different context of dynamic power management of mobile and hand-held devices.<br>text
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Hsiao, Wei-Ta, and 蕭煒達. "Design and Verification of Novel Wearable Ultra-Low Power Wireless Micro EEG Acquisition System." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/t2qrth.
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碩士<br>國立交通大學<br>生醫工程研究所<br>103<br>The brain-computer interface (BCI) technique is a method that provides a direct communication pathway between the brain and the external worlds. However, the instruments with high measured signal quality are always heavy and huge. Thus, recording EEG trends to be a difficult task in daily life. Although there were some portable EEG systems designed for improving this situation, they aren’t enough for daily life conveniently. Therefore, we mention a wearable wireless micro EEG acquisition system. We expect to improve the availability of BCI technique used in daily life.
This system includes two parts: (1) Wearable ultra-low power wireless micro EEG acquisition system, (2) User-interface for EEG display based on Android 4.3 system. This system can be used with wet sensor, Ag/AgCl electrode or dry sensors. Then the user-interface receives EEG data via wireless communication and also saves raw data as a file for off-line analysis. On the other hand, RS232 and USB on-the-go would be used for sending event’s tag in some cognitive experiments.
Although this system is designed with low-power techniques completely, it also maintains the signal quality. The systems’ synchronization is designed for some EEG applications with multi-channels. In addition, this system can achieve front-end EEG power-spectrum analysis for more BCI practicalities. Finally, we also verify the performance of our low-energy EEG system by means of many verification experiments. The results show that our system has high reliability of EEG processing and recording. It's suitable for some applications such as detection of sleep quality, attention, brain-control interface, etc. Therefore, the system’s pros of micro-sized, low-power consumption and functionalizing would promote applications of BCI technique for consumer electronics market.
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CHEN, SHEN-WEN, and 陳聖文. "The Design and Verification of a Low-Power Data Cache Architecture for 32-bit Embedded Microprocessors." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/pnk57e.
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碩士<br>國立臺灣科技大學<br>電子工程系<br>99<br>Deep submicron technology leads to the huge growth of hardware as the prediction of Moore's Law. The speed gap between processors and DRAM devices is increasingly widened along the progress of integrated circuit manufactures. To bridge such a gap, the design of cache memory in between the processor and main memory has become critical. However, the addition of cache memory also consumes a lot of power, which is a large part of the total power dissipation of an embedded system. Consequently, the design of a low-power cache memory has become an important issue in an embedded system.
In this thesis, a low-power data cache architecture, called partial way-predicting (assist-trigger) architecture, is proposed. This architecture is based on the improvement of conventional cache architecture according to the access behavior of data cache memory. To explore this, two low-power techniques, the way-predicting cache with MRU table and tag skipping technique, are combined. The resulting cache architecture can be operated in two modes: predict and non-predict. By using an assist unit to trigger the cache system into the prediction mode opportunely, this architecture avoids huge prediction miss effectively.
As compared to conventional 4-way way-predicting cache, the proposed partial way-predicting architecture can reduce about the 76% performance penalty at the cost of 57% power increase. We also provide this AST (assist-trigger) architecture concept for those whom are interested. In addition, the proposed data cache has been integrated with Proto3-ARM9TM, AMBA 2.0 system and related peripherals, designed previously in our lab, and implemented in TSMC 0.18-μm cell library. The resulting Proto3-ARM9TM has a core area of 1.963 × 1.955 mm2 and the whole chip area is 2.501 × 2.497 mm2. The average power consumption is 147 mW at the operating frequency of 129 MHz.
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Huang, Yi-Chieh, and 黃逸杰. "The Design and Verification of a Low-Power Instruction Cache Architecture for 32-bit Embedded Microprocessors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/94028317849099540460.
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碩士<br>國立臺灣科技大學<br>電子工程系<br>98<br>The speed gap between processors and DRAM devices is increasingly widened along with the progress of integrated circuit technique. To bridge such a gap, the use of cache memory in between the processor and the main memory has become indispensable. Nevertheless, the addition of cache memory also consumes a lot of power, which is a large part of the total power dissipation of an embedded system. Consequently, the design of a low-power cache memory has become an important issue in an embedded system.
In this thesis, a low-power instruction cache architecture is proposed. This architecture is based on the improvement of conventional cache architecture from both horizontal and vertical aspects, as well as the access behavior of instruction cache memory. Based on this, three techniques, including the filter cache with block detection, the data memory sub-banking and tag check ignoring, and the enable control of data memory, are used. With these techniques, the power dissipation can be reduced by the reduction of the access of L1 cache and the access of the tag memory and data memory during accessing L1 cache.
The resulting architecture can reduce about 55% power consumption compared to the conventional 4-way set-associative instruction cache. In addition, the proposed instruction cache has been integrated with Proto3-ARM9TM, AMBA 2.0 system and related peripherals, designed previously in our lab, and implemented as well as verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library, respectively. When realized with the FPGA, the system consumes 10302 LUTs and operates at maximum frequently of 29 MHz. When realized with the cell library, the Proto3-ARM9TM has a core area of 2.200 × 2.218 mm2 and the whole chip area is 3.036 × 3.028 mm2. The average power consumption is 147 mW at the operating frequency of 129 MHz.
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Zeng, Zhiyu. "Scalable Analysis, Verification and Design of IC Power Delivery." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10641.
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Due to recent aggressive process scaling into the nanometer regime, power delivery network design faces many challenges that set more stringent and specific requirements to the EDA tools. For example, from the perspective of analysis, simulation efficiency for large grids must be improved and the entire network with off-chip models and nonlinear devices should be able to be analyzed. Gated power delivery networks have multiple on/off operating conditions that need to be fully verified against the design requirements. Good power delivery network designs not only have to save the wiring resources for signal routing, but also need to have the optimal parameters assigned to various system components such as decaps, voltage regulators and converters. This dissertation presents new methodologies to address these challenging problems.
At first, a novel parallel partitioning-based approach which provides a flexible network partitioning scheme using locality is proposed for power grid static analysis. In addition, a fast CPU-GPU combined analysis engine that adopts a boundary-relaxation method to encompass several simulation strategies is developed to simulate power delivery networks with off-chip models and active circuits. These two proposed analysis approaches can achieve scalable simulation runtime.
Then, for gated power delivery networks, the challenge brought by the large verification space is addressed by developing a strategy that efficiently identifies a number of candidates for the worst-case operating condition. The computation complexity is reduced from O(2^N) to O(N).
At last, motivated by a proposed two-level hierarchical optimization, this dissertation presents a novel locality-driven partitioning scheme to facilitate divide-and-conquer-based scalable wire sizing for large power delivery networks. Simultaneous sizing of multiple partitions is allowed which leads to substantial runtime improvement. Moreover, the electric interactions between active regulators/converters and passive networks and their influences on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level co-design of a complete power delivery network is facilitated by an automatic optimization flow. Results show significant performance enhancement brought by the co-design.
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Chih-ChiunLiao and 廖智群. "Design and Verification of Micro Turbine Power Generator System." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/18795472881997258631.
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碩士<br>國立成功大學<br>航空太空工程學系碩博士班<br>101<br>The purpose of this research is to establish the micro gas generator by using turbocharger. This system combined a power turbine and a high speed generator. The power turbine is driven by the high exhaust gas temperature from the micro gas generator.
Due to the small size of the gas generator (compressor diameter = 1.5 inch), the operating speed is very high, usually up to 100,000RPM.The generator cannot afford such a high speed. Therefore, this system use the power turbine to drive the generator. This design will not only reduce the generator speed, but also isolate the heat from exhaust gas.
In this study, gas generator was built and ignited successfully. The turbine speed can be achieved175,000 RPM and the power turbine speed 41,000 RPM. The installation of power turbine does not affect the gas generator. The generator could provide 260 Watt when the current is set at 6 Amps. It successfully prove the feasibility of micro turbine power generator.
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Fan, Sheng-Wei, and 范勝崴. "Low Bandwidth JPEG-XR Transform Design and its System Verification." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/57886076491834641648.
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碩士<br>國立中正大學<br>資訊工程研究所<br>99<br>As a new generation image compression standard, there are many advantages in JPEG-XR, including high compression ratio twice than JPEG, lower complexity than JPEG-2000 with slight degradation of image quality, higher support, and etc. Since all block-based algorithms will have the blocking effect problem which is sensitive to human eyes, JPEG-XR proposed an algorithm named Photo Overlap Transform (Pre-filter) to solve this problem. There are three modes in pre-filter, and each of them has different corresponding reduction effects. If we process the macroblocks by the raster scan order and one MB in each pipeline stage, the huge memory access for doing the POT-2 mode which has the best reduction will lead to high memory bandwidth problem so as to reduce the throughout. Therefore, in this thesis we propose three low bandwidth techniques to decrease the data access in the overlapping area between MBs. Our proposed design can reduce 72% memory bandwidth when compared to the conventional method. At operating frequency of 117MHz, the proposed design could support the real-time processing for videos with resolution up to Full-HD@30fps.
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Hsu, Kai-Chuan, and 許凱筌. "The Design and Verification of a Low Cost Reflow Oven." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/82905689540713206212.
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碩士<br>龍華科技大學<br>電子工程系碩士班<br>103<br>The size of the electronic components is getting smaller because of the progress made in the integrated circuit industry. Therefore, most of the circuit been components such as resistors, capacitors, inductors and integrated circuits, etc. have replaced by surface mount devices (SMDs). It’s a necessary skill to solder the SMDs for electrical and electronic engineering students. if is a time-consuming task for students to solder by hand mean SMDs in a printed circuit board. Therefor a low cost reflow oven with temperature sensors, fans, motors, microcontrollers, and digital temperature control algorithm is devised in this thesis. The low cost reflow oven can be used to solder SMDs on PCBs with Lead, lead-free, and low-temperature solder paste. The reflow oven suits very well the need, of school laboratory and students. The effectiveness of the reflow oven has been verified with experiment micromouse and robotracer PCBs, and compared with commercially available products.
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Guan-Hao, Shen, and 沈冠豪. "Threshold Voltages Adjustment, Verification on N-Channel FinFET Transistors, and Circuit Design of Ultra-Wide-Band Low Noise Power Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/66004008753676517155.
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碩士<br>明新科技大學<br>電子工程研究所<br>102<br>The size of the device is deliberately shrunk down to nanometer scale because it can reduce the production cost and speed up the circuit functions. Unfortunately, the device becomes uncontrollable as the channels show tremendously leaky. This leaky issue can be avoided if FINFET devices are taken into account. The 3-D fin-like channel is then fully depleted as the gate is biased leaving no leaky paths. Once the leakage current is under control, the controllability is recovered.
Low-noise amplifier (Low Noise Power Amplifier; LNPA), contains the features of both LNA and PA. LNA is the front-end of the receiver for functioning pre-amplification. It plays a crucial role because it also suppresses the noises in subsequent stages dealing with the signals. On the other hand, a class-E PA amplifies the encoded signals mounting on the carrying waves before the antenna. Both amplifiers are coupled not only to double amplify the signals but also to widen the available channel band. The coupling effects can be verified by TSMC 180nm process technology through the software “Advanced Design System (ADS)” of Agilent. It is believed that the paper is supposed to have valuable contributions on wireless communication in the future.
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Tung, I.-Jui, and 童顗叡. "A SystemC Content Addressable Memory Power Estimation Tool for Early Design Verification." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/77984009767099566134.
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碩士<br>臺灣大學<br>資訊工程學研究所<br>98<br>Content Addressable memory (CAM) is a storage device which is widely implemented in the IP look-up table of a network router due to its high speed searching performance. In IPv6, the IP address will be 128 bits, as a result, the storage size of CAM will be larger in the future. The simulation time is an important factor affecting time-to-market. Using transistor level simulation such as SPICE in the early design stage of CAM will take huge time and delay time-to-market. SystemC is a system level modelling language and simulation platform, it provides better simulation efficiency and ability of hardware software co-design. However SystemC does not provide the function to estimate power consumption for low power algorithm or structure design. In this thesis, we developed a SystemC CAM power estimation tool (SystemC CAM PET) to estimate match-line power of CAM in the early design stage. We construct a new CAM match-line power model to estimate match-line power consumption. We simulated 10 benchmarks of Mibench and compared our SystemC CAM PET simulation results with SPICE simulation results. The simulation time is shorter in average 1654 and error rate of match-line power, search-line and storage cell estimation is average 14.79%, 11.681%, 3.66%. In addition, our SystemC CAM PET is able to calculate the miss rate, data comparison times, input and search data activity of each benchmark for PB-CAM structure. We also proposed a low power improvement example for PB-CAM structure using Gate-Block selection algorithm and verify it by our SystemC CAM PET. The number of data comparisons, miss rate and match-line power consumption are reduced by 49%, 51%, 51% in average.
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ZENG, YU-ZHE, and 曾于哲. "Structure and Anti-noise Design and Sensitivity Verification of Piezoelectric Low-frequency Accelerometer." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/393knm.
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碩士<br>南臺科技大學<br>機械工程系<br>107<br>With the pursuit of speed in 3C products, the confidential industry such as semiconductor manufacturing has become increasingly demanding for vibration. Therefore, the predecessors of this laboratory proposed active vibration isolation platform and piezoelectric low-frequency accelerometer gauge for micro-vibration suppression and measurement. This paper studies the sensitivity prediction analysis and the improvement of anti-noise ability on the second-generation accelerometer of this laboratory. The accelerometer structure uses ANSYS's modal and frequency response analysis to predict the accelerometer mode shape and available bandwidth, and ANSYS and theory predict the sensitivity of the accelerometer. In the piezoelectric analysis of ANSYS, the piezoelectric material is assumed to be a transversely isotropic material using elastic theory to obtain the complete piezoelectric parameters. In the experiment, four kinds of piezoelectric materials were used for the experiment. Finally, the ANSYS analysis and the actual measurement results were compared with the sensitivity calculation, and the sensitivity and the actual relationship of the accelerometer showed the same trend.The environment is full of many noise interferences. The accelerometer uses a charge amplifier to convert the charge into a voltage. This transmission is greatly affected. The general accelerometer puts the charge amplifier into the accelerometer to minimize this effect. Compared with the problem that the commercially available charge amplifier is too large, the self-made amplifier can be used to adjust the size and circuit design. In the experiment, the external environment noise (60Hz) will be reduced according to the way of external noise transmission, using grounding, shielding materials, filtering and changing the signal line type. Finally, the noise is reduced and applied to the accelerometers.
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Pan, Tai Yu, and 潘泰宇. "Design and Verification Test of High Power Induction Motor Driver for Electric Vehicles." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/32283576408194042218.
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碩士<br>長庚大學<br>電機工程學系<br>100<br>This thesis develops a TMS320F28335 DSP-based high power inverter for induction motor driving system used in electric vehicles (EVs). The performance of the driving system is verified with a test platform serving high power induction motors. A constant V/f closed-loop speed controller with slip and current compensations is designed for the driving system. The Matlab/Simulink program is employed for preliminarily test of the proposed controller. With the designed controller, a hardware prototype based on the TMS320F28335 DSP is built. Finally, experimental results verify the funtions of the high power induction motor driving system.
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He, Kai-Long, and 何凱隆. "The Design and Verification of Predictive Dynamic Power Management with 6502 Microcontroller IP." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/21448624852407976973.
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碩士<br>國立臺灣科技大學<br>電子工程系<br>97<br>With the increasing of the functionality of consumer electronics, extending battery life becomes one of the most important things in product design. Therefore, mobility and power consumption are considered seriously in consumer market. And Power Management is also becoming a develop trend at present. In this thesis, we implement a power-management hardware structure of which can be applied to microcontrollers. A microcontroller includes PWM, UART, and GPIO.
In this thesis, we complete our Power Management by using an algorithm and gated clocks. An algorithm, which manages CPU Burst in Operating System, is used as the main predictive function of our Power Management. Gated clocks are used to control all models in the system and can be synthesized by using Power Compiler to get latch-based style clock. We use the result calculated by exponential average as our prediction, and we also setup an energy gate value. We compare the prediction and the energy gate value to make the system get into saving power state more efficiently.
The microcontroller can be reconfigured by software to reduce the chip area and get a better performance. Besides, PWM provides four separated channels; each two can connect with each other to make longer channels. And each channel’s duty cycle also can be set by software. UART and GPIO are standard modules. The resulting PM system has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 cell library, respectively.
For the FPGA part, it takes 2279 LUTs and operates at the maximum working frequency of 10MHz. For the cell-based part; the core occupies 880 �慆 �e 880 �慆, which is approximately equivalent to 20499gates, while the whole chip occupies 1762 �慆 �e 1762 �慆. Our PM system can run at the maximum working frequency of 50MHz, with the chip power dissipation of 17.2 mW.
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Ferzli, Imad. "Verification and planning of the power delivery network in integrated circuits under design uncertainties." 2009. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=968437&T=F.
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Huang, Cheng-Yi, and 黃承毅. "Design and Verification of Low-Complexity and High-Accuracy Cell Search Algorithm for New Radio." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/76m3b5.
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碩士<br>中原大學<br>通訊工程碩士學位學程<br>107<br>In this thesis, we propose a low-complexity and high-accuracy cell search algorithm for new radio (NR) Synchronization Signals (SS) when 3GPP is about to complete the development of the 5G NR working standard. The algorithm is based on a low-complexity time-domain averaging timing carrier-frequency-offset (CFO) estimation combined with NR-SS parameter detection using one-shot low-complexity matching operations. In the design of the algorithm, firstly, this paper modifies the time-frequency estimation algorithm of Beek’97 [1], in which we avoid the estimation of signal-to-noise ratio (SNR) and accumulate multiple (Cyclic Prefix Orthogonal Frequency Division Multiplexing, CP-OFDM) symbols to obtain high-accuracy and low-complexity multiple-symbols time-frequency estimation algorithm to obtain the symbol timing and the fractional frequency offset (FFO). Then, this thesis uses the frequency-domain correlation algorithm to detect the Primary Synchronization Signals (PSS) parameters, and then obtains the integer carrier frequency offset (ICFO), and then obtains the sector cell index (Sector cell Index, Sector CID) detection rate. Furthermore, this paper uses a frequency-domain correlation algorithm to obtain the Group Cell Index (Group CID) of Secondary Synchronization Signals (SSS). The results of the computer simulation show the characteristics of this algorithm stated as follows: (1) The high accuracy of the average timing-frequency estimation can greatly improve the cell index detection rate, and (2) In the extremely low signal-to-noise ratio case of SNR=-6dB, high Cell Index detection rate of 70% can still be achieved.
In order to quickly verify our design, we use the software and hardware MATLAB / Simulink / Zedboard SDR mutual verification method. First of all, the proposed cell search algorithm is divided into three parts. The first part is the time-domain estimation algorithm in the time domain, which is used to estimate the coarse symbol timing and the fractional carrier frequency offset. The second part uses the PSS signal to detect the integer carrier frequency offset and the Sector CID simultaneously. The third part uses the SSS signal to detect the Group CID. Finally, the results of the hardware design are very close to the results of the MATLAB simulation, showing the correctness of our hardware design.
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Chiu, Chan-Feng, and 邱湛峰. "Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/03267217750637937033.
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碩士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline. The vertex shader performs these complex operations using logarithmic number system, and makes partial optimization for the hardware area based on the accuracy requirement of half-precision floating-point. The vertex shader design emphasizes low cost, and is well suited to low-accuracy embedded applications. The vertex shader is an SIMD (Single-Instruction-Multiple-Data) design with customized instruction set that allows users to write efficient vertex shader programs.
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Lu, Jun-Jen, and 盧俊仁. "Design, Verification and Risk Assessment of FPGA-based Instrumentation &; Control System for Nuclear Power Plant." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/04796854005867308489.
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博士<br>國立清華大學<br>工程與系統科學系<br>104<br>The instrumentation and control (I&;C) systems for the Lungmen nuclear power plant are fully digitized based on microprocessor and software technology, and extensively utilize multiplexing networks. That is, undetectable software faults and common cause failures due to software errors may occur, and that will defeat the redundancy of a nuclear power plant (NPP). A diverse backup implementation for the digital I&;C systems is an important means to defense against undetectable software faults. This research is to explore the feasibility and preliminary design of using FPGA-based instrumentation and control systems for nuclear power plants (PWR type Maanshan NPP and ABWR type Lungmen NPP).
First, this research explores a concepture design of using FPGA-based triple-redundant system for Anticipated-Transient-Without-Scam Mitigation System and Actuation Circuit (AMSAC) for Taipower’s Maanshan PWR type NPP. A simulated interface between AMSAC system and simplifed reactor/plant systems is developed to provide a test environment to validate the triple-redundant FPGA-based system.
Second, this paper presents a new feed-water controller under the automatic power regulating system (APR) for Taipower’s Lungmen ABWR type NPP (LMNPP). The new feed-water controller is designed by using a rule-based hierarchical fuzzy logic control algorithm and is implemented by using the modern FPGA technology. The FPGA-based feed-water controller is integrated into the LMNPP’s full-scope engineering simulator with APR system for validation and performance evaluation. Under automatic power maneuvers, two trajectories in the power/flow map have been tested and compared with the origin design. The transient response and the steady state tracking capability are evaluated and showed satisfactory results. The results demonstrate that the FPGA-based hierarchical fuzzy logic controller is a practical approach for automatic power operations in advanced nuclear power plant applications.
Third, this paper presents the system assessment of a quad-redundant RPS system design for Taipower’s Lungmen ABWR type NPP by utilizing FPGA technology. The FPGA-based RPS system has been assessed by using the LMNPP’s full-scope engineering simulator. Accident scenarios and abnormal conditions are inserted into the engineering simulator in order to activate the function of the FPGA-based RPS. The assessment results demonstrate that the FPGA-based nuclear instrumentation and control system is a practical approach to implement a diverse backup for nuclear power plant applications and can easily be used for the modernization of Taipower’s nuclear power plant analog systems. The software-free FPGA-based system may reduce the safety risk of undetectable software faults and common cause failures, and also minimize the regulatory licensing efforts and cost.
Final, the sensitivity study of probabilistic risk assessment (PRA) shows that RPS combined with ARI (Alternative Rod Insertion) contributes significant influence on the core damage frequency (CDF) calculation of LMNPP. The PRA sensitivity study is independent of the RPS technology.
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Tsai, Yi-Chang, and 蔡益昌. "Hardware Design, Implementation and Verification of the Analog Front-End for Software-Defined Power-Line Communications Platform." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/73856998597287055388.
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碩士<br>國立中央大學<br>通訊工程學系在職專班<br>103<br>PLC (Power line Communication) is a communication technology using power line as the transmission medium. The research topic of this thesis is on the design implementation and verification of the Analogy Front End (AFE) for a software-defined PLC platform which is composed of Analogy Front End (AFE) circuit board, Digital Analog Converter (DAC) and Analog Digital Converter (ADC) development board and FPGA board. The effectiveness of the AFE is demonstrated by a transmission of a software-defined OFDM signal, which is derived by referring to the HomePlug AV standard, through the real indoor electric outlet power line. We also measure the indoor PLC channel's response and investigate a particular phenomenon of powerline channel-special noise and channel variation using the composed software-defined PLC platform.
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Chang, Fu-Yuan, and 張福元. "Design and Verification of a Hip Power Sharing and Stance Control Knee Mechanism for Hip-knee-ankle-foot Orthoses." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/26585066565486512153.
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碩士<br>國立臺灣大學<br>機械工程學研究所<br>105<br>Recently, the number of people who has handicap handbook are growing, most of them are limb disorder. They always have degenerative arthritis, paralysis, and stroke. These diseases make the elders difficult with walking because of the weakness of the quadriceps or dysfunction in the knee joint. The stance control knee orthosis consists of a knee joint and knee lock control mechanism. It can provide the stability while patients sit or walk. It also can reduce the oscillation of body during walking.
The purpose of this research is to develop an orthosis with two main functions. One is the knee control mechanism and the other is the power sharing mechanism. Both mechanisms are respectively controlled by a cam and the ratchets. The knee control mechanism provides knee joint stability and the power sharing mechanism transmits the power from hip motor to knee angle help patients sit or stand in sit-to-stand motion. In order to simplify the control strategy, the two cams are controlled by one actuator. This thesis also test the orthosis after manufactured for the feasibility of two mechanisms.
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Wang, Li-Rong, and 王儷蓉. "Low Power Low Voltage Datapath Design." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/28197613558695753440.
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博士<br>國立交通大學<br>電子工程學系 電子研究所<br>101<br>Multiplication and multiplication-accumulation (MAC) are the very common mathematical operations and behaves as the key elements of a digital arithmetic module. In order to achieve the goal of performance improvement and power reduction, a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable MAC core is proposed. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two’s complementation circuit to reduce the area and improve the speed. The multiplier is then used to form a 32-bit reconfigurable MAC which can be flexibly configured to execute one 32×32, two 16×16 or four 8×8 signed multiply-accumulation. Experimentally, when implemented with a 130nm CMOS single-Vt standard cell library, operated in 100MHz frequency, the proposed multiplier with two various two’s complementation circuit architecture achieves a 15.8% area saving and 11.7% power saving over the prior design respectively. And the proposed reconfigurable MAC achieves 4.2% area and a 7.4% power saving over the MAC designs published so far if implemented with a mixed-Vt (MVT) standard cell library at 100MHz frequency further.
A chip of this proposed MAC core with built-in-self-test (BIST) circuit is designed, and implemented with the proposed 130nm academic-purpose MVT cell library. The post layout simulation of the chip shows that the chip can operate at 500MHz at a power consumption of 86.25 mW under the condition of 1.2 V VDD. Because of the limitation of testing equipment, the chip is measured at 125MHz and the power consumption of measured is 12.5mW, excluding the I/O pin and BIST circuit power consumption.
A new double-edge-triggered implicitly level-converting flip-flop based on the sense-amplifier latch structure (SA_DET-LCFF) is proposed. The feedback property of the sense amplifier eases the problem of the relatively large crossover current in the conventional differential static double-edge-triggered flip flop (DS_DET-FF), which facilities the power reduction and performance improvement significantly. Moreover, this design provides sufficient level conversion from a lower to a higher supply voltage without degrading circuit performance. Experimentally, when implemented with a 130-nm process, single normal-Vt and 0.84 V VDD condition, it achieves 64% power-delay product (PDP) improvement as compared to that of the DS_DET-FF If implemented in the same technology but with a mixed-Vt, it achieves 78% improvement on PDP. Thus, the proposed SA_DET-LCFF is suitable for the design of clustered voltage scaling (CVS) or dynamic voltage frequency scaling (DVFS) design platform.
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Chou, Chi-Wen, and 周啟文. "Low Power Multiplier Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/97752578308336946971.
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碩士<br>國立中山大學<br>資訊工程學系研究所<br>94<br>In this thesis, a novel low power multiplier design is introduced. We utilize the bypassing logic to construct a multiplier based on ripple carry array to minimize the switching activities rather than carry save array for the low power requirement and tree structure to enhance the performance. The advantage of using the bypassing logic in the ripple carry array multiplier is that it can use less extra hardware and achieve more power saving compared with conventional multipliers. The design of our circuit uses the standard TSMC 0.18um technology and simulates with Hspice. According to the simulation results, the proposed design can obtain power saving around 15% more than conventional multipliers, although it must occupy larger area.