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Journal articles on the topic 'Low-power design and verification'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 February 2022

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1

Liu, Guo Feng, Xi Liu, and Xing Guo Tian. "Design of low-power 2FSK demodulation circuit." MATEC Web of Conferences 232 (2018): 04069. http://dx.doi.org/10.1051/matecconf/201823204069.

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Aiming at the complex structure and high power consumption of the existing 2FSK demodulation circuit, this paper designs a simple structure and low power 2FSK demodulation circuit. A CMOS transistor matrix circuit is used to demodulate the 2FSK signals of 1200HZ and 2200HZ. The function model is established by using Matlab, and the number of sampling points is determined according to the simulation results and design requirements, and then the size of CMOS transistor matrix circuit is determined. The circuit uses Cadence software for functional verification, and HSPICE software is used for power consumption analysis. The simulation results meet the design requirements of low power consumption and achieve the desired demodulation effect.

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2

Potočný, Miroslav, Viera Stopjaková, and Martin Kováč. "Design and verification of a low-power AC/DC converter." Journal of Electrical Engineering 72, no. 2 (2021): 113–18. http://dx.doi.org/10.2478/jee-2021-0015.

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Abstract This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.

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3

Haripriya, K. R., Ajay Somkuwar, and Laxmi Kumre. "Low Power Checks in Multi Voltage Designs." WSEAS TRANSACTIONS ON ELECTRONICS 11 (July 1, 2020): 105–11. http://dx.doi.org/10.37394/232017.2020.11.13.

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Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

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Kapoor, Bhanu, and Shireesh Verma. "Power Management Design and Verification." Journal of Low Power Electronics 7, no. 1 (2011): 41–48. http://dx.doi.org/10.1166/jolpe.2011.1115.

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Mankar, Pranav J., Ajinkya M. Pund, Kunal P. Ambhore, and Shubham C. Anjankar. "Design and Verification of Low Power DA-Adaptive Digital FIR Filter." Procedia Computer Science 79 (2016): 367–73. http://dx.doi.org/10.1016/j.procs.2016.03.048.

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Asha Devi, Dharmavaram, Chintala Sandeep, and Sai Sugun L. "Design of Power Efficient 32-Bit Processing Unit." International Journal of Engineering & Technology 7, no. 2.16 (2018): 52. http://dx.doi.org/10.14419/ijet.v7i2.16.11415.

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The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit. The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.

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DHURY, S. CHOU, G. K. SINGH, and R. M. ME HRA. "Design and Verification Serial Peripheral Interface (SPI) Protocol for Low Power Applications." International Journal of Innovative Research in Science, Engineering and Technology 03, no. 10 (2014): 16750–58. http://dx.doi.org/10.15680/ijirset.2014.0310048.

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Rahman, Nahid, and B. P. Singh. "Design and Verification of Low Power SRAM using 8T SRAM Cell Approach." International Journal of Computer Applications 67, no. 18 (2013): 11–15. http://dx.doi.org/10.5120/11494-7201.

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9

Verma, Shireesh. "A Special Issue on Low Power Design and Verification Techniques." Journal of Low Power Electronics 7, no. 1 (2011): 1. http://dx.doi.org/10.1166/jolpe.2011.1111.

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10

Yadlapati, Avinash, and K. Hari Kishore. "Low power synthesis for asynchronous FIFO using unified power format (UPF)." International Journal of Engineering & Technology 7, no. 2.8 (2018): 7. http://dx.doi.org/10.14419/ijet.v7i2.8.10315.

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Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.

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Yadlapati, Avinash, and Hari Kishore Kakarla. "Low-power design-for-test implementation on phase-locked loop design." Measurement and Control 52, no. 7-8 (2019): 995–1001. http://dx.doi.org/10.1177/0020294019858089.

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Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-power technology in the phase of register transfer logic design, functional verification, register transfer logic and physical synthesis and physical design. Design for test is not an exception to this. The low-power design-for-test techniques can be applied at various levels of the design-for-test flow as in the scan insertion stage, automatic test pattern generation simulations stage, testing stage, and so on. Some of the reasons for the high-power utilization in the design-for-test phase can be due to the external circuitry being inserted during the design phase and not used in the functional mode. The complete circuit will be active in the test mode only. In this paper, the focus will be primarily on reducing the power during the automatic test pattern generation scan synthesis phase. All the scan flops are connected by a common scan clock with a fixed frequency. The intention of this study is to divide the clock frequency by half and make sure that the power is reduced without affecting any timing violations. Since the scan clock frequency is low, it can be further divided to ensure that power is reduced without affecting the testing process of the chip.

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12

Zhang, Hai Peng, Shao Dan Yang, Ya Dong Yin, and De Jun Wang. "A Power Supply On-Chip with Low Power Dissipation for Low Power Digital Integrated Circuit Applications." Applied Mechanics and Materials 513-517 (February 2014): 3844–49. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.3844.

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An implementation method of a power supply on-chip (PSOC) was presented for low power digital integrated circuit (IC) applications in this paper. The PSOC consists of a main power supply and a backup low power dissipation power supply, which is featured of micro-standby power consumption and fast switching. The PSOC was designed according to the design rules of SMIC 0.18μm CMOS process and validated both through simulation and silicon verification. The active area is about 0.035mm2 in fact. Post-layout simulation results indicate that output voltage of the PSOC is regulable in the range of 1.52~2.5V as input voltage is in the range of 2.0~3.6V, in which output of the main power supply is regulable in the range of 1.75~ 1.84V. The maximum quiescent current of main power supply is 16.23μA, while the maximum quiescent current of standby power is only 0.552μA. Experimental results indicate that the PSOC is capable of providing energy for the system digital IC implementation. Its power switching time is less than 148μs at the load capacitance of CL =56nF.

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13

Udupi, Shrinidhi, Joakim Urdahl, Dominik Stoffel, and Wolfgang Kunz. "Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 6 (2019): 1262–75. http://dx.doi.org/10.1109/tvlsi.2019.2906820.

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Yamaner, F. Yalcin, Selim Olcum, H. Kagan Oguz, Ayhan Bozkurt, Hayrettin Koymen, and Abdullah Atalar. "High-power CMUTs: design and experimental verification." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 59, no. 6 (2012): 1276–84. http://dx.doi.org/10.1109/tuffc.2012.2318.

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15

Yang, Ying, Yong Feng Zhang, and Ying Ying Xiao. "Layout Design and Verification of the Voltage Reference Module in the Auto Electronic Ignition Control Chip." Applied Mechanics and Materials 608-609 (October 2014): 933–36. http://dx.doi.org/10.4028/www.scientific.net/amm.608-609.933.

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This article describes the layout design and verification of the input module of a auto electronic ignition chip used in the field of automotive engineering. Using standard bipolar technology, full-custom design on the input module placement and routing, and completed the back-end verification. This chip has low power consumption, low cost, and stable performance.

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16

Yuan, Ling, and Ping Fan. "Verification of Dependable Architecture Based on Prototype Verification System." Advanced Materials Research 756-759 (September 2013): 4188–92. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4188.

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The electronic power system can be viewed as a system composed of a set of concurrently interacting subsystems to generate, transmit, and distribute electric power. The complex interaction among sub-systems makes the design of electronic power system complicated. Furthermore, in order to guarantee the safe generation and distribution of electronic power, the fault tolerant mechanisms are incorporated in the system design to satisfy high reliability requirements. As a result, the incorporation makes the design of such system more complicated. We propose a dependable electronic power system architecture, which can provide a generic framework to guide the development of electronic power system to ease the development complexity. In order to provide common idioms and patterns to the system designers, we formally model the electronic power system architecture by using the PVS formal language. Based on the PVS model of this system architecture, we formally verify the fault tolerant properties of the system architecture by using the PVS theorem prover, which can guarantee that the system architecture can satisfy high reliability requirements.

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17

Macko, Dominik, Katarína Jelemenská, and Pavel Čičák. "Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740002. http://dx.doi.org/10.1142/s0218126617400023.

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Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process.

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18

Tatevosyan, A. A. "Scientific basis for design low-speed synchronous permanent magnet generators for wind power plants." Omsk Scientific Bulletin, no. 175 (2021): 32–38. http://dx.doi.org/10.25206/1813-8225-2021-175-32-38.

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In this paper, the scientific basis for designing wind power plants (WPP) with low-speed synchronous generators on permanent magnets (SGPM) is understood as a system of scientific knowledge that forms the theoretical basis for the practice of designing a complex object, such as WPP consisting of interconnected equipment and structures designed to convert wind energy into electrical energy. Currently, the development of advanced WPP designs is receiving increased attention around the world. For example, in the Russian Federation, a promising direction is the creation of Autonomous WPP with low-speed medium- and low- power SGPMs that have the maximum range of applications by type of activity and climate zones throughout the territory. However, engineering approaches to the design of individual components of the WPP indicate the difficulties of developing a scientifically based methodology for optimizing the parameters of the WPP as a whole taking into account the mutual influence of individual components on each other. At the same time, the methodology for optimizing the parameters of WPP is understood as a tool for the scientific basis of design, which takes into account quality indicators and optimality criteria, energy and technical characteristics, as well as design stages with the results of preliminary and verification calculations. For the stage of verification calculations of VEU parameters, the scientific basis of design is determined by the construction of mathematical models and their research using application software packages for PCs, while for the stage of preliminary calculations, the development of analytical methods of analysis is important. This article discusses the scientific basis for designing wind turbines at the stage of preliminary calculations, formulated the problem of optimizing the parameters of low-speed WPP, proposed equations for the relationship of design parameters with the energy performance of wind turbines, providing the maximum efficiency of synchronous generators, taking into account the specified technical conditions

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19

Sun, Wei, Kui Hua Wu, Bo Yang, Rong Liang, Jian Wang, and Fei Wang. "Design Research of Unit Power Factor Power Converter." Advanced Materials Research 986-987 (July 2014): 1809–12. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1809.

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In view of the problems that traditional direct current control calculation is complex, that sensor precision requirements are high. This paper proposes a new control method of unit power factor power converter, which is easy to realize with simple control structure dispense with current sensor. Through the simulation and experimental verification, the control strategy can achieve unity power factor control, and the harmonic content is small and the operation is stable.

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20

Fotakis, Dimitris, Piotr Krysta, and Carmine Ventre. "The Power of Verification for Greedy Mechanism Design." Journal of Artificial Intelligence Research 62 (July 4, 2018): 459–88. http://dx.doi.org/10.1613/jair.1.11215.

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    Greedy algorithms are known to provide, in polynomial time, near optimal approximation guarantees for Combinatorial Auctions (CAs) with multidimensional bidders. It is known that truthful greedy-like mechanisms for CAs with multi-minded bidders do not achieve good approximation guarantees. In this work, we seek a deeper understanding of greedy mechanism design and investigate under which general assumptions, we can have efficient and truthful greedy mechanisms for CAs. Towards this goal, we use the framework of priority algorithms and weak and strong verification, where the bidders are not allowed to overbid on their winning set or on any subset of this set, respectively. We provide a complete characterization of the power of weak verification showing that it is sufficient and necessary for any greedy fixed priority algorithm to become truthful with the use of money or not, depending on the ordering of the bids. Moreover, we show that strong verification is sufficient and necessary to obtain a 2-approximate truthful mechanism with money, based on a known greedy algorithm, for the problem of submodular CAs in finite bidding domains. Our proof is based on an interesting structural analysis of the strongly connected components of the declaration graph.   

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21

Yoshikawa, Y., T. Matsuura, M. Kato, and M. Hori. "Design of low-humidification PEMFC by using cell simulator and its power generation verification test." Journal of Power Sources 158, no. 1 (2006): 143–47. http://dx.doi.org/10.1016/j.jpowsour.2005.10.003.

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22

Chi, Huajun, Sangman Kim, and Jusung Park. "Mixed Dual-rail Data Encoding Method Proposal and Verification for Low Power Asynchronous System Design." Journal of the Institute of Electronics and Information Engineers 51, no. 7 (2014): 96–102. http://dx.doi.org/10.5573/ieie.2014.51.7.096.

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23

Guo, Rui, Zhenghao Lu, Shaogang Hu, Qi Yu, Limei Rong, and Yang Liu. "Design and Verification of a Charge Pump in Local Oscillator for 5G Applications." Electronics 10, no. 9 (2021): 1009. http://dx.doi.org/10.3390/electronics10091009.

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A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design.

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24

Silveira, George Sobral, Alisson V. Brito, Helder F. de A. Oliveira, and Elmar U. K. Melcher. "Open SystemC Simulator with Support for Power Gating Design." International Journal of Reconfigurable Computing 2012 (2012): 1–8. http://dx.doi.org/10.1155/2012/793190.

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Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator.

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25

Gassoumi, Ismail, Lamjed Touil, Bouraoui Ouni, and Abdellatif Mtibaa. "An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology." Journal of Electrical and Computer Engineering 2019 (October 2, 2019): 1–11. http://dx.doi.org/10.1155/2019/9029526.

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Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential techniques in image and video compression systems, and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, quantum-dot cellular automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Furthermore, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption, and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool, is applied to estimate the power dissipation of the proposed circuit. The suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new window of opportunity for low power image processing systems.

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Yazhou, Shi, and Wang Weijun. "Calculation Method of Stability Derivatives and Verification for Power-lift Aircraft." MATEC Web of Conferences 179 (2018): 03018. http://dx.doi.org/10.1051/matecconf/201817903018.

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It is difficult to realize the STOL and high-speed cruise at one time when designing an aircraft, whereas the application of power-lift technology has successfully solved this technical problem. The research about the dynamic characteristics of power-lift aircraft in hover and low speed flight regime is key important for the selection of control strategy in transition process. However, if adopting the traditional aerodynamic calculation method based on thrust coefficient concept, the hover and low speed forward flight of power-lift aircraft cannot be studied as a unified process and the stability derivatives cannot be accurately calculated in low speed. In this paper, a method for calculating the stability derivatives and model the aircraft by using full dimensional aerodynamic data is proposed, which can not only solve the problems mentioned above, and it is very convenient for the design of the control law in the transient process.

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27

Wang, Ying, Xue Zhong Ai, Qi Liu, and Ren Yu Liu. "Design of Precise DC Millivolt Signal Source Based on System-on-Chip of C8051F410." Advanced Materials Research 382 (November 2011): 183–86. http://dx.doi.org/10.4028/www.scientific.net/amr.382.183.

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This paper describes design process of thermocouple signal precise source. System-on-chip of C8051F410 is a key to signal source. It can realize 15 bit analog output through internal two-path 12 bit current output type D/A .Signal amplification circuit includes power supply circuit, low drift, low noise signal that can be verification source of thermocouple measuring instrument.

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28

Wu, Jian, Jikang Sun, Tao Zhang, Hongbing Sun, Sai Ji, and Yajie Sun. "Design of a high-speed low-power wireless sensor node and verification for structural health monitoring." International Journal of Applied Electromagnetics and Mechanics 60, no. 4 (2019): 579–601. http://dx.doi.org/10.3233/jae-170051.

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Gassoumi, Ismail, Lamjed Touil, Bouraoui Ouni, and Abdellatif Mtibaa. "An Ultra-Low Power Parity Generator Circuit Based on QCA Technology." Journal of Electrical and Computer Engineering 2019 (October 7, 2019): 1–8. http://dx.doi.org/10.1155/2019/1675169.

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Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

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Chen, Bo. "Thermal Design, Analysis and Experimental Verification of a Satellite Borne Electronic Equipment." Advanced Materials Research 156-157 (October 2010): 611–14. http://dx.doi.org/10.4028/www.scientific.net/amr.156-157.611.

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Thermal design, finite element analysis and experiment verification of a satellite borne power amplifier are introduced in this paper. Some methods were adopted to help heat conduct and a simplified computing model was built. The analysis results show that the temperature scope of the main structure is from 45.3°C to50.7°C in high temperature work case and -9.7°C to -4.3°C in low temperature work case, and all of junction temperatures of components with high heat power consumption are lower than the derated maximum junction temperatures themselves and leave enough design margins. The experimental results show that the computing values are very close to experimental values and the largest error is 1.9°C, which proved that the simplification of model and the values of computing parameters are reasonable. Thermal analysis with reasonable model simplification and computing parameters would be helpful for production design.

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31

Zhang, Xu, Zhiguang Deng, Jun Li, Youwei Yang, Quan Ma, and Mingming Liu. "Design and Verification of Reactor Power Control Based on Stepped Dynamic Matrix Controller." Science and Technology of Nuclear Installations 2019 (November 3, 2019): 1–11. http://dx.doi.org/10.1155/2019/4973120.

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As key equipment in nuclear power plant, the reactor power control system is adopted to strictly control and regulate the reactor power of a PWR (pressurized water reactor) in a nuclear power plant. A well-optimized predictive control algorithm based on SDMC (stepped dynamic matrix controller) is developed and introduced in this paper and applied to the power regulation of a reactor power model. In addition, the test and verification of this application is conducted by two different methods and devices: the virtual verification platform and the physical DCS (digital control system). The result of the verification suggests that the application of SDMC gains a better performance in the maximum dynamic deviation, adjustment time, overshoot, and so on.

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Wei, Zhouhong, Jason Criss, Andy Bull, Fuhe Liang, and Yongsheng Wu. "The low-frequency seismic vibrator: design and experimental verification." First Break 36, no. 1 (2018): 77–84. http://dx.doi.org/10.3997/1365-2397.n0066.

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STAMENKOVIĆ, ZORAN. "SOC DESIGN FOR WIRELESS COMMUNICATIONS." Journal of Circuits, Systems and Computers 20, no. 08 (2011): 1505–27. http://dx.doi.org/10.1142/s0218126611008055.

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The paper emphasizes methods, architectures, and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all the problems involved. It shows how to go from description and verification to implementation and testing, presenting three systems-on-chip for three different wireless applications based on configurable processors and custom hardware accelerators.

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Wang, Yong, and Xiao Yu. "ICONE23-2003 THE RESEARCH FOR THE DESIGN VERIFICATION OF NUCLEAR POWER PLANT BASED ON VR DYNAMIC PLANT." Proceedings of the International Conference on Nuclear Engineering (ICONE) 2015.23 (2015): _ICONE23–2—_ICONE23–2. http://dx.doi.org/10.1299/jsmeicone.2015.23._icone23-2_1.

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35

Zhang, Sen, and Xiaoping Liao. "The thermoelectric-photoelectric integrated power generator and its design verification." Solid-State Electronics 170 (August 2020): 107818. http://dx.doi.org/10.1016/j.sse.2020.107818.

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Zhao, Zhengming, Don Tan, Bochen Shi, Yicheng Zhu, and Hua Jin. "A Breakthrough in Design Verification of Megawatt Power Electronic Systems." IEEE Power Electronics Magazine 7, no. 3 (2020): 36–43. http://dx.doi.org/10.1109/mpel.2020.3011775.

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Takahashi, Ryo, Keiji Tashiro, and Takashi Hikihara. "Router for Power Packet Distribution Network: Design and Experimental Verification." IEEE Transactions on Smart Grid 6, no. 2 (2015): 618–26. http://dx.doi.org/10.1109/tsg.2014.2384491.

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Mahanta, Hridoy Jyoti, Abhilash Chakraborty, and Ajoy Kumar Khan. "Design and verification of improved CMERE against power analysis attacks." Cyber-Physical Systems 6, no. 3 (2020): 165–79. http://dx.doi.org/10.1080/23335777.2020.1769735.

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Kapoulea, Stavroula, Costas Psychalinos, Ahmed S. Elwakil, and Mohammad Saleh Tavazoei. "Power-Law Compensator Design for Plants with Uncertainties: Experimental Verification." Electronics 10, no. 11 (2021): 1305. http://dx.doi.org/10.3390/electronics10111305.

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A power-law compensator scheme for achieving robust frequency compensation in control systems including plants with an uncertain pole, is introduced in this work. This is achieved through an appropriate selection of the compensator parameters, which guarantee that the Nyquist diagram of the open-loop system compensator-plant crosses a fixed point independent of the plant pole variations. The implementation of the fractional-order compensator is performed through the utilization of a curve-fitting-based technique and the derived rational integer-order transfer function is realized on a Field-Programmable Analog Array device. The experimental results confirm that the the phase margin is well preserved, even for ±40% variation in the pole location of the plant.

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Zhao, Yan, Xiao Wei Han, Li Hua Wu, and Fang Yu. "Design and Verification of Interconnection Network in an SOI-Based FPGA." Advanced Materials Research 159 (December 2010): 532–37. http://dx.doi.org/10.4028/www.scientific.net/amr.159.532.

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In designing an FPGA based on a 0.5 micron SOI-CMOS technology we experienced a crucial task of providing a robust programmable interconnection network to drive long-line and global signals through the entire chip. The performance and signal integrity of these signals are challenged by the variation in the process as well as the signal driving condition of the individual mapped circuits. In this paper, we focus on the design of an efficient long-line signal interconnect network targeting for high speed and low power consumption of the circuit operation in a tile-based FPGA. The design and verification of the long-line with booster in the channels and the clock network circuitry are described in details. The comparison of the simulation and measured signal timing data is reported.

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Rusowicz, Artur, Jakub Kajurek, and Kuat Baubekov. "Analysis of flow resistance in bundles of power plant condensers." E3S Web of Conferences 100 (2019): 00071. http://dx.doi.org/10.1051/e3sconf/201910000071.

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Shell-side pressure drop is a very important variable in the successful design of the condensers. The prediction of this pressure drop through the horizontal tube banks, with condensation, has long been a problem facing design engineers. Low pressure drop is a requirement in designing condensers for power plants. The paper presents a comparison of the various correlation to determine the pressure drop in the tube bundle. It is an important element for the verification of numerical simulations. Analysis of flow resistance for power plant condenser were made.

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A. A, Sujata, and Lalitha Y. S. "Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology." WSEAS TRANSACTIONS ON ELECTRONICS 12 (January 20, 2021): 1–8. http://dx.doi.org/10.37394/232017.2021.12.1.

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The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

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VURAL, Ahmet Mete, Ali Osman ARSLAN, and Mustafa DENİZ. "Design and Experimental Verification of a Single-Phase Asymmetric Hybrid Multi-level Inverter." European Journal of Engineering Science and Technology 3, no. 2 (2020): 1–17. http://dx.doi.org/10.33422/ejest.v3i2.344.

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In recent years, multi-level inverters have emerged as a feasible power conversion solution for medium and high power applications due to better harmonic performance and ability to operate at high voltage/power when compared to traditional two-level inverters. Since the output level of the multi-level inverters depends on the number of the switching elements, as more levels are required, more switching elements are used. This situation makes the circuit and the control design complex and the losses to upsurge. To overcome these limitations and produce low harmonic content at the output, reduced switch count topologies are popular. In this study, a single-phase asymmetric hybrid multi-level inverter is proposed by combining diode clamped and cascaded H-bridge topologies. The inputs of the proposed inverter are selected as two unequal DC voltage sources. In this regard, fewer switching elements are used to obtain the same number of voltage levels at the output when compared to traditional multi-level inverters. The efficiency and the harmonic performance of the proposed topology is both verified by simulation and experimental studies. The gating signals of the semiconductor switches are produced by phase disposition pulse width modulation with carriers’ frequency of 4 kHz. It is shown by the experiments that a maximum efficiency of 94 % and a total harmonic distortion of 29 % are attained in the case studies.

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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

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Gao, Qiang, Ke Feng Zhou, Sen Gai Yang, Huan Mao, and Jie Zhu. "Design and Development on Full Scope V&V Simulator of Nuclear Power Plant." Applied Mechanics and Materials 496-500 (January 2014): 1385–89. http://dx.doi.org/10.4028/www.scientific.net/amm.496-500.1385.

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In order to strengthen the ability of nuclear safety regulatory and avoid nuclear accident, full scope V&V simulator is designed and developed. By using RELAP-3D and MELCOR procedures coupled with the simulation platform, it achieves a whole conditions simulation which contains steady-state condition, transient condition and severe accident condition. The full scope V&V simulator can be used to do the design verification, operation verification, nuclear emergency and severe accident management program verification.

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Karagiannopoulos, Stavros, Athanasios Vasilakis, Panos Kotsampopoulos, Nikos Hatziargyriou, Petros Aristidou, and Gabriela Hug. "Experimental Verification of Self-Adapting Data-Driven Controllers in Active Distribution Grids." Energies 14, no. 10 (2021): 2837. http://dx.doi.org/10.3390/en14102837.

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Lately, data-driven algorithms have been proposed to design local controls for Distributed Generators (DGs) that can emulate the optimal behaviour without any need for communication or centralised control. The design is based on historical data, advanced off-line optimization techniques and machine learning methods, and has shown great potential when the operating conditions are similar to the training data. However, safety issues arise when the real-time conditions start to drift away from the training set, leading to the need for online self-adapting algorithms and experimental verification of data-driven controllers. In this paper, we propose an online self-adapting algorithm that adjusts the DG controls to tackle local power quality issues. Furthermore, we provide experimental verification of the data-driven controllers through power Hardware-in-the-Loop experiments using an industrial inverter. The results presented for a low-voltage distribution network show that data-driven schemes can emulate the optimal behaviour and the online modification scheme can mitigate local power quality issues.

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Wojciechowski, Jacek, Juliusz Modzelewski, Jan Ogrodzki, Leszek Opalski, and Krzysztof Zamłyński. "Computer-Aided Multi-Layer Design of Switch-Mode Power Circuits." International Journal of Electronics and Telecommunications 56, no. 3 (2010): 307–18. http://dx.doi.org/10.2478/v10177-010-0041-0.

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Computer-Aided Multi-Layer Design of Switch-Mode Power CircuitsSwitch-mode circuits are used as power processors, e.g. DC/DC converters, synchronous rectifiers, high-frequency resonant power amplifiers. Their efficient computer-aided design is a technical problem only partly resolved so far. This paper presents a multi-layer CAD methodology for switch-mode power circuits. It discusses several levels of modeling of switching devices. First rough design verification is feasible using ideal switch models. It gives a satisfactory first-cut design. Then full models and general-purpose tools provide more exact verification of the design. At this exact step the design procedure makes use of interactive improvement followed by automatic optimization of some quality based objective functions. The proposed methodology is shown to be especially useful for high power class-D voltage-switching resonant amplifiers, where the so far used experimental optimization is extremely cost consuming.

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Monfared, M., and H. Rastegar. "Design and experimental verification of a dead beat power control strategy for low cost three phase PWM converters." International Journal of Electrical Power & Energy Systems 42, no. 1 (2012): 418–25. http://dx.doi.org/10.1016/j.ijepes.2012.04.044.

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Tan, Ya Yun, He Zhang, Xiang Jing Zhang, and Lin Gan. "Design of Low-Noise Receiving Amplifier Circuit for Laser Proximity Fuze." Advanced Materials Research 926-930 (May 2014): 452–55. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.452.

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In order to improve the detection distance of laser proximity fuze without increasing laser power, the capability of laser fuze receiving weak laser echo signal must be improved. An avalanche photodiode (APD), which had the advantages of high sensitivity, low noise, with inner gain, was used as photodetector in laser fuze system to improve the capability of laser fuze detecting weak signal. The equivalent noise model of APD photoelectric conversion was analyzed, and the low-noise preamplifier and voltage amplification circuit matching the avalanche photodiode were designed. The noise ratio and frequency bandwidth of amplification circuit were analyzed and calculated, also the simulation and experimental verification were accomplished. The results showed that the circuit has wide bandwidth and high signal to noise ratio,which meets the requirements of subsequent processing circuitry of laser fuze.

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Lee, Sang Wook, and Soo-Whang Baek. "Implementation and Experimental Verification of Smart Junction Box for Low-Voltage Automotive Electronics in Electric Vehicles." Applied Sciences 10, no. 7 (2020): 2214. http://dx.doi.org/10.3390/app10072214.

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In this study, we designed and implemented a smart junction box (SJB) that was optimized for supplying power to low-voltage headlights (13.5 V) in electric vehicles. The design incorporated a number of automotive semiconductor devices, and components were placed in a high-density arrangement to reduce the overall size of the final design. The heat generated by the SJB was efficiently managed to mount an Intelligent Power Switch (IPS), which was used to power the headlights onto the printed circuit board (PCB) to minimize the impact on other components. The SJB was designed to provide power to the headlights via pulse width modulation to extend their lifetime. In addition, overload protection and fail/safe functions were implemented in the software to improve the stability of the system, and a controller area network (CAN) bus was provided for communications with various components in the SJB as well as with external controllers. The performance of the SJB was validated via a load operation test to assess the short circuit and overload protection functions, and the output duty cycle was evaluated across a range of input voltages to ensure proper operation. Based on our results, the power supplied to the headlights was found to be uniform and stable.

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