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Dissertations / Theses on the topic 'Low-power multiplier'

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Published: 5 June 2025

Last updated: 2 August 2025

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1

Zhou, Shun. "Multi-precision reconfigurable multiplier for low power application /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20ZHOU.

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2

Johansson, Kenny. "Low Complexity and Low Power Bit-Serial Multipliers." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1751.

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<p>Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital

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3

Oskuii, Saeeid Tahmasbi. "Design of Low-Power Reduction-Trees in Parallel Multipliers." Doctoral thesis, Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-1958.

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<p>Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital de

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4

Patel, Rishit Navinbhai. "Implementation of High Speed and Low Power Radix-4 8*8 Booth Multiplier in CMOS 32nm Technology." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1495371138748713.

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5

Remund, Craig Timothy. "Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd611.pdf.

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6

Sun, Kaihong. "Design andImplementation of a Module Generator for Low Power Multipliers." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1944.

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<p>Multiplication is an important part of real-time system applications. Various hardware parallel multipliers used in such applications have been proposed. However, when the operand sizes of the multipliers and the process technology need to be changed, the existing multipliers have to be redesigned. </p><p>From the point of library cell reuse, this master thesis work aims at developing a module generator for parallel multipliers with the help of software programs. This generator can be used to create the gate-level schematic for fixed point two's complement number multipliers. Based on the g

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7

Velaga, Srikirti. "Fault Modeling and Analysis for Multiple-Voltage Power Supplies in Low-Power Design." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368026670.

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8

Tong, Yajian. "Multiple-input multiple-output converters for future low-voltage DC power distribution architectures." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/52780.

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Multiple-input multiple-output (MIMO) converters have been identified as a cost-effective approach for energy harvesting and dispatching in hybrid power systems such as those envisioned in future smart homes and DC microgrids. Compared with relatively complex set-up of single-input single-output (SISO) converters linked at a common DC bus to exchange power, the MIMO converters possess promising features of fewer components, higher power density, and centralized control. This thesis addresses various issues regarding the development of MIMO converters. Both non-isolated and isolated MIMO conver

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9

Tennant, Mark P. "Low power adaptive equaliser architectures for wireless LMMSE receivers." Thesis, University of Edinburgh, 2007. http://hdl.handle.net/1842/2565.

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Power consumption requires critical consideration during system design for portable wireless communication devices as it has a direct influence on the battery weight and volume required for operation. Wideband Code Division Multiple Access (W-CDMA) techniques are favoured for use in future generation mobile communication systems. This thesis investigates novel low power techniques for use in system blocks within a W-CDMA adaptive linear minimum mean squared error (LMMSE) receiver architecture. Two low power techniques are presented for reducing power dissipation in the LMS adaptive filter, thi

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10

Depexe, Márcio Dalcul. "Concepção de um circuito energy harvesting aplicado a redes de sensores sem fio para sistemas de iluminação." Universidade Federal de Santa Maria, 2014. http://repositorio.ufsm.br/handle/1/8556.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior<br>This thesis aims to present the design and development of an Energy Harvesting (EH) circuit applied to wireless sensor networks (WSN), especially those that perform functions in lighting systems, such as monitoring or control. The primary function of an Energy Harvesting system is to convert, condition and manage energy from an available source in the environment, in order to power low power consumption devices, which usually would be fed by batteries. The most used energy sources in EH systems are solar, wind, electromagnetic wave

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11

Zhang, Duo. "DYNAMIC CMOS MIMO CIRCUITS WITH FEEDBACK INVERTER LOOP AND PULL-DOWN BRIDGE." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1377210272.

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12

Llanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.

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Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domín

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13

Fang, Xuefeng. "Small area, low power, mixed-mode circuits for hybrid neural network applications." Ohio : Ohio University, 1994. http://www.ohiolink.edu/etd/view.cgi?ohiou1173979063.

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14

Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.

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In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the dig

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15

Dhillon, Yuvraj Singh. "Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.

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Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/thr

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16

Wang, Jinpeng. "Impact of mobility and deployment in confined spaces on low power and lossy network." Thesis, Université Clermont Auvergne‎ (2017-2020), 2019. http://www.theses.fr/2019CLFAC024/document.

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La technologie des réseaux de capteurs sans fil (RCSF) est l’un des éléments constitutifs de l’Internet des objets (IoT). En raison de leurs caractéristiques de déploiement facile et de leur flexibilité, ils sont utilisés dans de nombreux domaines d’application. Les réseaux à faible consommation et à perte (LLN) sont un type spécial de WSN dans lequel les noeuds sont largement limités en ressources. Convergecast est l’un des modes de communication de base, dans lequel tout le trafic du réseau est destiné à une destination prédéfinie appelée collecteur. Tout en prenant en compte les domaines d’

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17

Mohanty, Saraju P. "Energy and Transient Power Minimization During Behavioral Synthesis." [Tampa, Fla.] : University of South Florida, 2003. http://purl.fcla.edu/fcla/etd/SFE0000129.

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18

Chaour, Issam, Ahmed Fakhfakh, and Olfa Kanoun. "Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting." Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-224264.

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For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson an

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Pieper, Leandro Zafalon. "Circuitos Multiplicadores Array de Baixo Consumo de Potência Aplicados a Filtros Adaptativos." Universidade Catolica de Pelotas, 2008. http://tede.ucpel.edu.br:8080/jspui/handle/tede/32.

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Made available in DSpace on 2016-03-22T17:26:08Z (GMT). No. of bitstreams: 1 leandro zafalon.pdf: 1268402 bytes, checksum: cd35030285126fa95b61d98c6a518798 (MD5) Previous issue date: 2008-08-08<br>The main goal of this work is the implementation and analyzes of new array multiplier architectures. These new architectures were recently presented in the scientific community by including different power reduction techniques, such as the use of efficient adder circuits and the optimization of the dedicated multiplication structures that allow the multiplication operation in the radix 2m. The new

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20

Morrison, Matthew Arthur. "Design of a Reversible ALU Based on Novel Reversible Logic Structures." Scholar Commons, 2012. http://scholarcommons.usf.edu/etd/4175.

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Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and ve

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21

Terres, Marco Antonio de Souza Madeira. "Arquiteturas de conversores de tensão para circuitos com múltiplas tensões de alimentação ajustadas de forma dinâmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/141259.

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Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MD

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22

Chou, Chi-Wen, and 周啟文. "Low Power Multiplier Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/97752578308336946971.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>94<br>In this thesis, a novel low power multiplier design is introduced. We utilize the bypassing logic to construct a multiplier based on ripple carry array to minimize the switching activities rather than carry save array for the low power requirement and tree structure to enhance the performance. The advantage of using the bypassing logic in the ripple carry array multiplier is that it can use less extra hardware and achieve more power saving compared with conventional multipliers. The design of our circuit uses the standard TSMC 0.18um technology and simulates

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23

LIN, SHIN-JUNG, and 林欣蓉. "Low-power CMOS multiplier complier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/80826445899773491677.

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碩士<br>國立中正大學<br>電機工程研究所<br>91<br>Abstract In recent year，electronic portable devices，such as mobile phones，PDA，and MP3，are commonly used。Therefore，the demands for High speed and low power VLSI arise。Digital signal processors(DSP) are commonly used on these electronic applications。As a result，how to minimize power consumption without losing speed performance is very important。Multiplier plays the most important role on DSP，since it usually organizes the critical path of DSP。Thus，the low power and high speed characteristics of multiplier become more and more important。Minimizing glit

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温明振. "Low Power Multiplier with Column Bypassing." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/84781238708324730686.

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25

Su, Hao-Zhi, and 蘇浩志. "Low Power Multiplier & Shifter Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/35224197962087219363.

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碩士<br>國立臺灣大學<br>資訊工程學研究所<br>90<br>This thesis presents a design methodology for the low power multiplier and the low power shifter. In the low power multiplier, the modified Booth architecture and the efficient sign extension can decrease the addition operation among partial products. By using fewer adders compared with the Braun-Wooley multiplier, the power consumption can be reduced. In order to enhance the performance of the multiplier, pipeline registers are inserted inside the multiplier to increase the throughput of the multiplier and Wallace tree 4:2 compressors are used to speed up the

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26

Guo, Cang-yuan, and 郭倉源. "Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/72910157957846921579.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point

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Jiang, Guan-Lin, and 江冠霖. "Low Power Multiplier with Alternative Bypassing Implementation." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/3467e5.

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碩士<br>國立中興大學<br>資訊科學與工程學系所<br>99<br>As portable devices have become increasingly popular, power reduction has become an important issue in device design. Because traditional row-bypassing multipliers and column-bypassing multipliers use tri-state buffers, they suffer from the floating-node problem. This problem in turn increases leakage power consumption. This paper presents a low power multiplier with an alternative design. The advantage of this multiplier design is that it does not use tri-state buffers, and can be used in the row-bypassing method or column-bypassing method. Based on UMC-90n

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Hou, Ching-Ho, and 侯慶和. "Design of Low-Power ALU and Multiplier." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/95551506108914621168.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>91<br>The ALU (Arithmetic Logic Unit) and multiplier are main elements of CPU. These perform all the operations required by CPU instructions, and dissipate much of the power consumption in CPU. If we reduce the power consumption of these two elements, we can achieve low power CPU. 　　In this thesis, we present two novel low power methods to implement the ALU and 4-2 compressor which used in multiplier, respectively. One is to abandon the “don’t care” condition in decoder of ALU. This method does not divide signal path into logical and arithmetic paths thus can achi

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29

shu, chia-jen, and 許嘉仁. "VLSI Design for Low Power and Low Cost Bypassing Multiplier." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/19369867117928848000.

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碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>95<br>In this paper, we proposed four novel low power multiplier designs based on improved row and column bypassing schemes. The basic idea is to eliminate unnecessary computation for power saving via signal bypassing. In an array multiplier, signal bypassing occurs on those columns or rows of adder corresponding to zero bits in the input operands. Previous designs resort to input gating and output multiplexing to accomplish signal bypassing. The proposed designs, however, successfully resolve the adverse DC power consumption problem due to troublesome input gat

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30

Chang, Jhih-Jie, and 張智傑. "Improvement of low power 2-Dimensional bypassing multiplier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/68906457820439940993.

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碩士<br>南台科技大學<br>電子工程系<br>97<br>Low power design is always one of the research keypoint in VLSI design. There are many multiplier architectures in digital circuits. The major claim of the 2D bypass multipliers is low power, which is achieved by reducing the transision time of the transistors. However, this method requires extra control circuit which is consumes more layout area. Thus, we proposed a bypassing adder cell (BAC) which will reduce the number of bypassing logic transistors. 　　There are many advantages gained by using BAC to realize bypass multiplier. For example, direct current consu

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Liu, Hsin-Chun, and 劉信均. "A Low Power Radix-4 Booth Multiplier Design." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26398031568419386105.

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碩士<br>國立中興大學<br>資訊科學與工程學系所<br>99<br>In this paper, we present a low power Booth multiplier with a conditionally gated decoder. Using the features of Booth decoding, our design can reduce the unnecessary node switching in Booth decoder. Based on UMC 90-nm CMOS technology, simulation results show that our decoder can achieve 11.05% improvement in dynamic power consumption and 10.05% in static power consumption. In addition, the power improvement of the 32 × 32 Booth multiplier can reach 6.07% in dynamic and 6.48% in static after implementing with our decoder.

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32

SHEKHAR, CHANDRA. "DESIGN OF LOW POWER LOW VOLTAGE GILBERT CELL BASED MULTIPLIER CIRCUIT." Thesis, 2011. http://dspace.dtu.ac.in:8080/jspui/handle/repository/13864.

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M.TECH<br>This thesis presents four quadrant analog multiplier circuit using CMOS and NMOS based on the Gilbert Cell multiplier architecture. Both the multipliers operate in saturation region. Analog multipliers are used in communication circuits, neural networks as well as frequency doublers, RMS circuits and phase detectors. High linearity is the prime issue for multipliers in conventional applications like modulation circuits. Initially, different multiplier architectures are reviewed. Multiplier using CMOS and NMOS is designed and simulated. The input power supply for the multipliers is ±

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Min, Jae Hong. "Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2495.

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Fused floating-point arithmetic units such as a floating-point fused Dot-Product (fused DP) and a floating-point fused Add-Subtract (fused AS) are employed for the implementation of the butterfly unit of the FFT due to their characteristics of low power and less area. In addition, the fused DP has less delay and lower error. Among the elements of the fused DP, two internal mantissa multipliers occupy the largest area and consume the largest power. A Multiple-Constant Multiplier (MCM) architecture has high speed, low power consumption, and small area compared to a conventional multiplier. The M

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Yang, Tsung-Han, and 楊宗翰. "A High-Performance Low-Power Multiplier with Reduced Spurious Switching." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/12811193786383626944.

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碩士<br>國立中正大學<br>電機工程所<br>95<br>Electronic portable devices, such as cellular phones, PDA, and digital camera, are commonly used in recent year. Digital signal processors (DSP) are often applied on these electronic apparatus. How to minimize power consumption without losing speed performance is very important. Multiplier plays the most important role on DSP, since it usually organizes the critical path of DSP. The low power and high speed characteristics of multiplier become more and more important. Decreasing glitches is a suitable method to reduce the power consumption while the speed perform

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Liang, Shish-chang, and 梁世昌. "Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/4n76rr.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>95<br>With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However, multiplier is always a fundamental component and influences the power consumption and performance much in many DSP and multimedia applications. Therefore, multiplier is the crucial design and need to be concerned at first. In these systems, the data width of input data is various because the different applications are operated in the same system. According to this characteristic of input data

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LIU, Chian-Lin, and 劉倩綝. "High-Level Power Optimization of Low-PowerLarge-Size Multiplier Circuits." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/74003714665656814451.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>96<br>As integrated-circuit (IC) technology advances to into deep-submicron (DSM) regime, more functionality can be combined into a single chip. To design such a complex device, low power consumption has become a significant requirement. If you want to design a high performance circuit, you should keep power consumption. The paper describe a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique using Synopsys PrimeTime tool for designing high-speed low-power SOC applications dealing wit

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Chang, Kai-cheng, and 張凱程. "High-performance Low-power Configurable Montgomery Multiplier for RSA Cryptosystems." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/61539011127731001243.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>The communication technology is changing rapidly every day, and the internet has played a very important role in our lives. Through specific protocols, people transform the data into 0’s and 1’s as digital signals and transfer them from sender to receiver via the network. Unfortunately, data transfer through the internet is open to the public, and too much exposure of private data may be a serious risk. To avoid this situation, we can encrypt the data before transmission to guarantee data confidentiality and privacy. The RSA encryption system is a simple and

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Hsu, Huan-Wei, and 許桓偉. "High-performance Low-power Montgomery Modular Multiplier for RSA Cryptosystems." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/12811941312759507932.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>99<br>The explosive growth in the data communications industry has positioned the internet to hold very important roles in our lives. Sending or receiving data on an open network is an invitation for unauthorized users to obtain your personal information. In order to avoid compromising sensitive information while transferring data, the data needs to be encrypted before transmission to ensure that the information remains safe and confidential. RSA is the most widely used public-key cryptosystem. An RSA operation is a modular exponentiation, which is usually achie

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Wu, Wei-Hong, and 吳威宏. "Low-Voltage Low-Power CMOS Multiplier Design Using Pipeline Latch High-Level Synthesis Approach." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02208380310385112207.

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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>The integrate-circuit technology scale down recently, more functionality can be combined into a single chip. So circuit complexity thereupon increases, performance and power consumption will be considered. The thesis describe a ways to increase speed of a circuit, and make up the high-level circuit. Chapter 1 introduce CMOS very large scale integrated circuits reason, power consumption and simulation software . Chapter 2 introduces a 16-bit Wallace tree multiplier circuit with VDD = 0.5V. Latch technology insert the multiplier become pipeline structure. Using Sy

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許恩. "A High-Performance and Low Power Montgomery Multiplier for RSA Cryptosystems." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/05656481671889119089.

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Lin, Kai-Feng, and 林楷峯. "Implementation of low power array multiplier based on CMOS and PTL." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/21918717424649532697.

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碩士<br>南台科技大學<br>電子工程系<br>97<br>Now days, the main development direction of ICs is to low-power consumption. In this way, the standby time will last longer. In array multipliers, many products are generated by AND gates, the improvement in [1] is to replace AND gates with NAND gates and to replace adders with transmission gates. However, this approach suffers from poor fan-out. Hence, in this thesis, we try to use partial products and its inverted signals as the control signals of the full adders. The ‘Sum’ output can be generated by the 2-input XOR gates while the ‘Cout’ can be generated by t

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Yeh, Ming-Chieh, and 葉明杰. "Low Power Alternating Logic Testable CMOS Array Multiplier and Analog Estimator." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/81899392476251317224.

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Ye, Ming-Jie, and 葉明杰. "Low Power Alternating Logic Testable CMOS Array Multiplier and Analog Estimator." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/13473460426749406024.

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Sung, Gang-neng, and 宋岡能. "A Low-power 2-dimensional Bypassing Digital Multiplier Design and A Low-power Sensorless Micro-controller for Brushless DC motors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/16824910590542118916.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>94<br>This thesis includes two research topics. The first topic is a low-power 2-dimensional bypassing digital multiplier design. The second one is a low-power sensorless micro-controller for brushless DC motors (BLDCM). The low-power 2-dimensional bypassing digital multiplier takes advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Hence, it is a 2-dimensional bypassing architecture. Thorough post-layout s

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Lin, Shu-Hsuan, and 林書玄. "High-Speed and Low-Power Multiplier-Accumulator Micro-Architecture and Circuit Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/68062221088208250298.

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碩士<br>國立交通大學<br>電子工程系所<br>93<br>A power-speed optimization technique of circuit level for a datapath of processors is proposed in this thesis. By using efficient multiplication algorithms, a high-speed multiplier-accumulator micro-architecture is designed in this thesis. According to this high-speed micro-architecture design, a low-power transistor level multiplier-accumulator is also implemented. Take the transistor size, the supply voltage, and the threshold voltage as tuning variables which are optimized jointly in terms of power and speed in this thesis which can reduce the dynamic power t

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Wang, Yen-Yuan, and 王彥淵. "A Low-Power Radix-4 Booth Multiplier Design Using Precise Operand Exchange." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/63516007279939452155.

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碩士<br>國立中興大學<br>資訊科學與工程學系<br>102<br>In this paper, we present a low power 16 × 16 Radix-4 Booth multiplier design using precise operand exchange. In the Booth algorithm the partial product is zero when the multiplier input is sequential 0/1. Our design can choose and set the preferable multiplier input between two operands to reduce the switching activity in the partial product generation. Moreover, we increase the chance of operand exchange by separating a 16 × 16 multiplier into four 8 × 8 multipliers with one-level recursion design. Based on TSMC 90-nm CMOS technology, simulation results sh

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Jan, Jeng-Shiun, and 詹政勳. "A Low-Power and High-Performance Function Generator for Multiplier-Based Arithmetic Operations." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/76225160736151191197.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>90<br>In this thesis, we develop an automatic hardware synthesizer for multiplier-based arithmetic functions such as parallel multipliers/multiplier-accumulator/inner-product calculator. The synthesizer is divided into two major phases. In the first phase called pre-layout netlist generation, the synthesizer generates the gate-level verilog codes and the corresponding test fixture file for pre-layout simulation. The second phase, called layout-generation, is to produce the CIF file of final physical layout based on the gate-level netlist generated in the first phas

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Lu, Yu-cheng, and 呂育誠. "All Digital Frequency Synthesizer Using Flying Adder Architecture and Low Power Low Latency 2-dimensional Bypassing Signed Multiplier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/vue22h.

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碩士<br>國立中山大學<br>通訊工程研究所<br>97<br>This thesis includes two topics. The first topic is an ADFS（All Digital Frequency Synthesizer）using a Flying Adder architecture. The second one is a low-power and low-latency 2-dimensional bypassing signed multiplier. In the first topic, the ADFS is implemented by only using the standard cell library of TSMC（Taiwan Semiconductor Manufacturing Company）0.18 μm 1P6M CMOS process. The turn-around time is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly enhanced. The design provides stable clock signals with f

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Lee, I.-Wen, and 李意文. "A Study of the Low Power Multiplier Design Based on Carry-Save Adder Array." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/94504137496814371951.

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碩士<br>國立交通大學<br>電子研究所<br>84<br>As the development of VLSI technology, the high density and high speed chip is easy to implement. The large power dissipation problem, however, is also in company with this development. So the low power circuit design is more and more important. In this thesis, a new design methodology of low power multiplier based on carry-save adder(CSA) array is presented. The proposed architecture is mainly emphasized on the delay- balance of the carry-save adder array to

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Chuang, Shang Mo, and 莊尚默. "Area-Efficient Low-Power Algorithmic Noise-Tolerant Architecture Based on High-Accuracy Fixed-Width Multiplier." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/12643301615733381007.

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碩士<br>長庚大學<br>電機工程學系<br>99<br>In this thesis, we propose a new algorithmic noise tolerant (ANT) multiplier architecture by using fixed-width multiplier to build the replica redundancy block. We design fixed-width multiplier with error compensation circuit via analyze of probability and statistics, by using input correction (IC) vector, minor input correction (MIC) vector and secondary minor input (SMIC) vector as constraint condition, to restrict the carries of major carry item, and we design the minor carry item and the secondary minor carry item to estimate the output value precisely. In ord

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