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Journal articles on the topic 'Low-power multiplier'

Author: Grafiati

Published: 5 June 2025

Last updated: 2 August 2025

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1

Kunal, Agarwal, and B. Ramesh K. "Design and Development of Low Power Array Multiplier." Journals of Advancement in Electronics Design 5, no. 1 (2022): 1–6. https://doi.org/10.5281/zenodo.6384138.

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<em>The progress of high-speed, low-power, and regular-layout multipliers is a latest in research. The multiplier's speed can be boosted by lowering the number of partial products generated. The array multiplier is one of many attempts to limit the amount of partial products generated in a multiplication process. To sum the carry products in less time, an array multiplier half adder was used. VLSI circuit designers are focused on producing high-speed integrated circuits with low power consumption. The multiplier, which is the most power-hungry component in digital circuits, is used for the

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2

Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 p

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3

Leela, S. Naga, Boppa Manisha, Palle Bharath, and Erram Praneeth. "Design of Wallace tree multiplier circuit using high performance and low power full adder." E3S Web of Conferences 391 (2023): 01025. http://dx.doi.org/10.1051/e3sconf/202339101025.

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The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consum

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Brunda, H. M., H. Jayalaxmi, H. N. Arpitha, Anupama R. Patil, and G. S. Manjushree. "Comparative Analysis of Various Multipliers Based on Performance." Scientia. Technology, Science and Society 2, no. 5 (2025): 100–108. https://doi.org/10.59324/stss.2025.2(5).08.

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In digital signal processing, computer arithmetic, and VLSI applications where speed, size, and power consumption are crucial design considerations, efficient multiplier architectures are crucial. The array multiplier, booth multiplier, Wallace tree multiplier, and dadda multiplier are the four commonly used multipliers that are compared in this study. Key performance measures like area, switching speed, latency, and power consumption were the focus of the evaluation. To evaluate each multiplier's performance under common computational circumstances, a simulation was conducted using the Xilinx

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Brunda, H.M., H. Jayalaxmi, H.N. Arpitha, Anupama R. Patil, and G.S. Manjushree. "Comparative Analysis of Various Multipliers Based on Performance." Scientia. Technology, Science and Society 2, no. 5 (2025): 100–108. https://doi.org/10.59324/stss.2025.2(5).08.

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In digital signal processing, computer arithmetic, and VLSI applications where speed, size, and power consumption are crucial design considerations, efficient multiplier architectures are crucial. The array multiplier, booth multiplier, Wallace tree multiplier, and dadda multiplier are the four commonly used multipliers that are compared in this study. Key performance measures like area, switching speed, latency, and power consumption were the focus of the evaluation. To evaluate each multiplier's performance under common computational circumstances, a simulation was conducted using the Xilinx

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6

S, Skandha Deepsita, Dhayala Kumar M, and Noor Mahammad SK. "Energy Efficient Error Resilient Multiplier Using Low-power Compressors." ACM Transactions on Design Automation of Electronic Systems 27, no. 3 (2022): 1–26. http://dx.doi.org/10.1145/3488837.

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The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 mul

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7

Sureshbabu, J., and G. Saravanakumar. "A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging." Journal of Medical Imaging and Health Informatics 10, no. 4 (2020): 814–21. http://dx.doi.org/10.1166/jmihi.2020.2936.

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In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to

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8

Rashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.

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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other mul

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9

Loganayaki, J., and M. Vasanthi. "Image Multiplier Based on Low Power Approximate Unsigned Multiplier." International Journal of Advance Research and Innovation 7, no. 2 (2019): 50–56. http://dx.doi.org/10.51976/ijari.721907.

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Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers us

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10

P, Karuppusamy. "DESIGN AND ANALYSIS OF LOW-POWER, HIGH-SPEED BAUGH WOOLEY MULTIPLIER." December 2019 2019, no. 02 (2019): 60–70. http://dx.doi.org/10.36548/jei.2019.2.001.

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The fundamental operations of the communication are the multiplication and division. The multiplier usually consumes a larger area and power and poses a very high latency. As all the above mentioned characteristics of the multiplier depends on the techniques utilized for the multiplication. It becomes necessary to put into effect a proper multiplier that reduces both the latency and the power consumption. So the paper analysis the performance of the various multipliers and scopes to develop a low power high speed multiplier based on the Baugh Wooley algorithm. The Performance analysis of the B

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11

Vallem, Dr Sharmila, G. Tejaswi, Hrithik Sidharth, and Shilpa Reddy. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. http://dx.doi.org/10.35940/ijrte.b7685.0712223.

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An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multiplier

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Dr., Sharmila Vallem, Tejaswi G., Sidharth Hrithik, and Reddy Shilpa. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. https://doi.org/10.35940/ijrte.B7685.0712223.

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<strong>Abstract: </strong>An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI

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13

B.Paulchamy, K.Kalpana, and J.Jaya. "An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 2605–11. https://doi.org/10.35940/ijeat.C5311.029320.

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Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and eff

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14

Dr. K. Nagi Reddy, K. Ruchitha, B. Sai Srinivas, and D. Venu, K. Vinay. "Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 3 (2024): 109–17. http://dx.doi.org/10.32628/cseit2410311.

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In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the near

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15

Pinto, Rohan, and Kumara Shama. "Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950019. http://dx.doi.org/10.1142/s0218126619500191.

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Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed para

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16

Rajmohan, V., and O. Uma Maheswari. "Improved Baugh Wooley Multiplier Using Cadence Register Transfer Level Logic for Power Consumption." Journal of Computational and Theoretical Nanoscience 14, no. 1 (2017): 277–83. http://dx.doi.org/10.1166/jctn.2017.6317.

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In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster than a conventional Baugh-W

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17

Sonia, Sharma* Anshul Soni. "IMPLEMENTATION OF LOW POWER AND LESS AREA BOOTH MULTIPLIER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 11 (2016): 261–65. https://doi.org/10.5281/zenodo.165633.

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Multiplication in hardware can be implemented in two ways either by using more hardware for achieving fast execution or by using less hardware and end up with slow execution. The area and power of the multiplier is an important issue, increment in speed and power results in large area consumption and vice versa. Multipliers play vital role in most of the high performance systems. Performance of a system depend to a great extent on the performance of multiplier thus multipliers should be fast and consume less area and hardware.

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18

Kumar, Pankaj, and Rajender Kumar Sharma. "Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing." Journal of Circuits, Systems and Computers 26, no. 02 (2016): 1750030. http://dx.doi.org/10.1142/s021812661750030x.

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To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC

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19

Ansiya, Eshack, and Krishnakumar S. "Pipelined Vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2951–58. https://doi.org/10.11591/ijece.v10i3.pp2951-2958.

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is

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20

Nikhil, R., G. V. S. Veerendra, J. Rahul M. S. Sri Harsha, and Dr V. S. V. Prabhakar. "Implementation of time efficient hybrid multiplier for FFT computation." International Journal of Engineering & Technology 7, no. 2.7 (2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.7.10755.

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Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridi

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21

Senthil Kumar, K. K., R. Vignesh, V. R. Vivek, Jagdish Prasad Ahirwar, Khamdamova Makhzuna, and R. Ram kumar. "Approximate Multiplier based on Low power and reduced latency with Modified LSB design." E3S Web of Conferences 399 (2023): 01009. http://dx.doi.org/10.1051/e3sconf/202339901009.

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The devised approximation multiplier can adapt the precision and processing power needed formul triplication sat run-time based on the needs of the user. To decrease error distance, we also suggest a straight forward error compensation circuit. There are two types of approximate multi pliers. Dynamic voltages caling can be used for the first kind, which controls the timing route of the multiplier. If the voltage is lower, the critical path will take longer to complete. As a result, when the time path is violated, errors occurs and approximated results are produced. These cond types involves re

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Prasada G.S, Sai Venkatramana, G. Seshikala, and S. Niranjana. "Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 6 (2020): 864–70. http://dx.doi.org/10.2174/2352096513666200107091932.

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Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it

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23

Bartlett, V. A., and E. Grass. "Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic." VLSI Design 12, no. 3 (2001): 349–63. http://dx.doi.org/10.1155/2001/94037.

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Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's comp

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A.Haritha, *., CH.Suryanarayana, B.Jeevitha, and G.Jyothi. "AN IMPLEMENTATION OF BYPASSING BASED MULTIPLIER BY USING INCREMENTAL ADDER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 4 (2016): 36–42. https://doi.org/10.5281/zenodo.48823.

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In the recent growth of the portable electronics is forcing the designers to optimize the existing design for better       performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. Hence it is very important for modern DSP systems to design high speed multipliers. Based on the simplification of addition operations in a  bypassing multiplier, a multiplier by using incremental adder  is proposed. Compared with row bypassing multiplier, colum

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Shikha, Singh, and B. Shukla Yagnesh. "Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder." TELKOMNIKA 21, no. 05 (2023): 1139–46. https://doi.org/10.12928/telkomnika.v21i5.24304.

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Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumpti

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Hong, Sangjin, Suhwan Kim, and Wayne E. Stark. "Low-power Application-specific Parallel Array Multiplier Design for DSP Applications." VLSI Design 14, no. 3 (2002): 287–98. http://dx.doi.org/10.1080/10655140290011087.

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Digital Signal Processing (DSP) often involves multiplications with a fixed set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error of the computation, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltag

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Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quart

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Priya, D. Hari. "Low Power Implementation and Analysis of Digital Fir Filter Based Low Power Multiplexer Base Shift/Add Multiplier." International Journal of Scientific Research 3, no. 8 (2012): 94–96. http://dx.doi.org/10.15373/22778179/august2014/29.

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Moghaddam, Majid, Mohammad Hossein Moaiyeri, Mohammad Eshghi, and Ali Jalali. "A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550124. http://dx.doi.org/10.1142/s0218126615501248.

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This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect a

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Dr. Bhushan Bandre. "Design and Analysis of Low Power Energy Efficient Braun Multiplier." International Journal of New Practices in Management and Engineering 2, no. 01 (2013): 08–16. http://dx.doi.org/10.17762/ijnpme.v2i01.12.

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Designing of Braun multipliers using various hybrid full adder circuits are described in this paper. In DSP and communication systems, multipliers are the main power consuming elements. Dynamic power dissipation contributes a lot to power consumption in CMOS logic. Braun multipliers employing Row bypassing techniques are designed to minimise the switching activities which aids in reducing dynamic power consumption. Full adders constitute a most vital part in multipliers. In this paper, Braun multiplier is designed using three different hybrid full adders .Area and power consumption of the resu

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Choubey, Abhishek, and Shruti Bhargava Choubey. "An area-delay efficient Radix-8 12x12 Booth multiplier in CMOS for ML accelerator." ITM Web of Conferences 74 (2025): 02007. https://doi.org/10.1051/itmconf/20257402007.

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The multiplier is a significant module of graphics processing units (GPUs) and digital signal processing (DSP). These applications need low power consumption. This paper proposes a low-power radix-8 12-by-12 Booth multiplier. The proposed radix-8 Booth multiplier is implemented using an optimized Binary to 2-’s complement (B2C), convertor, and optimized multiplexer at each stage of the Booth multiplier architecture. The proposed architecture uses 23% less power and 12% less delay compared to existing architecture. To validate the results, all designs are synthesized using Cadence CMOS technolo

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A. Swapna Bharathi, G. Sowjanya, N. Mageswari, N. Vinod Kumar, M. Venkatesh,. "Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders." Tuijin Jishu/Journal of Propulsion Technology 44, no. 4 (2023): 1238–44. http://dx.doi.org/10.52783/tjjpt.v44.i4.1005.

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Now a days, in CMOS circuits leakage power is becoming more and more remarkable in power dissipation. Digital signal processing performs many functions including multiplication which is the prominent one. In the design of energy efficient processor multipliers play a key role in which it determines the DSP processor efficiency. A 4*4Wallace tree multiplier employs gate diffusion input technique to minimize leakage power. It is designed by adopting one bit full adder. In the proposed method, full addersare replaced by4*4 Wallace tree multiplier. Power dissipation majorly occurs in full adders.

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Kishore, Mr G. Shyam, S. Jaya Prakash, B. Sachin, and D. Puneeth. "Design Wallace Tree Multiplier Using Reversible Gates." International Journal for Research in Applied Science and Engineering Technology 12, no. 4 (2024): 1701–12. http://dx.doi.org/10.22214/ijraset.2024.60154.

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Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree mul

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O, Vignesh, Mangalam H, and AnjuBala K. "Survey on Approximate Multipliers for Image Processing." European Journal of Advances in Engineering and Technology 5, no. 5 (2018): 344–49. https://doi.org/10.5281/zenodo.10708304.

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<strong>ABSTRACT </strong> Approximate computing has become ravishing approach for designing high performance and low energy consumption with limited loss in accuracy for many digital logic designs. Since there is a trade-off between speed/power with accuracy shown through previous research works. The demand of high speed and power efficiency as well as the feature of error tolerant applications has driven the development of approximate arithmetic circuits. The most important arithmetic modules in a processor are adder and multipliers to determine the performance for many computing tasks in to

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Eshack, Ansiya, and S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is

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36

Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.

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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that

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de la Cruz-Alejo, Jesús, and L. Noe Oliva-Moreno. "Low Voltage FGMOS Four Quadrants Analog Multiplier." Advanced Materials Research 918 (April 2014): 313–18. http://dx.doi.org/10.4028/www.scientific.net/amr.918.313.

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In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process e

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CVS, Chaitanya, Sundaresan C, and P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers

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S, Chaitanya CV, Sundaresan C, P. R. Venkateswaran, and Keerthana Prasad. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 845–52. https://doi.org/10.11591/ijeecs.v13.i2.pp845-852.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multi

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Tang, Xiqin, Yang Li, Chenxiao Lin, and Delong Shang. "A Low-Power Area-Efficient Precision ScalableMultiplier with an Input Vector Systolic Structure." Electronics 11, no. 17 (2022): 2685. http://dx.doi.org/10.3390/electronics11172685.

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In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. Th

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SARI, Filiz, and Yunus UZUN. "A COMPARATIVE STUDY: VOLTAGE MULTIPLIERS FOR RF ENERGY HARVESTING SYSTEM." Communications Faculty of Sciences University of Ankara Series A2-A3 Physical Sciences and Engineering 61, no. 1 (2019): 12–23. http://dx.doi.org/10.33769/aupse.469183.

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Voltage multipliers are widely used for energy harvesting processes to convert the received AC signal to DC signal, also enhanced the low level received signal. In this study, Villard, Dickson and Greinacher type voltage multipliers are analyzed without impedance matching and substrate materials to decide the effective voltage multiplier type depend on the inputs of the harvester. So, load resistance, input power and input frequencies’ effects are analyzed and compared with each other. Agilent Advanced Design System (ADS) is used for simulations. HSMS 2852 Schottky diode and capacitors are use

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Prasad, M. V. S. Ram, B. Kushwanth, P. R. D. Bharadwaj, and P. T. Sai Teja. "Low-power and high-speed approximate multiplier using higher order compressors for measurement systems." ACTA IMEKO 11, no. 2 (2022): 1. http://dx.doi.org/10.21014/acta_imeko.v11i2.1244.

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At present, approximate multipliers are used in the image processing applications. These approximate multipliers are designed with the help of higher order compressors to decrease the number of addition stages involved for the lessening stages. The approximate computing is the best technique to improve the power efficiency and reduce delay path. With the use of approximate computing multiple compressors are designed. In this paper, 10:2 compressors are designed and implemented in the 32-bit multiplier and compared with the exact 32-bit multipliers. The proposed higher bit compressors along wit

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Sadeghi, Mohsen, Mahya Zahedi, and Maaruf Ali. "The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications." Annals of Emerging Technologies in Computing 3, no. 3 (2019): 19–27. http://dx.doi.org/10.33166/aetic.2019.03.003.

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This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA)

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Ashwini, Banoth, Vyasa Ranjith Kumar, Nallawar Amulya, and Dr P. .Munaswamy. "A Low-Power High-Accuracy Approximate Multiplier Using High-Order Approximate Compressors." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40282.

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To address the need to reduce power consumption, approximate multipliers have emerged as a potential solution for fault-tolerant applications. In this work, we present a new 8x8 approximate multiplier that focuses on minimizing performance while maintaining a high degree of accuracy. The design features two key features: firstly, based on their importance, different weights are handled by the compressors with different levels of precision, allowing for a trade-off between energy efficiency and minimum error. Second, higher order approximation compressors such as 8:2 compressors are used for in

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Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of parti

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E., Sindhu Dharani, and Sharmila Raj V. "LOW POWER AND LOW AREA MULTIPLICATION CIRCUITS THROUGH PARTIAL PRODUCT PERFORATION." International Journal of Computational Research and Development 1, no. 2 (2017): 44–48. https://doi.org/10.5281/zenodo.437990.

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Focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. The partial product perforation method for creating approximate multipliers. It omit the generation of some partial products, thus reducing the number of partial products that have to be accumulated; we decrease the area, power. The major contributions of this work, the software-based perforation technique on the design of hardware circuits, obtaining the optimized design solutions regarding the power–area–error tradeoffs. Analyze in a mathematically

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Rajasekar, B., and K. Ashokkumar. "Low Power 4×4 Bit Multiplier Design Using DADDA, WALLACE Algorithm and Gate Diffusion Input Technology Kotha Vinil Kumar Reddy, Kondamuri Venkata Bala Manikanta Abhinav,." Journal of Computational and Theoretical Nanoscience 16, no. 8 (2019): 3359–66. http://dx.doi.org/10.1166/jctn.2019.8220.

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We designed two different multipliers in order to reduce the power consumption, propagation delay and also area occupied by the multiplier. Previously there is a multiplier using DADDA algorithm that consumes high power and propagation delay also more in order to overcome that problems we designed multiplier using WALLACE algorithm. This multiplier can overcome those drawbacks. For more efficient multiplier we used GDI (Gate Diffusion Input) technology used along with the WALLACE algorithm. This model has been designed using Tanner EDA tool.

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Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.

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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reduct

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Yu, Yihe, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin, and Zhiyi Yu. "Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model." Electronics 13, no. 7 (2024): 1284. http://dx.doi.org/10.3390/electronics13071284.

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finall

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Chukkaluru, Ravi Shankar Reddy, Venkata Gopi Kumar Padavala, Manikandan Radhakrishnan, and Bhavana Kuruva. "A high speed and power efficient multiplier based on counterbased stacking." A high speed and power efficient multiplier based on counterbased stacking 32, no. 1 (2023): 98–106. https://doi.org/10.11591/ijeecs.v32.i1.pp98-106.

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High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These pa

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