Relevant bibliographies by topics / Low voltage integrated circuits – Design and construction

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Low voltage integrated circuits – Design and construction'

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Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Low voltage integrated circuits – Design and construction"

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Richelli, Anna. "Low-Voltage Integrated Circuits Design and Application." Electronics 10, no. 1 (January 5, 2021): 89. http://dx.doi.org/10.3390/electronics10010089.

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One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...]
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Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (August 28, 2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.

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AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.
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Serdijn, Wouter A., Albert C. Van Der Woerd, Arthur H. M. Van Roermund, and Jan Davidse. "Design principles for low-voltage low-power analog integrated circuits." Analog Integrated Circuits and Signal Processing 8, no. 1 (July 1995): 115–20. http://dx.doi.org/10.1007/bf01239382.

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Manku, T., G. Beck, and E. J. Shin. "A low-voltage design technique for RF integrated circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 10 (1998): 1408–13. http://dx.doi.org/10.1109/82.728853.

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Lee, Min Chin, Ming Chia Hsieh, and Chi Jing Hu. "Implementation and Design of High PSRR Low Dropout Regulator." Advanced Materials Research 614-615 (December 2012): 1553–57. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1553.

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As the progress with all kinds of mixed-mode signal circuits, the requirements of power management become increasingly stringent. Therefore it takes all kinds of high-performance linear regulator to produce a very clean and stable voltage. Here cascading technique is used to increase the output impedance in this architecture. The output voltage is less susceptible to variation of input voltage, resulting in a clean and stable voltage which is used the operating voltage of internal circuits in a mixed-mode signal integrated circuit chip. This paper using the TSMC 0.35μm CMOS 2P4M process to implement the design of high PSRR LDO regulator, having chip area, 1.34 mW consumption power. The chip supply voltage can from 2.9V to 3.3V with -106dB and -65dB PSRR at 1KHz and 100KHz, and its output voltage can stable at 1.2V and less than 2.4mV ripple voltage at maximum loading current 20 mA.
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Tarim, T. B., M. Ismail, and H. H. Kuntman. "Robust design and yield enhancement of low-voltage CMOS analog integrated circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48, no. 4 (April 2001): 475–86. http://dx.doi.org/10.1109/81.917984.

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HUNG, YU-CHERNG, SHAO-HUI SHIEH, and CHIOU-KOU TUNG. "A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 89–105. http://dx.doi.org/10.1142/s0218126611007104.

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Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.
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ALLSTOT, DAVID J., SANKARAN ANIRUDDHAN, MIN CHU, JEYANANDH PARAMESH, and SUDIP SHEKHAR. "RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 377–428. http://dx.doi.org/10.1142/s0129156405003247.

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Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides comparatively higher gain and lower noise figure. Aside from the traditional passive and active Gilbert mixers, the even-harmonic and masking-quadrature mixers are developed to combat second-order non-linearity and improve image-rejection, respectively. For quadrature carrier generation, the degeneration-injected QVCO is superior to the cascode-injected QVCO both in terms of phase noise and tuning range. The Colpitts QVCO is attractive as a low-noise alternative as it does not disturb the output voltage as much as its traditional LC counterpart and thus offers lower phase noise.
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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.
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Petrosyants, Konstantin O., Igor A. Kharitonov, and Nikita I. Ryabov. "Electro-Thermal Design of Smart Power Devices and Integrated Circuits." Advanced Materials Research 918 (April 2014): 191–94. http://dx.doi.org/10.4028/www.scientific.net/amr.918.191.

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An efficient methodology of electro-thermal design of smart power semiconductor devices and ICs, based on the combined use of SPICE circuit analysis tool and software tools for 2D/3D thermal simulation of IC chip construction, is presented. The features of low, medium and high power elements, temperature sensors, IC chips simulation are considered.
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Dissertations / Theses on the topic "Low voltage integrated circuits – Design and construction"

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Murty, Anjali. "Highly linear, rail-to-rail ICMR, low voltage CMOS operational amplifer." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/14884.

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Low, Aichen. "A floating-gate low dropout voltage regulator." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.

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Dong, Zhiwei. "Low-power, low-distortion constant transconductance Gm-C filters." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/25400.

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Zhong, Jian Yu. "Design of high-speed power-efficient SAR-type ADCs." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691882.

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Siddique, Nafiul Alam. "Spare Block Cache Architecture to Enable Low-Voltage Operation." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/216.

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Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.
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Padwal, Prachi Gulab. "Just-In-Time Power Gating of GasP Circuits." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/211.

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In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle. This method is called power gating. This thesis presents a state-preserving technique to achieve power savings in GasP family of asynchronous circuits by turning off the power when the circuit is idle. The power control logic turns on the power in anticipation of the receiving data. The power control logic turns off the power when the stage is idle either because it is empty or because the pipeline is clogged. The low logical effort of GasP circuits makes just-in-time power gating possible on a stage-by-stage basis. A new latch called Lazy Latch is introduced in this thesis. The lazy latch preserves its output and permits power gating of its larger transistors. The lazy latch is power efficient because it drives strongly only when necessary. A new latch called Blended Latch is proposed in this thesis which blends the advantages of the Conventional latches and the Lazy latches. Performance of power gating is evaluated by comparing the power-gated pipeline against the non-power gated pipeline. Power savings achieved are dependent on the duty cycle of operation. The fact that just-in-time power gating achieves power savings after it is idle for a minimum of 106 cycles makes it useful in limited applications where a quick start is required after long idle times.
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Lauterbach, Adam Peter. "Low-cost SiGe circuits for frequency synthesis in millimeter-wave devices." Australia : Macquarie University, 2010. http://hdl.handle.net/1959.14/76626.

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"2009"
Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010.
Bibliography: p. 163-166.
Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion.
Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices.
Mode of access: World Wide Web.
xxii, 166 p. : ill (some col.)
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Yang, Yun Ju 1980. "Impacto de técnicas de redução do consumo de energia no projeto de SoCs Multimedia." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275743.

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Orientador: Guido Costa Souza de Araújo
Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação
Made available in DSpace on 2018-08-19T00:08:02Z (GMT). No. of bitstreams: 1 Yang_YunJu_M.pdf: 3101962 bytes, checksum: 3711cbf9c4db60e5d2938d566db0d87c (MD5) Previous issue date: 2011
Resumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção correta de um sistema eletrônico de baixo consumo de energia é um problema de vários níveis de complexidade e exige estratégias sistemáticas na sua construção. Fora disso, a adoção de qualquer técnica de redução de energia sempre está vinculada com objetivos especiais e provoca alguns impactos no projeto. Apesar dos projetistas conheçam bem os impactos de forma qualitativa, as detalhes quantitativas ainda são incógnitas ou apenas mantidas dentro do 'know-how' das empresas. Neste trabalho, de acordo com resultados experimentais baseado num plataforma de SoC1 industrial, tentamos quantificar os impactos derivados do uso de técnicas de redução de consumo de energia. Nos concentramos em relacionar o fator de redução de energia de cada técnica aos impactos em termo de área, desempenho, esforço de implementação e verificação. Na ausência desse tipo de dados, que relacionam o esforço de engenharia com as metas de consumo de energia, incertezas e atrasos serão frequentes no cronograma de projeto. Esperamos que este tipo de orientações possam ajudar/guiar os arquitetos de projeto em selecionar as técnicas adequadas para reduzir o consumo de energia dentro do alcance de orçamento e cronograma de projeto
Abstract: The semiconductor industry has always faced strong demands to solve the problem of heat dissipation and reduce the power consumption in electronic devices. This trend has been increased in recent years with the action of environmental sustainability. The correct conception of an electronic system for low power consumption is an issue with multiple levels of complexities and requires systematic approaches in its construction. However, the adoption of any technique for reducing the power consumption is always linked with some specific goals and causes some impacts on the project. Although the designers know well that these impacts can affect the design in a quality aspect, the quantitative details are still unkown or just be kept inside the company's know-how. In this work, according to the experimental results based on an industrial SoC2 platform, we try to quantify the impacts of the use of low power techniques. We will relate the power reduction factor of each technique to the impact in terms of area, performance, implementation and verification effort. In the absence of such data, which relates the engineering effort to the goals of power consumption, uncertainties and delays are frequent. We hope that such guidelines can help/guide the project architects in selecting the appropriate techniques to reduce the power consumption within the limit of budget and project schedule
Mestrado
Ciência da Computação
Mestre em Ciência da Computação
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Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.

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Books on the topic "Low voltage integrated circuits – Design and construction"

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S, Abu-Khater Issam, and Elmasry Mohamed I. 1943-, eds. Advanced low-power digital circuit techniques. Boston: Kluwer Academic Publishers, 1997.

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Tajalli, Armin. Extreme low-power mixed signal IC design: Subthreshold source-coupled circuits. New York: Springer, 2010.

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Tajalli, Armin. Extreme low-power mixed signal IC design: Subthreshold source-coupled circuits. New York: Springer, 2010.

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Adoración, Rueda, and Huertas José L, eds. Low-voltage CMOS log companding analog design. Boston: Kluwer Academic Publishers, 2003.

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Rincón-Mora, Gabriel A. Analog IC design with low-dropout regulators. New York: McGraw-Hill, 2009.

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Kularatna, Nihal. Power electronics design handbook: Low-power components and applications. Boston: Newnes, 1998.

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Power electronics design handbook: Low-power components and applications. Boston: Newnes, 1998.

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Carbognani, Flavio. Low-power techniques for low-frequency VLSI applications. Konstanz: Hartung-Gorre, 2007.

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Yeo, Kiat Seng. CMOS/BiCMOS ULSI: Low voltage, low power. Upper Saddle River, NJ: Prentice Hall PTR, 2002.

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Avinash, Lakshminarayana, and Shukla Sandeep K, eds. Low power design with high-level power estimation and power-aware synthesis. New York: Springer, 2012.

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Book chapters on the topic "Low voltage integrated circuits – Design and construction"

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Rabaey, Jan. "Ultra Low Power/Voltage Design." In Integrated Circuits and Systems, 289–316. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-71713-5_11.

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Verma, Naveen, and Anantha P. Chandrakasan. "Ultra Low Voltage SRAM Design." In Integrated Circuits and Systems, 89–126. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-88497-4_4.

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Serdijn, Wouter A., Albertc C. Woerd, Arthur H. M. Roermund, and Jan Davidse. "Design Principles for Low-Voltage Low-Power Analog Integrated Circuits." In Low-Voltage Low-Power Analog Integrated Circuits, 115–20. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2283-6_8.

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Baschirotto, Andrea. "Low-Voltage Switched-Capacitor Filters." In Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits, 215–50. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/0-306-48089-1_10.

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Wojtyna, Ryszard, Piotr Grad, and Jaroslaw Majewski. "Four-Quadrant CMOS Amplifier for Low-Voltage Current-Mode Analog Signal Processing." In Mixed Design of Integrated Circuits and Systems, 47–52. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5651-0_8.

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Lu, Yan, and Rui P. Martins. "Design of Low Standby Power Fully Integrated Voltage Regulators." In Low-Power Circuits for Emerging Applications in Communications, Computing, and Sensing, 33–56. First edition. | Boca Raton : CRC Press / Taylor & Francis, [2018] | Series: Taylor and Francis series in devices, circuits, & systems: CRC Press, 2018. http://dx.doi.org/10.1201/9780429507564-2.

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Arbet, Daniel, Lukas Nagy, and Viera Stopjakova. "Ultra-Low-Voltage IC Design Methods." In Integrated Circuits/Microchips. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.91958.

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"LowVoltage Analog CMOS Filter Design." In Low-Voltage/Low-Power Integrated Circuits and Systems. IEEE, 2009. http://dx.doi.org/10.1109/9780470545065.ch10.

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"A CurrentBased MOSFET Model for Integrated Circuit Design." In Low-Voltage/Low-Power Integrated Circuits and Systems. IEEE, 2009. http://dx.doi.org/10.1109/9780470545065.ch2.

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"Two New Directions in LowPower Digital CMOS VLSI Design." In Low-Voltage/Low-Power Integrated Circuits and Systems. IEEE, 2009. http://dx.doi.org/10.1109/9780470545065.ch13.

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Conference papers on the topic "Low voltage integrated circuits – Design and construction"

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Hudelson, John N., Jeremy Stark, Hannah Gibson, Fang Hao, Zhongkai Xu, Malay Mazumder, and Mark N. Horenstein. "Development and Evaluation of Prototype Transparent Electrodynamic Screen (EDS) Integrated Solar Collectors for Automated Dust Removal." In ASME 2014 8th International Conference on Energy Sustainability collocated with the ASME 2014 12th International Conference on Fuel Cell Science, Engineering and Technology. American Society of Mechanical Engineers, 2014. http://dx.doi.org/10.1115/es2014-6597.

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The integration of transparent electro-dynamic screen (EDS) on the front surface of solar mirrors and glass cover plates of photovoltaic panels has a strong potential to significantly reduce the frequency of water-based cleaning needed to mitigate losses from dust depositions present in arid regions. The objective of our research was to develop and evaluate prototype transparent EDS-integrated mirrors and solar panels for their self-cleaning functions, with an aim to keep the collectors clean at a low cost without water or manual labor. This paper focuses on the design, fabrication, and laboratory evaluation of a prototype EDS integrated second surface mirrors and solar panels. The EDS consists of a set of parallel transparent electrodes screen-printed on the optical surface and embedded in a thin transparent dielectric film. By applying three-phase, low current, low frequency high voltage-pulses to the electrodes, electro-dynamic repulsion forces and a traveling wave are created for removing dust particles from the surface of the collectors. Design and construction of an environmental test chamber to simulate different atmospheric conditions of semi-arid and arid areas with respect to temperature, RH, and dust deposition conditions are briefly described. A non-contact specular reflectometer was designed, constructed and calibrated for measuring specular reflection efficiency of the mirrors. Laboratory evaluation of the performance of the EDS-integrated collectors was completed using humidity controlled environment test chamber where the prototype mirrors and panels were examined for their self-cleaning action. In each experiment, the solar collectors were loaded with dust until the specular reflectance of the test mirror or the short circuit current of the panel showed a significant decrease. The EDS was then operated for one minute and the relative output was recorded. The results show that the specular reflectivity of EDS mirrors and the short circuit current of the EDS panels can be restored by more than 90% of the values measured under the clean conditions.
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Seok, Mingoo, Scott Hanson, Jae-Sun Seo, Dennis Sylvester, and David Blaauw. "Robust ultra-low voltage ROM design." In 2008 IEEE Custom Integrated Circuits Conference - CICC 2008. IEEE, 2008. http://dx.doi.org/10.1109/cicc.2008.4672110.

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Jannesari, A., and M. Kamarei. "Design of a Low Voltage Low-Phase-Noise Complementary CMOS VCO." In 2007 International Symposium on Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441889.

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Hsu, C. B., and J. B. Kuo. "MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits." In 2014 International Symposium on Integrated Circuits (ISIC). IEEE, 2014. http://dx.doi.org/10.1109/isicir.2014.7029442.

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Campana, Renato V., Hamilton Klimach, and Sergio Bampi. "0.5 V Supply Resistorless Voltage Reference for Low Voltage Applications." In SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2800986.2800987.

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Machowski, W., J. Jasielski, and S. Kuta. "Low Voltage Low Frequency Continuous Time CMOS Antialiasing Filters." In 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/mixdes.2007.4286241.

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Cortes, Fernando Paixao, Guilherme Freitas, Henrique L. A. Pimentel, Juan P. Martinez Brito, and Fernando Chavez. "Low-Power/Low-Voltage analog front-end for LF passive RFID tag systems." In 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2013. http://dx.doi.org/10.1109/sbcci.2013.6644868.

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Quendera, Filipe, and Nuno Paulino. "A low voltage low power temperature sensor using a 2nd order delta-sigma modulator." In 2015 Conference on Design of Circuits and Integrated Systems (DCIS). IEEE, 2015. http://dx.doi.org/10.1109/dcis.2015.7388608.

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Wojtyna, Ryszard. "Low-voltage quasi-linear current-to-voltage converter for analog signal processing." In 2016 MIXDES - 23rd International Conference "Mixed Design of Integrated Circuits and Systems". IEEE, 2016. http://dx.doi.org/10.1109/mixdes.2016.7529775.

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Dualibe, Carlos, Pablo Petrashin, Luis Toledo, and Walter Lancioni. "New Low-Voltage Electrically Tunable Triode-MOSFET Transconductor and its Application to Low-Frequency Gm-C Filtering." In 2005 18th Symposium on Integrated Circuits and Systems Design. IEEE, 2005. http://dx.doi.org/10.1109/sbcci.2005.4286858.

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