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Murty, Anjali. "Highly linear, rail-to-rail ICMR, low voltage CMOS operational amplifer." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/14884.
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Low, Aichen. "A floating-gate low dropout voltage regulator." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.
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Dong, Zhiwei. "Low-power, low-distortion constant transconductance Gm-C filters." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/25400.
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Zhong, Jian Yu. "Design of high-speed power-efficient SAR-type ADCs." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691882.
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Siddique, Nafiul Alam. "Spare Block Cache Architecture to Enable Low-Voltage Operation." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/216.
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Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.
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Padwal, Prachi Gulab. "Just-In-Time Power Gating of GasP Circuits." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/211.
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In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle. This method is called power gating. This thesis presents a state-preserving technique to achieve power savings in GasP family of asynchronous circuits by turning off the power when the circuit is idle. The power control logic turns on the power in anticipation of the receiving data. The power control logic turns off the power when the stage is idle either because it is empty or because the pipeline is clogged. The low logical effort of GasP circuits makes just-in-time power gating possible on a stage-by-stage basis. A new latch called Lazy Latch is introduced in this thesis. The lazy latch preserves its output and permits power gating of its larger transistors. The lazy latch is power efficient because it drives strongly only when necessary. A new latch called Blended Latch is proposed in this thesis which blends the advantages of the Conventional latches and the Lazy latches. Performance of power gating is evaluated by comparing the power-gated pipeline against the non-power gated pipeline. Power savings achieved are dependent on the duty cycle of operation. The fact that just-in-time power gating achieves power savings after it is idle for a minimum of 106 cycles makes it useful in limited applications where a quick start is required after long idle times.
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Lauterbach, Adam Peter. "Low-cost SiGe circuits for frequency synthesis in millimeter-wave devices." Australia : Macquarie University, 2010. http://hdl.handle.net/1959.14/76626.
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"2009"Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010.
Bibliography: p. 163-166.
Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion.
Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices.
Mode of access: World Wide Web.
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.
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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems.
The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Yang, Yun Ju 1980. "Impacto de técnicas de redução do consumo de energia no projeto de SoCs Multimedia." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275743.
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Orientador: Guido Costa Souza de AraújoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação
Made available in DSpace on 2018-08-19T00:08:02Z (GMT). No. of bitstreams: 1 Yang_YunJu_M.pdf: 3101962 bytes, checksum: 3711cbf9c4db60e5d2938d566db0d87c (MD5) Previous issue date: 2011
Resumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção correta de um sistema eletrônico de baixo consumo de energia é um problema de vários níveis de complexidade e exige estratégias sistemáticas na sua construção. Fora disso, a adoção de qualquer técnica de redução de energia sempre está vinculada com objetivos especiais e provoca alguns impactos no projeto. Apesar dos projetistas conheçam bem os impactos de forma qualitativa, as detalhes quantitativas ainda são incógnitas ou apenas mantidas dentro do 'know-how' das empresas. Neste trabalho, de acordo com resultados experimentais baseado num plataforma de SoC1 industrial, tentamos quantificar os impactos derivados do uso de técnicas de redução de consumo de energia. Nos concentramos em relacionar o fator de redução de energia de cada técnica aos impactos em termo de área, desempenho, esforço de implementação e verificação. Na ausência desse tipo de dados, que relacionam o esforço de engenharia com as metas de consumo de energia, incertezas e atrasos serão frequentes no cronograma de projeto. Esperamos que este tipo de orientações possam ajudar/guiar os arquitetos de projeto em selecionar as técnicas adequadas para reduzir o consumo de energia dentro do alcance de orçamento e cronograma de projeto
Abstract: The semiconductor industry has always faced strong demands to solve the problem of heat dissipation and reduce the power consumption in electronic devices. This trend has been increased in recent years with the action of environmental sustainability. The correct conception of an electronic system for low power consumption is an issue with multiple levels of complexities and requires systematic approaches in its construction. However, the adoption of any technique for reducing the power consumption is always linked with some specific goals and causes some impacts on the project. Although the designers know well that these impacts can affect the design in a quality aspect, the quantitative details are still unkown or just be kept inside the company's know-how. In this work, according to the experimental results based on an industrial SoC2 platform, we try to quantify the impacts of the use of low power techniques. We will relate the power reduction factor of each technique to the impact in terms of area, performance, implementation and verification effort. In the absence of such data, which relates the engineering effort to the goals of power consumption, uncertainties and delays are frequent. We hope that such guidelines can help/guide the project architects in selecting the appropriate techniques to reduce the power consumption within the limit of budget and project schedule
Mestrado
Ciência da Computação
Mestre em Ciência da Computação
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Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.
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Kim, Dongho. "Power estimation for combinational logic and low power design /." Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008367.
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Kanitkar, Hrishikesh. "Subthreshold circuits : design, implementation and application /." Online version of thesis, 2009. http://hdl.handle.net/1850/8926.
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Varanasi, Archana. "Course grained low power design flow using UPF /." Online version of thesis, 2009. http://hdl.handle.net/1850/11768.
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Palakurthi, Praveen Kumar. "Design of a low voltage analog to digital converter." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Kalargaris, Charalampos. "Design methodologies and tools for vertically integrated circuits." Thesis, University of Manchester, 2017. https://www.research.manchester.ac.uk/portal/en/theses/design-methodologies-and-tools-for-vertically-integrated-circuits(63c9c674-566a-44e5-b6b6-8a277b1adf08).html.
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Vertical integration technologies, such as three-dimensional integration and interposers, are technologies that support high integration densities while offering shorter interconnect lengths as compared to planar integration and other packaging technologies. To exploit these advantages, however, several challenges lay across the designing, manufacturing and testing stages of integrated systems. Considering the high complexity of modern microelectronic devices and the diverse features of vertical integration technologies, this thesis sheds light on the circuit design process. New methodologies and tools are offered in order to assess and improve traditional objectives in circuit design, such as performance, power, and area for vertically integrated circuits. Interconnects on different interposer materials are investigated, demonstrating the several trade-offs between power, performance, area, and crosstalk. A backend design flow is proposed to capture the performance and power gains from the introduction of the third dimension. Emphasis is also placed on the power consumption of modern circuits due to the immense growth of battery-operated devices in the last fifteen years. Therefore, the effect of scaling the operating voltage in three-dimensional circuits is investigated as it is one of the most efficient techniques for reducing power while considering the performance of the circuit. Furthermore, a solution to eliminate timing penalties from the usage of voltage scaling technique at finer circuits granularities is also presented in this thesis.
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Xu, Ping. "High-frequency Analog Voltage Converter Design." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4891.
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For many high-speed, high-performance circuits, purely differential inputs are needed. This project focuses on building high-speed voltage converters which can transfer a single-ended signal to a purely differential signal, or a differential input signal to a single-ended signal. Operational transconductance amplifier (OTAs) techniques are widely used in high-speed continuous-time integrated analog signal processing (ASP) circuits because resistors, inductors, integrators, buffers, multipliers and filters can be built by OT As and capacitors. Taking advantage of OT As, very-high-speed voltage converters are designed in CMOS technology. These converters can work in a frequency range from DC (OHz) up to lOOMHz and higher, and keep low distortion over a± 0.5V input range. They can replace transformers so that designing fully integrated differential circuits becomes possible. The designs are based on a MOSIS 2μm n-well process. SPICE simulations of these designs are given. The circuit was laid out with MAGIC layout tools and fabricated through MOSIS. The chip was measured at PSU and Intel circuit labs and the experimental results show the correctness of the designs.
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Jung, Moongon. "Low power and reliable design methodologies for 3D ICs." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51824.
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The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.
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Gao, Karen Ging. "Photoresist removal using low molecular weight alcohols and IPA-based solutions." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/11875.
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Amarchinta, Sumanth. "High performance subthreshold standard cell design and cell placement optimization /." Online version of thesis, 2009. http://hdl.handle.net/1850/10740.
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Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.
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Khasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors." Diss., Online access via UMI:, 2006.
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Wong, Wai Yu. "Supply-independent current-mode slew rate enhancement design /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202006%20WONG.
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Sen, Shreyas. "Design of process and environment adaptive ultra-low power wireless circuits and systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45755.
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The objective of the proposed research is to investigate the design of Self-Aware Radio Frequency Circuits and Wireless Communication Systems that can adapt to environmental and process variations to always operate at minimum power levels possible, extending battery life.
The explosive growth of portable battery operated devices has mandated design of low power circuits and systems to prolong battery life. These devices fabricated in modern nanoscale CMOS technologies suffer from severe process variation due to the reduced controllability of the fabrication process, causing yield loss. This calls for integrated low power and process tolerant design techniques, or design of systems that can adapt to its process and environment to maintain its performance while minimizing power consumption.
Currently, most of the wireless circuits are designed to meet minimum quality-of-service requirements under worst-case wireless link conditions (interference, noise, multi-path effects), leading to high power consumption when the channel is better than worst-case. In this research, we develop a multi-dimensional adaptation approach for wireless transmitters and receivers that optimally trades-off power vs. performance across temporally changing operating conditions by concurrently tuning control parameters in the RF front end to lower power consumption. Tunable circuits (e.g. LNA) with built-in tuning knobs providing independent controllability of important specifications allow optimal adaptation. Process sensing using intelligent test and calibration facilitates yield improvement and the design of process tolerant environment adaptive systems.
Low cost testing methodologies are developed for identification of the health of the wireless circuit/system. These are used in conjunction with tuning algorithms that tune a wireless system under process variation to meet performance specifications and recover yield loss. This testing and adaptation is performed once during the post manufacture test/tune phase to compensate for manufacturing variations. This can also be applied periodically during in field operation of a device to account for performance degradation due to ageing. Finally, process tolerant environment adaptive systems are designed.
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Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
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Li, Weiping. "Large-area, low-cost via formation and metallization in multilayer thin film interconnection on Printed Wiring Boards (PWB)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/19641.
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Bethel, Ryan H. "Low Voltage BiCMOS Circuit Topologies for the Design of a 19GHz, 1.2V, 4-Bit Accumulator in Silicon-Germanium." Fogler Library, University of Maine, 2007. http://www.library.umaine.edu/theses/pdf/BethelRH2007.pdf.
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Li, You. "Design of low-capacitance and high-speed electrostatic discharge (ESD) devices for low-voltage protection applications." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4551.
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Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of low-voltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures.; The recent industry data indicates the charged device model (CDM) ESD event becomes increasingly important in today's manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices' dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region.; Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysilicon-bound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode's design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode's overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers.; Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.ID: 029050342; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 92-100).
Ph.D.
Doctorate
Department of Electrical Engineering and Computer Science
Engineering and Computer Science
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Pham, Tien Ke. "Low-power, high-accuracy, and fast-tuning integrated continuous-time 450-KHz bandpass filter." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13525.
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Yoo, Seungyup. "Field effect transistor noise model analysis and low noise amplifier design for wireless data communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13024.
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Li, Lisha. "High Gain Low Power Operational Amplifier Design and Compensation Techniques." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1701.pdf.
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Severino, Raffaele Roberto. "Design methodology for millimeter wave integrated circuits : application to SiGe BiCMOS LNAs." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14284/document.
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Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur SiliciumThe interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver
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Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.
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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
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Srinivasan, Ganesh Parasuram. "Efficient Production Testing of High-Performance RF Modules and Systems using Low-Cost ATE." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14113.
Full textAbstract:
The proliferation of wireless communication devices in the recent past has increased the pressure on semiconductor manufacturers to produce quality radio frequency (RF) modules and systems at a low cost. This entails reducing their test cost as well, since the cost of testing modern RF devices can be up to 40% of their manufacturing cost. The high test cost of these devices can be mainly attributed to (a) the expensive nature of the RF automated test equipment (ATE) used to perform wafer-level and fully packaged RF functionality tests, (b) limited test point access for the application and capture of test signals, (c) the long test development and application times, and (d) the lack of diagnostic tools to evaluate and improve the performance of loadboards and test resources in high-volume tests.
In this thesis, a framework for the efficient production testing of high-performance RF modules and systems using low-cost ATE is presented. This framework uses low-speed, low-resolution test resources to generate reliable tests for complex RF systems. Also, the test resources will be evaluated and improved ahead of high-volume tests to improve test yield and throughput. The components of the proposed framework are:
(1) Genetic ATPG for reliable test stimulus generation using low-resolution test resources: A genetic algorithm (GA) based automatic test pattern generator (ATPG) to optimize the alternate test stimulus for reliable testing of complex RF systems using low-resolution, low-cost test resources. These test resources may be on-chip or off-chip.
(2) Concurrent voltage/current alternate test methodology: A testing framework for efficiently testing the high-frequency specifications of RF systems using low-frequency spectral and/or transient current signatures. Suitable on-chip and/or off-chip design-for-test (DfT) resources are used to enable the source and capture operations at lower frequencies.
(3) Loadboard checker: A checker tool to accurately characterize/diagnose the DfT resources on the RF loadboards used to enable test of RF devices/systems using low-cost ATE.
(4) Advanced test signal processing algorithms: The performance of the low-cost ATE resources, in terms of their linearity/resolution, will be evaluated and improved to enable the accurate capture of the test response signals.
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Alzahrani, Saeed A. "A Systematic Low Power, Wide Tuning Range, and Low Phase Noise mm-Wave VCO Design Methodology for 5G Applications." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1578037481545091.
Full text
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Mukherjee, Tamal. "Investigation of Post-Plasma Etch Fluorocarbon Residue Characterization, Removal and Plasma-Induced Low-K Damage for Advanced Interconnect Applications." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849649/.
Full textAbstract:
Modern three-dimensional integrated circuit design is rapidly evolving to more complex architecture. With continuous downscaling of devices, there is a pressing need for metrology tool development for rapid but efficient process and material characterization. In this dissertation work, application of a novel multiple internal reflection infrared spectroscopy metrology is discussed in various semiconductor fabrication process development. Firstly, chemical bonding structure of thin fluorocarbon polymer film deposited on patterned nanostructures was elucidated. Different functional groups were identified by specific derivatization reactions and model bonding configuration was proposed for the first time. In a continued effort, wet removal of these fluorocarbon polymer was investigated in presence of UV light. Mechanistic hypothesis for UV-assisted enhanced polymer cleaning efficiency was put forward supported by detailed theoretical consideration and experimental evidence. In another endeavor, plasma-induced damage to porous low-dielectric constant interlayer dielectric material was studied. Both qualitative and quantitative analyses of dielectric degradation in terms of increased silanol content and carbon depletion provided directions towards less aggressive plasma etch and strip process development. Infrared spectroscopy metrology was also utilized in surface functionalization evaluation of very thin organic films deposited by wet and dry chemistries. Palladium binding by surface amine groups was examined in plasma-polymerized amorphous hydrocarbon films and in self-assembled aminosilane thin films. Comparison of amine concentration under different deposition conditions guided effective process optimization. A time- and cost-effective method such as current FTIR metrology that provides in-depth chemical information about thin films, surfaces, interfaces and bulk layers can be increasingly valuable as critical dimensions continue to scale down and subtle process variances begin to have a significant impact on device performance.
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Mays, Kenneth W. "A 40 GHz Power Amplifier Using a Low Cost High Volume 0.15 um Optical Lithography pHEMT Process." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/552.
Full textAbstract:
The demand for higher frequency applications is largely driven by bandwidth. The evolution of circuits in the microwave and millimeter frequency ranges always demands higher performance and lower cost as the technology and specification requirements evolve. Thus the development of new processes addressing higher frequencies and bandwidth requirements is essential to the growth of any semiconductor company participating in these markets. There exist processes which can perform in the higher frequency design space from a technical perspective. However, a cost effective solution must complement the technical merits for deployment. Thus a new 0.15 um optical lithography pHEMT process was developed at TriQuint Semiconductor to address this market segment. A 40 GHz power amplifier has been designed to quantify and showcase the capabilities of this new process by leveraging the existing processing knowledge and the implementation of high frequency scalable models. The three stage power amplifier was designed using the TOM4 scalable depletion mode FET model. The TriQuint TQP15 Design Kit also implements microstrip transmission line models that can be used for evaluating the interconnect lines and matching networks. The process also features substrate vias and the thin film resistor and MIM capacitor models which utilize the capabilities of the BCB process flow. During the design stage we extensively used Agilent ADS program for circuit and EM simulation in order to optimize the final design. Special attention was paid to proper sizing of devices, developing matching circuits, optimizing transmission lines and power combining. The final design exhibits good performance in the 40 GHz range using the new TQP15 process. The measured results show a gain of greater than 13 dB under 3 volt drain voltage and a linear output power of greater than 28 dBm at 40 GHz. The 40 GHz power amplifier demonstrates that the new process has successfully leveraged an existing manufacturing infrastructure and has achieved repeatability, high volume manufacturing, and low cost in the millimeter frequency range.
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Morton, Matthew Allan. "Development of Monolithic SiGe and Packaged RF MEMS High-Linearity Five-bit High-Low Pass Phase Shifters for SoC X-band T/R Modules." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16190.
Full textAbstract:
A comprehensive study of the High-pass/Low-pass topology has been performed, increasing the understanding of error sources arising from bit layout issues and fabrication tolerances. This included a detailed analysis of error sources in monolithic microwave phase shifters due to device size limitations, inductor parasitics, loading effects, and non-ideal switches. Each component utilized in the implementation of a monolithic high-low pass phase shifter was analyzed, with its influence on phase behavior shown in detail. An emphasis was placed on the net impact on absolute phase variation, which is critical to the system performance of a phased array radar system. The design of the individual phase shifter filter sections, and the influence of bit ordering on overall performance was also addressed.
A variety of X-band four- and five-bit phase shifters were fabricated in a 200 GHz SiGe HBT BiCMOS technology platform, and further served to validate the analysis and design methodology. The SiGe phase shifter can be successfully incorporated into a single-chip T/R module forming a system-on-a-chip (SoC).
Reduction in the physical size of transmission lines was shown to be a possibility with spinel magnetic nanoparticle films. The signal transmission properties of phase lines treated with nanoparticle thin films were examined, showing the potential for significant size reduction in both delay line and High-pass/Low-pass phase topologies.
Wide-band, low-loss, and near-hermetic packaging techniques for RF MEMS devices were presented. A thermal compression bonding technique compatible with standard IC fabrication techniques was shown, that uses a low temperature thermal compression bonding method that avoids plastic deformations of the MEMS membrane.
Ultimately, a system-on-a-package (SoP) approach was demonstrated that utilized packaged RF MEMS switches to maintain the performance of the SiGe phase shifter with much lower loss. The extremely competitive performance of the MEMS-based High-pass/Low-pass phase shifter, despite the lack of the extensive toolkits and commercial fabrication facilities employed with the active-based SiGe phase shifters, confirms both the effectiveness of the detailed phase error analysis presented in this work and the robust nature of the High-pass/Low-pass topology.
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Liu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.
Full textAbstract:
Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (Vsubscript T) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (Vsubscript T]) shift and 25% to electron mobility (mu subscript n]) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation.ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
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Bidari, Emad. "Low-voltage switched-capacitor circuits." Thesis, 1998. http://hdl.handle.net/1957/33450.
Full textAbstract:
In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material presented in this thesis shows the drawback of these schemes while presenting three new methods for realizing low-voltage switched-capacitor integrators which are the key stages of ����� modulators and SC filters.
Using these integrators, several circuit realizations of SC filters and second order ����� modulators will be shown.Graduation date: 1999
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"Reticle floorplanning and voltage island partitioning." 2006. http://library.cuhk.edu.hk/record=b5892947.
Full textAbstract:
Ching Lap Sze.Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.
Includes bibliographical references (leaves 69-71).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Shuttle Mask --- p.2
Chapter 1.2 --- Voltage Island --- p.6
Chapter 1.3 --- Structure of the Thesis --- p.8
Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9
Chapter 2.1 --- Introduction --- p.9
Chapter 2.1.1 --- Problem formulation --- p.10
Chapter 2.2 --- Slicing Floorplan --- p.10
Chapter 2.3 --- General Floorplan --- p.11
Chapter 2.3.1 --- Conflict Graph Approaches --- p.11
Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14
Chapter 2.4 --- Grid Packing --- p.15
Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15
Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17
Chapter 3 --- Shuttle Mask Floorplanning --- p.18
Chapter 3.1 --- Problem Description --- p.18
Chapter 3.2 --- An Overview --- p.20
Chapter 3.3 --- Modified α-Restricted Grid --- p.21
Chapter 3.4 --- Branch and Bound Algorithm --- p.23
Chapter 3.4.1 --- Feasibility Check --- p.25
Chapter 3.5 --- Dicing Plan --- p.30
Chapter 3.6 --- Experimental Result --- p.30
Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36
Chapter 4.1 --- Introduction --- p.36
Chapter 4.1.1 --- Problem Definition --- p.36
Chapter 4.2 --- Dynamic Programming --- p.38
Chapter 4.2.1 --- Problem Definition --- p.38
Chapter 4.2.2 --- Algorithm Overview --- p.38
Chapter 4.2.3 --- Size Reduction --- p.39
Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40
Chapter 4.3 --- Quad-tree Approach --- p.41
Chapter 5 --- Voltage Island Partitioning --- p.44
Chapter 5.1 --- Introduction --- p.44
Chapter 5.2 --- Problem Formulation --- p.45
Chapter 5.3 --- Methodology --- p.46
Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47
Chapter 5.3.2 --- Tree Construction --- p.49
Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50
Chapter 5.3.4 --- Tree Refinement --- p.52
Chapter 5.3.5 --- Solution Legalization --- p.53
Chapter 5.3.6 --- Time Complexity --- p.54
Chapter 5.4 --- Direct Method --- p.55
Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56
Chapter 5.4.2 --- Time Complexity --- p.58
Chapter 5.5 --- Experimental Results --- p.59
Chapter 6 --- Conclusion --- p.66
Bibliography --- p.69
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"Design and implementation of fully integrated low-voltage low-noise CMOS VCO." 2002. http://library.cuhk.edu.hk/record=b5891102.
Full textAbstract:
Yip Kim-fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 95-100).
Abstracts in English and Chinese.
Abstract --- p.I
Acknowledgement --- p.III
Table of Contents --- p.IV
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Objective --- p.6
Chapter Chapter 2 --- Theory of Oscillators --- p.7
Chapter 2.1 --- Oscillator Design --- p.7
Chapter 2.1.1 --- Loop-Gain Method --- p.7
Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8
Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10
Chapter Chapter 3 --- Noise Analysis --- p.15
Chapter 3.1 --- Origin of Noise Sources --- p.16
Chapter 3.1.1 --- Flicker Noise --- p.16
Chapter 3.1.2 --- Thermal Noise --- p.17
Chapter 3.1.3 --- Noise Model of Varactor --- p.18
Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19
Chapter 3.2 --- Derivation of Resonator --- p.19
Chapter 3.3 --- Phase Noise Model --- p.22
Chapter 3.3.1 --- Leeson's Model --- p.23
Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24
Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26
Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31
Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33
Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33
Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35
Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37
Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39
Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42
Chapter 4.1 --- Device Modeling --- p.42
Chapter 4.1.1 --- FET model --- p.42
Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46
Chapter 4.1.3 --- Planar Inductor --- p.48
Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50
Chapter 4.1.5 --- Inductor Layout Consideration --- p.54
Chapter 4.1.6 --- CMOS RF Varactor --- p.55
Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57
Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59
Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59
Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59
Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61
Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62
Chapter 5.1.4 --- Output buffer --- p.63
Chapter 5.1.5 --- Biasing Circuitry --- p.64
Chapter 5.2 --- Spiral Inductor Design --- p.65
Chapter 5.3 --- Determination of W/L ratio of FET --- p.67
Chapter 5.4 --- Varactor Design --- p.68
Chapter 5.5 --- Layout (Cadence) --- p.69
Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74
Chapter Chapter 6 --- Experimental Results and Discussion --- p.76
Chapter 6.1 --- Measurement Setup --- p.76
Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81
Chapter 6.2.1 --- Output Spectrum --- p.81
Chapter 6.2.2 --- Phase Noise Performance --- p.82
Chapter 6.2.3 --- Tuning Characteristic --- p.83
Chapter 6.2.4 --- Microphotograph --- p.84
Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85
Chapter 6.3.1 --- Output Spectrum --- p.85
Chapter 6.3.2 --- Phase Noise Performance --- p.86
Chapter 6.3.3 --- Tuning Characteristic --- p.87
Chapter 6.3.4 --- Microphotograph --- p.88
Chapter 6.4 --- Comparison of Measured Results --- p.89
Chapter 6.4.1 --- Phase Noise Performance --- p.89
Chapter 6.4.2 --- Tuning Characteristic --- p.90
Chapter Chapter 7 --- Conclusion and Future Work --- p.93
Chapter 7.1 --- Conclusion --- p.93
Chapter 7.2 --- Future Work --- p.94
References --- p.95
Author's Publication --- p.100
Appendix A --- p.101
Appendix B --- p.104
Appendix C --- p.106
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Chang, Che-jen. "The low-power design of prefix adder." Thesis, 1997. http://hdl.handle.net/1957/33679.
Full textAbstract:
Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area.
In this thesis, the dynamic switching power consumption of ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, and prefix adder are discussed. The power factor, the sum of products of probability and fan-out of all internal nodes, is presented. This thesis also studies the power and time trade-off with efficiency index which is the product of power factor and worst case gate counts. The result shows that the carry look ahead adder has the lowest efficiency index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32 bit adder. The ripple carry adder is the best choice for an 8 bit adder.
This study also presents a low power prefix adder design which will reduce the power consumption of the prefix adder without lost of performance.Graduation date: 1998
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"Rewired retiming for flip-flop reduction and low power without delay penalty." 2009. http://library.cuhk.edu.hk/record=b5894017.
Full textAbstract:
Jiang, Mingqi.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.
Includes bibliographical references (leaves [49]-51).
Abstract also in Chinese.
Abstract --- p.i
Acknowledgement --- p.iii
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Rewiring Background --- p.4
Chapter 2.1 --- REWIRE --- p.6
Chapter 2.2 --- GBAW --- p.7
Chapter 3 --- Retiming --- p.9
Chapter 3.1 --- Min-Clock Period Retiming --- p.9
Chapter 3.2 --- Min-Area Retiming --- p.17
Chapter 3.3 --- Retiming for Low Power --- p.18
Chapter 3.4 --- Retiming with Interconnect Delay --- p.22
Chapter 4 --- Rewired Retiming for Flip-flop Reduction --- p.26
Chapter 4.1 --- Motivation and Problem Formulation --- p.26
Chapter 4.2 --- Retiming Indication --- p.29
Chapter 4.3 --- Target Wire Selection --- p.31
Chapter 4.4 --- Incremental Placement Update --- p.33
Chapter 4.5 --- Optimization Flow --- p.36
Chapter 4.6 --- Experimental Results --- p.38
Chapter 5 --- Power Analysis for Rewired Retiming --- p.41
Chapter 5.1 --- Power Model --- p.41
Chapter 5.2 --- Experimental Results --- p.44
Chapter 6 --- Conclusion --- p.47
Bibliography --- p.50
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"Voltage island-driven floorplanning." 2008. http://library.cuhk.edu.hk/record=b5893629.
Full textAbstract:
Ma, Qiang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.
Includes bibliographical references (leaves 78-80).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Background --- p.1
Chapter 1.2 --- Floorplanning --- p.2
Chapter 1.3 --- Motivations --- p.4
Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5
Chapter 1.5 --- Problem Formulation --- p.8
Chapter 1.6 --- Progress on the Problem --- p.10
Chapter 1.7 --- Contributions --- p.12
Chapter 1.8 --- Thesis Organization --- p.14
Chapter 2 --- Literature Review on MSV --- p.15
Chapter 2.1 --- Introduction --- p.15
Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16
Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16
Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18
Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19
Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20
Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21
Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22
Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22
Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23
Chapter 2.4 --- Summary --- p.27
Chapter 3 --- MSV Driven Floorplanning --- p.29
Chapter 3.1 --- Introduction --- p.29
Chapter 3.2 --- Problem Formulation --- p.32
Chapter 3.3 --- Algorithm Overview --- p.33
Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33
Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35
Chapter 3.4.2 --- Proof of Optimality --- p.36
Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37
Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38
Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39
Chapter 3.5 --- Simulated Annealing --- p.39
Chapter 3.5.1 --- Moves --- p.39
Chapter 3.5.2 --- Cost Function --- p.40
Chapter 3.6 --- Experimental Results --- p.40
Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45
Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46
Chapter 3.7 --- Summary --- p.46
Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49
Chapter 4.1 --- Introduction --- p.49
Chapter 4.2 --- Problem Formulation --- p.52
Chapter 4.3 --- Algorithm Overview --- p.56
Chapter 4.4 --- Voltage Assignment Problem --- p.56
Chapter 4.4.1 --- Lagrangian Relaxation --- p.58
Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60
Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64
Chapter 4.4.4 --- Solution Transformation --- p.66
Chapter 4.5 --- Simulated Annealing --- p.69
Chapter 4.5.1 --- Moves --- p.69
Chapter 4.5.2 --- Speeding up heuristic --- p.69
Chapter 4.5.3 --- Cost Function --- p.70
Chapter 4.5.4 --- Annealing Schedule --- p.71
Chapter 4.6 --- Experimental Results --- p.71
Chapter 4.7 --- Summary --- p.72
Chapter 5 --- Conclusion --- p.76
Bibliography --- p.80
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Mohammad, Baker Shehadah. "Cache design for low power and yield enhancement." 2008. http://hdl.handle.net/2152/17884.
Full textAbstract:
One of the major limiters to computer systems and systems on chip (SOC) designs is accessing the main memory, which is typically two orders of magnitude slower than the processor. To bridge this gap, modern processors already devote more than half of the on-chip transistors to the last-level cache. Caches have negative impact on area, power, and yield. This research goal is to design caches that operate at lower voltages while enhancing yield. Our strategy is to improve the static noise margin (SNM) and the writability of the conventional six-transistor SRAM cell by reducing the effect of parametric variations on the cell. This is done using a novel circuit that reduces the voltage swing on the word line during read operations and reduces the memory supply voltage during write operations. The proposed circuit increases the SRAM’s SNM and write margin using a single voltage supply that has minimal impacts on chip area, complexity, and timing. A test chip with an 8-kilobyte SRAM block manufactured in 45- nm technology is used to verify the practicality of the contribution and demonstrate the effectiveness of the new circuit’s implementation. Cache organization is one of the most important factors that affect cache design complexity, performance, area, and power. The main architectural choice for caches is whether to implement the tag array using a standard SRAM or using a content addressable memory (CAM). The choice made has far-reaching consequences on several aspects of the cache design, and in particular on power consumption. Our contribution in this area is an in-depth study of the complex tradeoffs of area, timing, power, and design complexity between an SRAM-based tag and a CAM-based one. Our results indicate that an SRAM-based tag design often provides a better overall design point and is superior with respect to energy, especially for interleaved multi-threading processors. Being able to test and screen chips is a key factor in achieving high yield. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, since caches are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The third contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design.text
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Van, Rhyn Pierre. "Probabilistic low voltage distribution network design for aggregated light industrial loads." Thesis, 2015. http://hdl.handle.net/10210/13361.
Full textAbstract:
D.Ing.This thesis initially reviews current empirical and probabilistic electrical load models available to distribution design engineers today to calculate voltage regulation levels in low voltage residential, commercial and light industrial consumer networks. Although both empirical and probabilistic techniques have extensively been used for residential consumers in recent years, it has been concluded that commercial and light industrial consumer loads have not been a focus area of probabilistic load study for purposes of low voltage feeder design. However, traditional empirical techniques, which include adjustments for diversity to accommodate non-coincidental electrical loading conditions, have generally been found to be applied using in-house design directives with only a few international publications attempting to address the problem. This work defines the light industrial group of consumers in accordance with its international Standard Industrial Classification (SIC) and presents case studies on a small group of three different types of light industrial sub-classes, It is proposed and proved that the electrical load models can satisfactorily be described as beta-distributed load current models at the instant of group or individual maximum power demand on typical characteristic 24-hour load cycles. Characteristic mean load profiles were obtained by recording repetitive daily loading of different sub-classes, ensuring adequate sample size at all times. Probabilistic modelling of light industrial loads using beta-distributed load current at maximum demand is a new innovation in the modelling of light industrial loads. This work is further -complemented by the development of a new probabilistic summation algorithm in spreadsheet format. This algorithm adds any selected number of characteristic load current profiles, adjusted for scale, power factor, and load current imbalance, and identifies the combined instant of group or system maximum demand. This spreadsheet also calculates the characteristic beta pdf parameters per phase describing the spread and profile of the combined system loading at maximum demand. These parameters are then conveniently used as input values to existing probabilistic voltage regulation algorithms to calculate voltage regulation in single-, bi- and three-phase low voltage distribution networks.
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"Development of low-power high-accuracy ultrafast-transient-response low-dropout regulators for battery-powered applications." 2013. http://library.cuhk.edu.hk/record=b5884387.
Full textAbstract:
Ho, Marco.Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
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"Low-power circuit design using adiabatic and asynchronous techniques." 2005. http://library.cuhk.edu.hk/record=b5892423.
Full textAbstract:
So Pui Tak.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.
Includes bibliographical references.
Abstracts in English and Chinese.
Abstract --- p.ii
Acknowledgement --- p.v
Table of Contents --- p.vi
List of Figures --- p.ix
List of Tables --- p.xii
Chapter Chapter 1 --- Introduction --- p.11
Chapter 1.1 --- Overview --- p.1-1
Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1
Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6
Chapter 1.4 --- Objectives --- p.1-7
Chapter 1.5 --- Thesis Outline --- p.1-8
Chapter Chapter 2 --- Background Theory --- p.2-1
Chapter 2.1 --- Introduction --- p.2-1
Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1
Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3
Chapter 2.4 --- Asynchro nous Circuits --- p.2-7
Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1
Chapter 3.1 --- Introduction --- p.3-1
Chapter 3.2 --- Architecture --- p.3-2
Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4
Chapter 3.4 --- Circuit Evaluation --- p.3-7
Chapter 3.5 --- Simulation Results --- p.3-8
Chapter 3.4 --- Experimental Results --- p.3-9
Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1
Chapter 4.1 --- Introduction --- p.4-1
Chapter 4.2 --- Architecture --- p.4-1
Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2
Chapter 4.2.2 --- Delay Block Design --- p.4-4
Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1
Chapter 5.1 --- Introduction --- p.5-1
Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1
Chapter 5.3 --- Oscillator Block Design --- p.5-3
Chapter 5.4 --- Multiplier Architecture --- p.5-6
Chapter Chapter 6 --- Layout Consideration --- p.6-1
Chapter 6.1 --- Introduction --- p.6-1
Chapter 6.2 --- Floorplanning --- p.6-1
Chapter 6.3 --- Routing Channels --- p.6-2
Chapter 6.3 --- Power Supply --- p.6-4
Chapter 6.4 --- Input Protection Circuitry --- p.6-5
Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7
Chapter Chapter 7 --- Simulation Results --- p.7-1
Chapter 7.1 --- Introduction --- p.7-1
Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1
Chapter 7.3 --- Power Consumption --- p.7-6
Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6
Chapter 7.3.2 --- AAT Multiplier --- p.7-7
Chapter 7.3.3 --- Power Comparison --- p.7-8
Chapter Chapter 8 --- Measurement Results --- p.8-1
Chapter 8.1 --- Introduction --- p.8-1
Chapter 8.2 --- Experimental Setup --- p.8-2
Chapter 8.3 --- Measurement Results --- p.8-6
Chapter Chapter 9 --- Conclusion --- p.9-1
Chapter 9.1 --- Contributions --- p.9-1
Chapter Chapter 10 --- Bibliography --- p.10-1
Appendix I Building Blocks --- p.1
Appendix II Simulated Waveform --- p.7
Appendix III Measured Waveform --- p.8
Appendix IV Pin List --- p.9
49
"Low power design in layout and system level." 2010. http://library.cuhk.edu.hk/record=b5894272.
Full textAbstract:
Qian, Zaichen.Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references (leaves 62-67).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- VLSI Design Methodology --- p.1
Chapter 1.2 --- Low Power Design --- p.6
Chapter 1.3 --- Literature Review on Multiple Supply Voltage (MSV) --- p.10
Chapter 1.3.1 --- Voltage Island Partitioning Problems --- p.11
Chapter 1.3.2 --- Multiple Voltage Assignment (MVA) Problem --- p.12
Chapter 1.4 --- Literature Review on Dynamic Voltage Scaling and Dynamic Power Management --- p.15
Chapter 1.4.1 --- Dynamic Voltage Scaling (DVS) Problem --- p.16
Chapter 1.4.2 --- Dynamic Power Management --- p.20
Chapter 1.5 --- Thesis Contribution and Organization --- p.22
Chapter 2 --- Multi-Voltage Floorplan Design --- p.24
Chapter 2.1 --- Introduction --- p.24
Chapter 2.2 --- Problem Formulation --- p.26
Chapter 2.3 --- A Value-Oriented Branch-and-Bound Algorithm --- p.29
Chapter 2.3.1 --- Branching Rules --- p.30
Chapter 2.3.2 --- Upper Bounds --- p.31
Chapter 2.3.3 --- Lower Bounds --- p.32
Chapter 2.3.4 --- Pruning Rules and Value-Oriented Searching Rules --- p.33
Chapter 2.4 --- Floorplanning --- p.35
Chapter 2.5 --- Experimental Results --- p.36
Chapter 2.5.1 --- Optimal Voltage Assignment --- p.37
Chapter 2.5.2 --- Floorplanning Results --- p.38
Chapter 3 --- Low Power Scheduling at System Level --- p.40
Chapter 3.1 --- Introduction --- p.40
Chapter 3.2 --- Problem Formulation --- p.42
Chapter 3.3 --- An Optimal Offline Algorithm --- p.43
Chapter 3.4 --- Online Algorithm --- p.46
Chapter 3.4.1 --- Analysis on One Single Interval --- p.46
Chapter 3.4.2 --- Online Algorithm --- p.49
Chapter 3.4.3 --- Analysis of the Online Algorithm --- p.52
Chapter 3.5 --- Experimental Results --- p.56
Chapter 4 --- Conclusion and Future Work --- p.60
Bibliography --- p.67
50
"High performance ultra-low voltage continuous-time delta-sigma modulators." Thesis, 2011. http://library.cuhk.edu.hk/record=b6075115.
Full textAbstract:
Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply.Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply.
In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise.
The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions.
The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C.
Chen, Yan.
Adviser: Kong Pang Pun.
Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (leaves 127-135).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.