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Richelli, Anna. "Low-Voltage Integrated Circuits Design and Application." Electronics 10, no. 1 (January 5, 2021): 89. http://dx.doi.org/10.3390/electronics10010089.
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One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...]
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Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (August 28, 2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.
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AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.
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Serdijn, Wouter A., Albert C. Van Der Woerd, Arthur H. M. Van Roermund, and Jan Davidse. "Design principles for low-voltage low-power analog integrated circuits." Analog Integrated Circuits and Signal Processing 8, no. 1 (July 1995): 115–20. http://dx.doi.org/10.1007/bf01239382.
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Manku, T., G. Beck, and E. J. Shin. "A low-voltage design technique for RF integrated circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 10 (1998): 1408–13. http://dx.doi.org/10.1109/82.728853.
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Lee, Min Chin, Ming Chia Hsieh, and Chi Jing Hu. "Implementation and Design of High PSRR Low Dropout Regulator." Advanced Materials Research 614-615 (December 2012): 1553–57. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1553.
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As the progress with all kinds of mixed-mode signal circuits, the requirements of power management become increasingly stringent. Therefore it takes all kinds of high-performance linear regulator to produce a very clean and stable voltage. Here cascading technique is used to increase the output impedance in this architecture. The output voltage is less susceptible to variation of input voltage, resulting in a clean and stable voltage which is used the operating voltage of internal circuits in a mixed-mode signal integrated circuit chip. This paper using the TSMC 0.35μm CMOS 2P4M process to implement the design of high PSRR LDO regulator, having chip area, 1.34 mW consumption power. The chip supply voltage can from 2.9V to 3.3V with -106dB and -65dB PSRR at 1KHz and 100KHz, and its output voltage can stable at 1.2V and less than 2.4mV ripple voltage at maximum loading current 20 mA.
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Tarim, T. B., M. Ismail, and H. H. Kuntman. "Robust design and yield enhancement of low-voltage CMOS analog integrated circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48, no. 4 (April 2001): 475–86. http://dx.doi.org/10.1109/81.917984.
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HUNG, YU-CHERNG, SHAO-HUI SHIEH, and CHIOU-KOU TUNG. "A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 89–105. http://dx.doi.org/10.1142/s0218126611007104.
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Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.
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ALLSTOT, DAVID J., SANKARAN ANIRUDDHAN, MIN CHU, JEYANANDH PARAMESH, and SUDIP SHEKHAR. "RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 377–428. http://dx.doi.org/10.1142/s0129156405003247.
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Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides comparatively higher gain and lower noise figure. Aside from the traditional passive and active Gilbert mixers, the even-harmonic and masking-quadrature mixers are developed to combat second-order non-linearity and improve image-rejection, respectively. For quadrature carrier generation, the degeneration-injected QVCO is superior to the cascode-injected QVCO both in terms of phase noise and tuning range. The Colpitts QVCO is attractive as a low-noise alternative as it does not disturb the output voltage as much as its traditional LC counterpart and thus offers lower phase noise.
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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.
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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.
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Petrosyants, Konstantin O., Igor A. Kharitonov, and Nikita I. Ryabov. "Electro-Thermal Design of Smart Power Devices and Integrated Circuits." Advanced Materials Research 918 (April 2014): 191–94. http://dx.doi.org/10.4028/www.scientific.net/amr.918.191.
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An efficient methodology of electro-thermal design of smart power semiconductor devices and ICs, based on the combined use of SPICE circuit analysis tool and software tools for 2D/3D thermal simulation of IC chip construction, is presented. The features of low, medium and high power elements, temperature sensors, IC chips simulation are considered.
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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (December 2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.
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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.
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Zhang, Xiao Feng, Fo Chang Xie, Guo Wei Yang, and Wei Zhang. "The Transceiver Circuit Design of Digital Ultrasonic System." Advanced Materials Research 834-836 (October 2013): 968–73. http://dx.doi.org/10.4028/www.scientific.net/amr.834-836.968.
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This paper introduces the design process of the digital ultrasonic transmission circuit: echo receiving circuit and the echo signal regulate circuit. Among them, outside 500 V DC - DC module for high voltage power input, use non-tuned type circuit design ultrasonic transmission circuit ; Select high voltage fast recovery diode FR107 design echo receiving limiter circuit; Using ultra-high speed, low noise, low distortion of the integrated operational amplifier MAX4104ESA design preamplifier circuits and the band-pass filter circuits; Using linear decibels, low noise, wide bandwidth, high gain accuracy amplifier AD603 design echo amplifying circuit. The experimental results indicate that the basic realization of the ultrasonic transceiver circuit and echo signal conditioning functions.
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Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.
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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.
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SAPONARA, SERGIO, TOMMASO BALDETTI, LUCA FANUCCI, EMILIO VOLPI, and FRANCESCO D'ASCOLI. "DESIGN OF AN INTEGRATED SCANNING MICROMIRROR DRIVER IN BCD TECHNOLOGY." Journal of Circuits, Systems and Computers 20, no. 04 (June 2011): 781–99. http://dx.doi.org/10.1142/s0218126611007608.
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The paper presents the design and characterization of a smart IC driver for MEMS scanning micromirrors. The driver integrates in 0.18 μm BCD technology the cascade of the following circuits: resistor-string DAC circuitry for direct interface to a host digital processing unit, a voltage buffer between the DAC and the High-Voltage (HV) stage, and a fully-differential HV amplifier with programmable output common mode. A couple of the designed DACs permits to generate, starting from digital samples, low-voltage analog stimuli. This signal amplified up to 25 V by the HV stage provides the electrostatical actuation of the micromirror. When compared to state-of-the-art the driver offers an integrated solution with good dynamic performances.
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LEHMANN, TORSTEN, HOSUNG CHUN, and YUANYUAN YANG. "POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS." Journal of Circuits, Systems and Computers 21, no. 06 (October 2012): 1240016. http://dx.doi.org/10.1142/s0218126612400166.
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Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.
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Samaali, Hatem, Fehmi Najar, Bouraoui Ouni, and Slim Choura. "MEMS SPDT microswitch with low actuation voltage for RF applications." Microelectronics International 32, no. 2 (May 5, 2015): 55–62. http://dx.doi.org/10.1108/mi-12-2014-0055.
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Purpose – This paper aims to propose a novel design of an ohmic contact single-pole double-throw (SPDT) microelectromechanical system (MEMS) microswitch for radio frequency applications. Design/methodology/approach – The proposed microswitch (SPDT design) shares antenna between transmitter and receiver in a wireless sensor. An electrical voltage is used to create an electrostatic force that controls the ON/OFF states of the microswitch. First, the authors develop a mathematical model of the proposed microswitch and propose a reduced-order model of the design, based on the differential quadrature method, which fully incorporates the electrostatic force nonlinearities. The authors solve the static, transient and dynamic behavior and compare the results with finite element solutions. Then, the authors examine the dynamic solution of the switch under different actuation waveforms. Findings – The obtained results showed a significant reduction in actuation voltage, pull-in bandwidth and switching time. Originality/value – In this paper, a new design of SPDT MEMS switch is proposed, the SPDT switch needs low voltage to be actuated and it can be easily integrated with integrated circuits.
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Gierczak, Miroslaw Gracjan, Jacek Wróblewski, and Andrzej Dziedzic. "The design and fabrication of electromagnetic microgenerator with integrated rectifying circuits." Microelectronics International 34, no. 3 (August 7, 2017): 131–39. http://dx.doi.org/10.1108/mi-02-2017-0010.
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Purpose The paper focuses on design, fabrication and characterization of electromagnetic microgenerators with integrated rectifying circuits to convert AC output signal to DC one. The work includes research on simulation of voltage-rectifying circuits, including charge pump, realization of the experimental printed circuit board (PCB) with selected electronic circuits and the execution of the final structure with integrated rectifying circuit. Measurements were performed on these circuits. Design/methodology/approach Electromagnetic microgenerators include multipole permanent magnets secured on rotor three-phase brushless direct current (BLDC) motor and planar multilayer multiple coils. These were fabricated using low temperature co-fired ceramics (LTCC) technology. In our experiment, six rectifying circuits were simulated and tested with a structure consisting of eight layers of coils and with an outer diameter of 50 mm fabricated earlier. Findings The microgenerator with Graetz bridge generates higher output power than the modified charge pump at the same rotary speed. However, it is less stable for the distance change between the structure and the magnets than the modified charge pump, which has more constant output power in a wider range of load resistance. Originality/value The presented electronic rectifying circuits are novel for LTCC-based electromagnetic microgenerator application. The structure with integrated rectifying circuits allows generation of electrical output power larger than 100 mW at the rotor speed of about 8,000 rpm.
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Caselli, Michele, Marco Ronchi, and Andrea Boni. "Power Management Circuits for Low-Power RF Energy Harvesters." Journal of Low Power Electronics and Applications 10, no. 3 (September 19, 2020): 29. http://dx.doi.org/10.3390/jlpea10030029.
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The paper describes the design and implementation of power management circuits for RF energy harvesters suitable for integration in wireless sensor nodes. In particular, we report the power management circuits used to provide the voltage supply of an integrated temperature sensor with analog-to-digital converter. A DC-DC boost converter is used to transfer efficiently the energy harvested from a generic radio-frequency rectifier into a charge reservoir, whereas a linear regulator scales the voltage supply to a suitable value for a sensing and conversion circuit. Implemented in a 65 nm CMOS technology, the power management system achieves a measured overall efficiency of 20%, with an available power of 4.5 μW at the DC-DC converter input. The system can sustain a temperature measurement rate of one sample/s with an RF input power of −28 dBm, making it compatible with the power levels available in generic outdoor environments.
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Benvenuti, Lorenzo, Alessandro Catania, Giuseppe Manfredini, Andrea Ria, Massimo Piotto, and Paolo Bruschi. "Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs." Electronics 10, no. 10 (May 13, 2021): 1156. http://dx.doi.org/10.3390/electronics10101156.
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The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.
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Mahmoudi, Parisa, Ashkan Mahmoudi, and Esmaeil Najafiaghdam. "A Design of Thermo-Electrostatic Actuated Microelectromechanical Switch with Low Voltage and Fabrication Efforts." Advanced Materials Research 403-408 (November 2011): 3791–96. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.3791.
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Requirement of voltage up-converters due to high pull-in voltage is one of the main problems by merely electrostatic actuated Microelectromechanical system-based switches. Thermally actuated switches are another alternatives but with very high power dissipation. In this paper a low voltage switch is demonstrated, which uses a combined thermo-electrostatic actuator. The switch can be integrated with standard CMOS circuits without any up-converters. Thermally power dissipation for the switch is lower than just thermal actuators. The switching time is about 70µs and the maximal temperature of thermal actuator is lower than 150oC which cannot cause any longtime damage. Isolation and Insertion Loss quantities have been calculated to -25dB and -0.65dB at 20GHz from HFSS results respectively.
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Ohme, Bruce W., Mark R. Larson, Bhal Tulpule, and Alireza Behbahani. "Characterization of Circuit Blocks for Configurable Analog-Front-End." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000146–53. http://dx.doi.org/10.4071/hitec-wa13.
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Analog functions have been implemented in a Silicon-on-Insulator (SOI) process optimized for high-temperature (>225°C) operation. These include a linear regulator/reference block that supports input voltages up to 50V and provides multiple independent voltage outputs. Additional blocks provide configurable sensor excitation levels of up to 10V DC and/or 20V AC-differential, with current limiting and monitoring. A dual-channel Programmable-Gain-Instrumentation Amplifier (PGIA) and a high-level AC input block with programmable gain and offset serve signal conditioning, gain, and scaling needs. A multiplexer and analog buffer provide an output that is scaled and centered for down-stream A-to-D conversion. Limited component availability and high component counts deter development of sensing and control electronics for extreme temperature (>200°) applications. Systems require front-end power conditioning, sensor excitation and monitoring, response amplification, scaling, and multiplexing. Back-end Analog-to-Digital conversion and digital processing/control can be implemented using one or two integrated circuit chips, whereas the front-end functions require component counts in the dozens. The low level of integration in the available portfolio of SOI devices results in high component count when constructing signal conditioning interfaces for aerospace sensors. These include quasi-DC sensors such as thermo-couples, strain-gauges, bridge transducers as well as AC-coupled sensors and position transducers, such as Linear Variable Differential Transducers (LVDT's). Furthermore, a majority of sensor applications are best served by excitation/response voltage ranges that typically exceed the voltage range of digital electronics (either 5V or 3.3V in currently available digital IC's for use above 200°C). These constraints led Embedded Systems LLC to design a generic device which was implemented by Honeywell as an analog ASIC (Application Specific Integrated Circuit). This paper will describe the ASIC block-level capabilities in the context of the typical applications and present characterization data from wafer-level testing at the target temperature range (225C). This material is based upon work performed by Honeywell International under a subcontract from Embedded Systems LLC, funding for which was provided by the U.S. Air Force Small Business Innovative Research program.
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Kompitaya, Pantre, and Khanittha Kaewdang. "An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter." Journal of Circuits, Systems and Computers 25, no. 06 (March 31, 2016): 1650066. http://dx.doi.org/10.1142/s0218126616500663.
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A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.
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Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (May 3, 2019): 496. http://dx.doi.org/10.3390/electronics8050496.
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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.
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D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (August 17, 2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.
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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.
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Li, Zhiqun, Yan Yao, Zengqi Wang, Guoxiao Cheng, and Lei Luo. "A Low-Voltage Multi-Band ZigBee Transceiver." Electronics 8, no. 12 (December 4, 2019): 1474. http://dx.doi.org/10.3390/electronics8121474.
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This paper presents a low-voltage ZigBee transceiver covering a unique frequency band of 780/868/915/2400 MHz in 180 nm CMOS technology. The design consists of a receiver with a wideband variable-gain front end and a complex band-pass filter (CBPF) based on poles construction, a transmitter employing the two-point direct-modulation structure, a Ʃ-Δ fractional-N frequency synthesizer with two VCOs and some auxiliary circuits. The measured results show that under 1 V supply voltage, the receiver reaches −93.8 dBm and −102 dBm sensitivity for 2.4 GHz and sub-GHz band, respectively, and dissipates only 1.42 mW power. The frequency synthesizer achieves −106.8 dBc/Hz and −116.7 dBc/Hz phase noise at 1 MHz frequency offset along with 4.2 mW and 3.5 mW power consumption for 2.4 GHz and sub-GHz band, respectively. The transmitter features 2.67 dBm and 12.65 dBm maximum output power at the expense of 21.2 mW and 69.5 mW power for 2.4 GHz and sub-GHz band, respectively.
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Han, Yifeng, Mingjing Zhai, and Junfeng Zhou. "A thermal protection module for automotive integrated circuits." Modern Physics Letters B 31, no. 19-21 (July 27, 2017): 1740097. http://dx.doi.org/10.1142/s0217984917400978.
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Automotive ICs work in wide ambient temperature range up to 150[Formula: see text]C. It is important to design an over temperature protection mechanism for the reliability of ICs and systems. A thermal protection module for the automotive ICs is reported in this paper. Dual channel detection and decision scheme was designed based on band gap voltage reference. Precision thermal protection point was set by serial resistors and the variations of power supply, temperature and the process were removed by the resistor ratio. The thermal protection module was implemented in CSMC 0.5 [Formula: see text] 60 V BCD process, incorporated in a CAN transceiver chip. The area of the module was about 0.02 mm2 and thus it was very compact and low cost to integrate in chips. The performance of the thermal protection parameters was measured in incubators. The thermal shutdown temperature was about 164.4[Formula: see text]C and the thermal recovery temperature was about 153[Formula: see text]C with hysteresis temperature of 10 K. Additionally, the thermal protection module showed good consistency with different chips.
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Myderrizi, Indrit, and Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology." Journal of Circuits, Systems and Computers 26, no. 11 (April 17, 2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.
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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.
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Sarker, Mahidur R., Azah Mohamed, and Ramizi Mohamed. "Modelling and Simulation an AC-DC Rectifier Circuit Based on Piezoelectric Vibration Sensor for Energy Harvesting System." Applied Mechanics and Materials 785 (August 2015): 131–35. http://dx.doi.org/10.4028/www.scientific.net/amm.785.131.
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This paper presents the modeling of a full-wave rectifier circuit based on piezoelectric vibration transducer for energy-harvester system. Piezoelectric vibration crystals are a viable means of harvesting energy for low-power embedded systems e.g. wireless sensor network. Distinct power handling circuits are assessed with the presence of piezoelectric vibration based energy harvesting transducer. Inside the interface circuit, the voltage should be started up when the AC input voltage is very low to supply a regulated DC voltage up to 2V. An active technique is chosen to design an ultra-low power circuit from a piezoelectric vibration transducer. MOSFET bride ac–dc rectifier, energy storage device e.g. capacitor and boost converter with regulator are the common components of the energy harvesting circuits. An integrated promoter ac-dc rectifier circuit and boost converter that accept a maximum input voltage of 0.3V and provide a regulated output voltage of 2V serve as the supply. The MOSFET and thyristor are considered to develop the proposed circuit replacing conventional ac-dc rectifier due to low input voltage at which diode does not work.
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Dvornikov, Oleg, Vladimir Tchekhovski, Valentin Dziatlau, Nikolay Prokopenko, and Nikolay Butyrlagin. "Design of low-temperature DDOAs on the elements of BiJFet array chip MH2XA030." Serbian Journal of Electrical Engineering 15, no. 2 (2018): 233–47. http://dx.doi.org/10.2298/sjee1802233d.
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Brief information about the new BiJFet array chip (AC) MH2XA030 intended for accelerated creation of analog integrated circuits (IC), which retain their performance under the influence of penetrating radiation and extremely low temperatures (up to minus 197??) is presented. The features of schematic design of two types of DDOAs (OAmp3, OAmp4) are considered. The recommendations on the schematic design of the DDOA are developed taking into account the static characteristics of the field effect and bipolar transistors of the AC under the influence of low temperatures. The amplitude-frequency response of the DDOA and the dependence of the noise voltage on the frequency of Fourier density are given. At a temperature of -197?? cryogenic amplifiers OAmp3 (OAmp4) are characterized by the following parameters: the current consumption is less than 500 ?A, the input current is less than 1 fA, the voltage gain is more than 50.000 (200.000), the offset voltage is less than 200 (60) ?V. The results of the circuit simulation of the instrumentation amplifier based on DDOA OAmp3 are presented.
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Aiello, Orazio. "Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference." Journal of Low Power Electronics and Applications 11, no. 1 (January 20, 2021): 6. http://dx.doi.org/10.3390/jlpea11010006.
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The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.
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Sankar, P. A. Gowri, and G. Sathiyabama. "A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application." International Journal of Engineering Research in Africa 19 (October 2015): 19–36. http://dx.doi.org/10.4028/www.scientific.net/jera.19.19.
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The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.
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Ahlgren, D. C., S. J. Jeng, D. Nguyen-Ngoc, K. Stein, D. Sunderland, M. Gilbert, J. Malinowski, et al. "Si-Ge heterojunction bipolar technology for high-speed integrated circuits." Canadian Journal of Physics 74, S1 (December 1, 1996): 159–66. http://dx.doi.org/10.1139/p96-851.
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This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.
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Kledrowetz, Vilem, Roman Prokop, Lukas Fujcik, Michal Pavlik, and Jiří Háze. "Low-power ASIC suitable for miniaturized wireless EMG systems." Journal of Electrical Engineering 70, no. 5 (September 1, 2019): 393–99. http://dx.doi.org/10.2478/jee-2019-0071.
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Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.
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Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.
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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outputs, and a single-input and single-output adjustable current amplifier. These cells (sub-blocks of the manufactured IC device), designed to operate in a bandwidth of up to tens of MHz, can be used as a construction set for building a variety of advanced active elements, offering up to four independently adjustable internal parameters. The performances of all individual cells were verified by extensive laboratory measurements, and the obtained results were compared to simulations in the Cadence IC6 tool. The definition and assembly of a newly specified advanced active element, namely a current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA), is shown as an example of modular interconnection of the selected cells. This device was implemented in a newly synthesized topology of an electronically linearly tunable quadrature oscillator. Features of this active element were verified by simulations and experimental measurements.
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YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.
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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.
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ZHANG, YAJING, WENGAO LU, GUANNAN WANG, ZHONGJIAN CHEN, and YACONG ZHANG. "A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340015. http://dx.doi.org/10.1142/s021812661340015x.
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A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.
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Zhang, Qing, Nikola Pekas, and David Juncker. "Design and Fabrication of Novel Compliant Electrostatically Actuated Microvalves." Advanced Materials Research 74 (June 2009): 179–82. http://dx.doi.org/10.4028/www.scientific.net/amr.74.179.
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Electrostatically actuated microvalves are appealing candidates to build fully integrated microfluidic circuits because of the direct transduction of electrical signals into mechanical responses at low power consumption levels. Practical solutions, however, are still lacking due to their multi-layered architecture and difficulties in incorporating heterogeneous materials. In this paper, we report the design and fabrication process of an electrostatically actuated gas microvalve amenable to large scale integration for gas flow control. The device we designed consists of an upper die, containing a flexible electrode sealed by a thin elastic membrane, and a lower die, containing gas channels of trapezoidal cross-section and fixed electrodes. Each microvalve is defined by one fixed electrode spanning the floor and sidewalls of the trapezoidal gas channel and one corresponding flexible electrode suspended above the channel. In contrast to the conventional parallel-plate arrangement of electrodes, the two electrodes are approximated starting from the edges of the trapezoidal gas channel during the actuation step, which is advantageous for lowering the required actuation voltage. The upper die was fabricated by replica molding in polymeric material, the lower die was fabricated in a glass substrate by conventional microfabrication techniques, and the two dies were subsequently aligned and bonded using an adhesive layer. This reported low cost fabrication process could be implemented in any basic microfabrication facility. When a net pressure up to 1 bar was applied to the gas channel, reasonable flow rate was achieved. We also observed displacement of the flexible membrane when a DC voltage of 200 V was applied to a pair of electrodes. These preliminary results show that this microvalve is a promising candidate for integrated on-chip valving and will allow for building large scale microfluidic circuits with reduced power consumption.
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HUANG, WEN-TZENG, SUN-YEN TAN, and YUAN-JEN CHANG. "A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE." Journal of Circuits, Systems and Computers 19, no. 06 (October 2010): 1275–97. http://dx.doi.org/10.1142/s0218126610006670.
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Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.
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Lee, Minwoong, Seongik Cho, Namho Lee, and Jongyeol Kim. "New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis." Electronics 9, no. 3 (February 26, 2020): 388. http://dx.doi.org/10.3390/electronics9030388.
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A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.
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SHAN, WEIWEI, YAN LIANG, and DONGMING JIN. "CMOS CIRCUIT DESIGN OF A TAKAGI-SUGENO FUZZY LOGIC CONTROLLER." Journal of Circuits, Systems and Computers 18, no. 04 (June 2009): 841–56. http://dx.doi.org/10.1142/s0218126609005009.
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This paper presents a low power CMOS analog integrated circuit of a Takagi–Sugeno fuzzy logic controller with voltage/voltage interface, small chip area, relatively high accuracy and medium speed, which is composed of several improved functional blocks. Z-shaped, Gaussian and S-shaped membership function circuits with compact structures are designed, performing well with low power, high speed and small areas. A current minimization circuit is provided with high accuracy and high speed. A follower-aggregation defuzzification block composed of several multipliers for center of gravity (COG) defuzzification is presented without using a division circuit. Based on these blocks, a two-input one-output singleton fuzzy controller with nine rules is designed under a CMOS 0.6 μm standard technology provided by CSMC. HSPICE simulation results show that this controller reaches an accuracy of ±3% with power consumption of only 3.5 mW (at ±2.5 V). The speed of this controller goes up to 0.625M Fuzzy Logic Inference per Second (FLIPS), which is fast enough for real-time control.
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Andreou, Charalambos M., Diego Miguel González-Castaño, Simone Gerardin, Marta Bagatin, Faustino Gómez Rodriguez, Alessandro Paccagnella, Alexander V. Prokofiev, et al. "Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions." Electronics 8, no. 5 (May 21, 2019): 562. http://dx.doi.org/10.3390/electronics8050562.
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The radiation tolerance of subthreshold reference circuits for space microelectronics is presented. The assessment is supported by measured results of total ionization dose and single event transient radiation-induced effects under γ -rays, X-rays, protons and heavy ions (silicon, krypton and xenon). A high total irradiation dose with different radiation sources was used to evaluate the proposed topologies for a wide range of applications operating in harsh environments similar to the space environment. The proposed custom designed integrated circuits (IC) circuits utilize only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any external components such as compensation capacitors. The circuits are radiation hardened by design (RHBD) and they were fabricated using TowerJazz Semiconductor’s 0.18 μm standard CMOS technology. The proposed voltage references are shown to be suitable for high-precision and low-power space applications. It is demonstrated that radiation hardened microelectronics operating in subthreshold regime are promising candidates for significantly reducing the size and cost of space missions due to reduced energy requirements.
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Ono, Ronald H. "Thin Film Processing of Complex Multilayer Structures of High-Temperature Superconductors." MRS Bulletin 17, no. 8 (August 1992): 34–38. http://dx.doi.org/10.1557/s088376940004183x.
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The realization of a revolutionary generation of electronics based on high-temperature superconductors (HTS) crucially depends on the ability to make high-quality thin film microstructures. These will incorporate materials such as YBa2Cu3O7-δ (YBCO), TlBaCaCuO, or BiSrCaCuO in a fashion similar to the circuits and devices made of their low Tc counterparts Nb or NbN. Without exception, the most valuable structures will be composed of multiple layers of superconducting films and dielectrics, in some cases combined with normal metals, low-temperature superconductors, or a variety of semiconductors. Generically, these can be combined in two ways: in a hybrid design where specialized packages and bonding are used to attach dissimilar materials, or in a monolithic thin film structure such as the one seen in Figure 1.The division between hybrid and monolithic multilayers results from the historical development of electronic circuits. Hybrid designs typically require linewidths and alignment accuracy somewhat less demanding than those used in fully integrated circuits. The advantage of hybrid construction is the separation of incompatible processing steps onto different substrates or die. The monolithic integrated circuit, whether microelectronic, millimeter wave, or radio frequency, can be made in large batches with concomitant economy of scale and can be fabricated with fewer parasitic constraints. Superconducting integrated circuits have followed the semiconductor pattern of being developed in a hybrid fashion, then transferred to a fully integrated process.
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Galante-Sempere, David, Dailos Ramos-Valido, Sunil Lalchand Khemchandani, and Javier del Pino. "Low-Power RFED Wake-Up Receiver Design for Low-Cost Wireless Sensor Network Applications." Sensors 20, no. 22 (November 10, 2020): 6406. http://dx.doi.org/10.3390/s20226406.
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The development of wake-up receivers (WuR) has recently received a lot of interest from both academia and industry researchers, primarily because of their major impact on the improvement of the performance of wireless sensor networks (WSNs). In this paper, we present the development of three different radiofrequency envelope detection (RFED) based WuRs operating at the 868 MHz industrial, scientific and medical (ISM) band. These circuits can find application in densely populated WSNs, which are fundamental components of Internet-of-Things (IoT) or Internet-of-Everything (IoE) applications. The aim of this work is to provide circuits with high integrability and a low cost-per-node, so as to facilitate the implementation of sensor nodes in low-cost IoT applications. In order to demonstrate the feasibility of implementing a WuR with commercially available off-chip components, the design of an RFED WuR in a PCB mount is presented. The circuit is validated in a real scenario by testing the WuR in a system with a pattern recognizer (AS3933), an MCU (MSP430G2553 from TI), a transceiver (CC1101 from TI) and a T/R switch (ADG918). The WuR has no active components and features a sensitivity of about −50 dBm, with a total size of 22.5 × 51.8 mm2. To facilitate the integration of the WuR in compact systems and low-cost applications, two designs in a commercial UMC 65 nm CMOS process are also explored. Firstly, an RFED WuR with integrated transformer providing a passive voltage gain of 18 dB is demonstrated. The circuit achieves a sensitivity as low as −62 dBm and a power consumption of only 528 nW, with a total area of 634 × 391 μm2. Secondly, so as to reduce the area of the circuit, a design of a tuned-RF WuR with integrated current-reuse active inductor is presented. In this case, the WuR features a sensitivity of −55 dBm with a power consumption of 43.5 μW and a total area of 272 × 464 μm2, obtaining a significant area reduction at the expense of higher power consumption. The alternatives presented show a very low die footprint with a performance in line with most of the state-of-the-art contributions, making the topologies attractive in scenarios where high integrability and low cost-per-node are necessary.
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Zhang, Chuang, Chang-Ling Zou, Yan Zhao, Chun-Hua Dong, Cong Wei, Hanlin Wang, Yunqi Liu, Guang-Can Guo, Jiannian Yao, and Yong Sheng Zhao. "Organic printed photonics: From microring lasers to integrated circuits." Science Advances 1, no. 8 (September 2015): e1500257. http://dx.doi.org/10.1126/sciadv.1500257.
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A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.
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Kawauchi, Hayato, and Toru Tanzawa. "A Fully Integrated Clocked AC-DC Charge Pump for Mignetostrictive Vibration Energy Harvesting." Electronics 9, no. 12 (December 18, 2020): 2194. http://dx.doi.org/10.3390/electronics9122194.
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This paper describes a clocked AC-DC charge pump to enable full integration of power converters into a sensor or radio frequency (RF) chip even with low open circuit voltage magnetostrictive vibration energy transducer operating at a low resonant frequency of 10 Hz to 1 kHz. The frequency of the clock to drive an AC-DC charge pump was up-converted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. A model of the system including the charge pump and vibration energy transducer is shown. It was validated by HSPICE simulation and measured, resulting in a prototype chip with an area of 0.11 mm2 fabricated in a 65 nm 1 V CMOS process. The fabricated charge pump was also measured together with a magnetostrictive transducer. The charge pump converted the power from the transducer to an output power of 4.2 μW at an output voltage of 2.0 V. The output power varied below 3% over a wide input frequency of 10 Hz to 100 kHz, which suggests that universal design of the clocked AC-DC charge pump can be used for transducers with different resonant frequencies. In a low-input voltage region below 0.8 V, the proposed circuit has higher output power compared with the conventional circuits.
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Al-Khateeb, Khalid A. S., and Wajdi F. Al-Khateeb. "DESIGN AND PERFORMANCE ANALYSIS OF VCO FOR STANDARD GSM USING MEMS." IIUM Engineering Journal 11, no. 1 (May 26, 2010): 41–49. http://dx.doi.org/10.31436/iiumej.v11i1.40.
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The design of a prototype monolithic Micro Electro-Mechanical Systems (MEMS) electronic circuits, namely the Voltage Controlled Oscillators (VCOs) is presented. The components can achieve the stringent requirements of wireless communication applications such as GSM cellular telephony. The VCO meets the low phase noise specifications of -136 dBc/Hz at large offset frequency of 3MHz, over the appropriate frequency range. The model of the monolithic VCO is based on the topology of the Colpitts Oscillator. It is relatively less complicated, which facilitates the practical integration of the MEMS components into the configuration. The variable capacitor and the monolithic 3-D coil inductor are suitable for low phase-noise and low power consumption at the application frequencies. A PSpice simulation model was developed with MEMS switching devices that can be integrated into the system. The model helps in determining the design parameters, which affect the performance and operation reliability of the RF transceiver system, for which a prototype has been tested and proved successful.
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NIRANJAN, VANDANA, ASHWANI KUMAR, and SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
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In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.
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Calazans, Ney Laert Vilar, Taciano Ares Rodolfo, and Marcos L. L. Sartori. "Robust and Energy-Efficient Hardware: The Case for Asynchronous Design." Journal of Integrated Circuits and Systems 16, no. 2 (August 19, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.518.
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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades, but their costs are increasingly hard to cope with. Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes. This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process variations; (3) temperature variations; (4) circuit aging. Besides addressing energy-efficiency and all the mentioned robustness aspects, this work also approaches some of the state-of-the-art tools available to deal with asynchronous design, and points to desirable research development to be conducted in these subjects in the future.
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McCue, B. M., R. L. Greenwell, M. I. Laurence, B. J. Blalock, S. K. Islam, and L. M. Tolbert. "SOI Based Voltage Regulator for High-Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000207–13. http://dx.doi.org/10.4071/hitec-2012-wp12.
Full textAbstract:
Developments in automotive (particularly hybrid-electric vehicles), aerospace, and energy production industries have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature silicon-on-insulator (SOI) process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various supply voltages and load currents. These supply voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuits is generated on chip via a voltage regulator producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator has been developed to meet the demands of a gate driver IC. The voltage regulator must be able to provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −25°C to 200°C, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation resulting in lower operating junction temperature. The designed voltage regulator has been successfully tested from −50°C to 200°C while demonstrating an output voltage variation of less than 10 mV under the full range of input voltage. Additionally, line regulation tests from 10 V to 30 V show a 12-ppm/V supply sensitivity. Full temperature and input voltage range tests reveal that the no-load supply current draw is within 17 mA while still providing in excess of 200-mA load current upon demand. Modifications to the existing design or off-chip biasing can widen the range of attainable output voltages and drive capabilities.
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Li, Li, and Ji Jun Zhang. "Analysis the Interface of Amplifier in GPON System by PSpice." Applied Mechanics and Materials 44-47 (December 2010): 3833–38. http://dx.doi.org/10.4028/www.scientific.net/amm.44-47.3833.
Full textAbstract:
Model help to understand the system there may be a signal reflection and impedance matching problem. Most fiber integrated circuits from Maxim use Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS) I/O formats. Language can be set up through the PSpice circuit model of the IC, with an ideal voltage controlled current source of alternative sources and active circuit elements. And the use of spice macro-model simulation to test the circuit performance of the chip interface design. In this paper, it takes the model of amplifier IC in GPON receiver front-end for example to shows the steps and importance of interface simulation in GPON system by PSpice macro-model.