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Dissertations / Theses on the topic 'Ltnps'

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Published: 4 June 2021
Last updated: 5 February 2022

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1

van, Bockel David John Clinical School St Vincent's Hospital Faculty of Medicine UNSW. "Qualitative analysis of T-cell repertoire for relevance to non-progressive HIV infection." Publisher:University of New South Wales. Clinical School - St Vincent's Hospital, 2008. http://handle.unsw.edu.au/1959.4/41304.

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Cytotoxic T-lymphocytes are important for the control of viral replication during HIV infection, however the magnitude and breadth of HIV-specific CD8+ T-cell response does not correlate well. The purpose for this study was the examination of the HLA-B*2705-specific CD8+ T-cell response to the KRWIILGLNK (KK10) epitope as a definitive model of immune control over HIV replication. The breadth of the T-cell receptor (TCR) repertoire was determined for an association between the qualitative nature of this response and immune escape and therefore, disease progression. Methodology was developed and validated for TCR repertoire analysis in formaldehyde fixed antigen-specific CD8+ T-cells. The TCR repertoire for the KK10-specific CD8+ T-cell response was defined in cross-section and longitudinally for 6 HLA-B*2705+ patients. Comparison was made to cognate HLA-A*0201 CMV NV9 and HLA-B*2705 EBV RL9-specific CD8+ T-cell populations using the Simpson??s diversity index and the Morisita-Horn similarity index for standardized repertoire analysis. HLA-B*2705 KK10-specific TCR repertoire was not found to be a determinant of control. Greater clonotype variation was found within CMV-specific CD8+ T-cell populations, suggesting an association with reactivation of CMV and disease state. An association was found between KK10-specific population diversity and the prevalence of cognate KK10 epitope in vivo. Cross-reactivity observed for dominant KK10-specific clonotypes suggested that avidity of CD8+ T-cells was important for in vivo survival. Phenotype and function was tested through multiparameter analysis of HIV and CMV-specific CD8+ T-cells. Increased frequency of CD127 (IL-7R) and Bcl-2 expression within dominant populations was suggestive of selective advantage. Division of dominant and sub-dominant CMV-specific CD8+ T-cell populations into ??early?? and ??late?? differentiation phenotypes indicated virus-specific mechanisms of clonotype turn over. No simple association of TCR expression was found for HIV and CMV-specific CD8+ T-cells with published examples of definitive TCR bias. Over-represented TCR ??-chain families of patients were found in association with public clonotypes. Convergent recombination of TCR genes was demonstrated as a mechanism for the prevalence of shared clonotypes. Standardized assessment of T-cell repertoire successfully identified mechanisms of antigen-specific CD8+ T-cell recruitment. A substantial increase in sample numbers is required before this methodology can be used to accurately demonstrate the importance of TCR repertoire usage in the control of human viral infection.
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2

Lucas, Karen Rae, and karen lucas@rmit edu au. "The Effects of Latent Myofascial Trigger Points on Muscle Activation Patterns During Scapular Plane Elevation." RMIT University. Health Sciences, 2007. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20080408.144402.

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Despite a paucity of experimental evidence, clinical opinion remains that though LTrPs allow pain-free movement, they are primarily associated with deleterious motor effects and occur commonly in 'healthy' muscles. The primary aim of this study was to investigate the effects of LTrPs on the muscle activation patterns (MAPs) of key shoulder girdle muscles during scapular plane elevation of the arm in the unloaded, loaded and fatigued states. In connection with the main aim, a preliminary study was carried out to examine the frequency with which LTrPs occur in the scapular positioning muscles in a group of normal subjects. After establishing intra-examiner reliability for the clinical examination process, 154 healthy subjects volunteered to be screened for normal shoulder girdle function, then undergo a physical examination for LTrPs in the trapezius, rhomboids, levator scapulae, serratus anterior and the pectoralis minor muscles bilaterally. Of these 'healthy' subjects, 89.8% had at least one LTrP in the scapular positioning muscles (mean=10.65 ± 6.8, range=1-27), with serratus anterior and upper trapezius harbouring the most LTrPs on average (2.46 ± 1.8 and 2.36 ± 1.3 respectively). Consistent with clinical opinion, this study found that LTrPs occur commonly in the scapular positioning muscles. To investigate the motor effects of LTrPs, surface electromyography (sEMG) was used to measure the timing of muscle activation of the upper and lower trapezius and serratus anterior (upward scapular rotators), the infraspinatus (rotator cuff) and middle deltoid (arm abductor). These studies found that LTrPs housed in the scapular upward rotator muscles affected the timing of activation and increased the variability of the activation times of this muscle group and were also associated with altered timing of activation in the functionally related but LTrP-free infraspinatus and middle deltoid. Compared with the control group (all muscles LTrP-free), the MAPs of the LTrP group appeared to be sub-optimal, particularly in relation to preserving the subacromial space and the loading of the rotator cuff muscles. After the initial sEMG evaluations, the LTrP subjects were randomly assigned to one of two interventions: superficial dry needling (SDN) followed by post-isometric relaxation (PIR) stretching to remove LTrP s or sham ultrasound, to act as a placebo treatment where LTrPs remained. Where LTrPs were removed, a subsequent sEMG evaluation found MAPs to be similar to the control group in most of the experimental conditions investigated. Of particular note, when LTrPs had been treated and the subjects repeated the fatiguing protocol, the resultant MAP showed no significant difference with that of the control group in the rested state, suggesting treating LTrPs was associated with an improved response to fatigue induced by repetitive overhead movements. In conclusion, the findings indicate that LTrPs commonly occur in scapular positioning muscles and have deleterious effects on MAPs employed to perform scapular plane elevation and thus affect motor control mechanisms. Treating LTrPs with SDN and PIR stretching increases pressure-pain thresholds, removes associated taut bands and at least transiently optimises the MAP during scapular plane elevation. Discussion includes possible neuromuscular pathophysiology that might explain these results.
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3

Saharinen, Juha. "Interactions of small latent transforming growth factor-betas with their binding proteins, LTBPs." Helsinki : University of Helsinki, 2000. http://ethesis.helsinki.fi/julkaisut/laa/haart/vk/saharinen/.

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4

Kumari, Khushbu [Verfasser], and Dirk [Gutachter] Becker. "The role of lipid transfer proteins (LTPs) during the fertilization process in Arabidopsis thaliana / Khushbu Kumari ; Gutachter: Dirk Becker." Würzburg : Universität Würzburg, 2021. http://d-nb.info/1226669492/34.

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5

Sá, Júnior Euridson de. "Mercado secundário de títulos públicos: microestrutura, liquidez e spread de compra e venda para o mercado de LTNs no Brasil." reponame:Repositório Institucional do FGV, 2007. http://hdl.handle.net/10438/1773.

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This work comprises two parts. First part, it discusses and compares liquidity and market microstructure aspects from government securities in some countries as Brazil, Chile, Mexico, Korea, Poland and United States. The analyses uses some microstructure dimensions like the liquidity from secondary market (bid and ask spread, turnover to average outstanding stock and most important maturity), the efficiency costs, infrastructure and transparency from primary and secondary market and the market security. The goal is to describe the microstructure of secondary markets from theses countries and to compare with the microstructure of Brazilian secondary markets. Despite of low tenor from government securities the Brazilian secondary market presents microstructure like those countries that suggested other reasons avoiding enlarge tenors from prefixed securities. The second part of this work examines the liquidity of the local secondary market for the Brazilian government securities between 2003 to 2006 and the determinants of realized bid-ask spreads for secondary market of the LTNs – Letras do Tesouro Nacional between 2005 to 2006. The spreads were calculated from daily basis with high frequency database for 30 minutes period and one-day period. Overall, the liquidity is an important determinant of the realized bid-ask spread for the LTN market. Specifically, the bid-ask spread decreases when the volume increases. The bid-ask spread increases in the remaining-time-to-maturity of LTN. LTNs up to 30 days tenor presented average bid-ask spreads around 1 cents of reais (1.89 bp) and LTNs with two years tenor presented average bid-ask spreads around 54 cents of reais (3.84 bp) for 30 minutes period and 81 cents of reais (5.72 bp) for one day period. The econometric tests were performed based on a model presented by Chakravarty e Sarkar (1999) applied to USA bonds markets for the years 1995 to 1997. The tests were estimated by Generalized Method of Moments (GMM) technique. Our estimation and evaluation of liquidity measures for the Brazilian government securities market reveal that the simple bid-ask spread is a useful measure for assessing and tracking liquidity.
Este trabalho está dividido em dois ensaios. O primeiro ensaio examina aspectos da liquidez do mercado secundário de títulos públicos no Brasil no período 2003 a 2006 e os determinantes do spread de compra e venda no mercado secundário de LTN - Letra do Tesouro Nacional no período 2005 a 2006. Os spreads foram calculados com base em dados diários de alta freqüência, para períodos de 30 minutos e de um dia. Em linhas gerais, a liquidez é um determinante importante no cálculo do spread. Especificamente os spreads diminuem quando os volumes ofertados aumentam. No caso dos prazos de vencimento, os spreads aumentam quando os prazos se ampliam. LTNs com prazos de vencimentos até 30 dias apresentaram spreads de 1 centavo de reais (1.89 bp) enquanto que LTNs com prazos acima de dois anos apresentaram spreads médios em torno de 54 centavos de reais (3.84 bp) para intervalos de 30 minutos e 81 centavos de reais (5.72 bp) para intervalos de um dia. Os testes econométricos foram realizados com base em um modelo apresentado por Chakravarty e Sarkar (1999) e aplicado ao mercado americano de bonds no período de 1995 e 1997. Os testes foram feitos utilizando-se a técnica do Método dos Momentos Generalizados (GMM). Os resultados confirmam o spread de compra e venda como medida importante no acompanhamento da liquidez. O segundo ensaio compara aspectos da liquidez e da microestrutura do mercado de títulos públicos em alguns paises como Brasil, Chile, México, Coréia, Singapura, Polônia e Estados Unidos. A análise utiliza algumas dimensões da microestrutura como a liquidez do mercado secundário (spread de compra e venda, giro do estoque de títulos e vencimentos mais negociados), os custos de eficiência, a estrutura e transparência do mercado primário e secundário e, por último, a segurança do mercado. O objetivo é comparar as características e o funcionamento dos mercados secundários desses paises e, confrontar com a realidade do mercado brasileiro face ao desenvolvimento da microestrutura. Apesar da falta de alongamento dos prazos dos títulos públicos, o mercado secundário no Brasil apresenta aspectos da microestrutura semelhantes aos paises em consideração o que sugere a existência de outros fatores fora a microestrutura que limitam o aumento dos prazos. Os resultados do primeiro ensaio ajudam nas comparações dos demais paises. Como resultado, encontramos que embora a liquidez do mercado secundário de títulos públicos no Brasil concentra-se em papéis de prazo menor, este fato provavelmente não se deve a questões de microestrutura do mercado.
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6

Valcke, Han Sang. "Étude du dysfonctionnement du compartiment des cellules B chez des patients à différents stades d’infection par le virus d’immunodéficience humaine (VIH)." Thèse, 2009. http://hdl.handle.net/1866/3556.

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Les anomalies phénotypiques et fonctionnelles des lymphocytes B (LB) sont typiques d'une infection au VIH et se traduisent principalement par une activation polyclonale, une perte de la mémoire immunitaire ainsi qu'une réponse humorale déficiente et des phénomènes auto-immunitaires souvent précurseurs de lymphomes B. Ces anomalies se retrouvent principalement chez les patients lors de la phase chronique de la maladie et semblent être reliées en partie au niveau de la charge virale ainsi qu'à un compartiment de lymphocytes T CD4+ altéré. Cependant, quoique controversé, des éléments d’activation polyclonale ont également été observés chez les non-progresseurs à long terme (LTNPs) qui présentent une charge virale faible et un compartiment T CD4+ semblable aux individus séronégatifs. Ainsi, les objectifs principaux de cette étude sont 1) d’établir une chronologie des anomalies du compartiment des cellules B chez des individus infectés par le VIH qui ont une progression différente de la maladie (PHI normaux, rapides, sains et LTNP). 2) corréler les niveaux sériques du stimulateur de lymphocytes B (BLyS), un facteur de croissance des cellules B, avec les phénotypes observés chez ces mêmes patients. L’hyperglobulinémie, les niveaux sériques de BLyS et d’auto-anticorps ont été mesuré longitudinalement chez une cohorte d’individus en primo-infection (PHI) avec des progressions différentes de la maladie (rapides et normaux), LTNP et sujets sains. Nos résultats démontrent que l’activation polyclonale des LB survient indépendamment de la vitesse de progression et persiste chez les LTNP ou malgré une thérapie antirétrovirale efficace chez les progresseurs rapides. Des niveaux élevés de BLyS dans le sérum des progresseurs rapides corrèlent avec des fréquences altérées de monocytes et cellules dendritiques, suggérant un rôle de celles-ci dans l’atteinte du compartiment des cellules B.
B lymphocyte abnormalities are an important consequence of HIV infection, where both polyclonal activation and loss of B cell memory and humoral immunity have been described, and often evolve towards rheumatic-like autoimmunity and lymphoma. Although these abnormalities are prevalent in chronically infected patients, polyclonal B cell activation is also reported in patients with primary HIV-infection (PHI), who already present signs of defective humoral immunity. Although controversial, elements of B cell dysregulation have been reported in long term non progressor (LTNP) patients, even though they bear low viral loads and present a relatively "normal" CD4+ T cell compartment, suggesting that other factors are involved. Therefore, the main objectives of this study are to 1) establish a timeline for specific B cell abnormalities in HIV-infected patients with different rates of disease progression (PHI normal and fast progressors, LTNP), and controls 2) to correlate serum levels of the B lymphocyte stimulator (BLyS) a B cell growth factor, among these patients and controls. Thus we have longitudinally assessed hyperglobulinemia, auto-antibody and soluble BLyS levels in the serum of subjects undergoing primary HIV infection (PHI) with different rates of disease progression; rapid and normal progressors, long term non-progressors (LTNPs), and healthy donors. Here, we report that B cell polyclonal activation occurs independently of the rate of disease progression, with hypergammaglobulinemia persisting beyond successful therapy in rapid progressors and despite non-progressing clinical disease in LTNPs. High levels of BLyS in the serum of PHI rapid progressors correlate with altered blood monocyte and dendritic cell frequencies suggesting their contribution in triggering B cell dysregulations.
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7

Tu, Wei-Chen, and 涂維珍. "Improvement of LTPS Photo Detector." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/49134402070105154794.

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碩士
國立清華大學
電子工程研究所
95
Novel LTPS PIN photo detectors with low dark current and high sensitivity have been developed. Dual gate insulator including TEOS and SiNx layer are employed to enhance hydrogen level which can effectively repair defects in the poly-Si thin film and in turn reduces dark current level in the PIN device. To increase photo responsibility, structural layer on top of the photo-detector is designed to reduce light loss. A hollow region is etched and filled with ITO to enhance light penetration to the depletion region. Bias voltage added to the ITO electrode is demonstrated to increase the depletion region of the device, which lead to better photo responsibility. By the above methods, we successfully develop a high performance PIN diode.
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8

Ho, Meng Hsiu, and 何孟修. "LTPS TFTs Etching process improvement analysis." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/x65uw4.

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9

Wu, Shi-Min, and 吳細閔. "Readout circuit for LTPS TFT capacitive fingerprint sensor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/64658028702668125226.

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碩士
國立暨南國際大學
電機工程學系
93
Abstract In recent years, the need for user authentication on personal portable information products to guarantee the security of use becomes an emergent demand. Fingerprint can offer a convenience and reliable way to replace traditional password or personal identification number. A capacitive fingerprint sensor acquires the fingerprint image by detecting capacitance changes induced by fingerprint surface. It can also easily combine with semiconductor process to achieve small volume and low cost. In this thesis, we will present a readout circuit for capacitive fingerprint sensor array fabricated by low temperature poly-silicon (LTPS) process. By using the TSMC 0.35μm Mixed-Signal 2P4M CMOS process provided by Chip Implementation Center, two readout circuit for 4×4 pixels and 30×30 pixels of two-dimensional array have been designed. The CMOS readout circuit chip and the LTPS capacitive sensor array chip are wire-bonded together on a printed circuit board for system integration and testing. The designed chips work at a single 5V power supply and a 2MHz clock. The sensor array can detect the capacitance range from 0fF to 600fF.
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10

Lin, Zsung-Chun, and 林宗儁. "A Study of LTPS TFTs Degradation Under Dynamic Stress." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93157925025020861206.

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碩士
國立清華大學
電子工程研究所
101
In the last few years Low temperature polycrystalline silicon thin-film transistors, due to it's excellent device characteristics has been widely used in small-to-medium display panel. Recent years, Low temperature polycrystalline silicon thin-film transistors with high carrier mobilities allows for the realization of complementary circuit technology. As device miniaturized, panel aperture ratio, power consumption, the quality and resolution can be further improved. Integrating the driving circuits on the glass, so that the panel also has a narrow frame with higher imaging characteristics. Therefore, low-temperature polycrystalline silicon becomes the mainstream technology for small-to-medium size displays. The reliability of the panel between the performance of the system panel, peripheral drive circuit is critical to the LTPS technology , Long-term operation in the environment of high voltage or high current ,can greatly affected the transistor’s stability. As the size of transistor is shrinking , devices will experience ever more severe hot carrier effects (Hot Carrier Effect), self-heating effects (Self-Heating Effect) leading to even worse reliability. This study investigates the degradation behavior of the low temperature polycrystalline silicon thin-film transistors when operate in AC pulse signal. Devices stressed under different temperature, frequency, Duty cycle resulting in different deteriorating characteristics are discussed and analyzed comprehensively.
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11

Lee, Te-Yu, and 李淂裕. "Design and Analysis of LTPS TFTs for SOP Applications." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/51932636803143667463.

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博士
國立清華大學
電子工程研究所
102
Currently, LTPS TFTs are the most important display technology of mobile devices. Owing to the superior device characteristics, active-matrix driven LTPS TFT displays offer high brightness, high efficiency, wide viewing angle and high contrast ratio. Fast response time for moving images, ultra-thin module, low-power consumption, and low fabrication cost further fulfill the needs of portable electronics. However, LTPS TFT technology still faces many challenges in realizing the ideal display in mobile applications such as high resolution, integrated circuitry and flexible display. In this dissertation, reliability challenges of LTPS TFT technology for state-of-art mobile applications are investigated. For the high resolution liquid crystal displays, the average off-state leakage current of LTPS TFTs can be effectively suppressed by grain protrusion assisted localized FN operation. Under the increasing backlight system, asymmetric shielding gates as well as surround gate structure are proven to alleviate the drain turn-on effect caused by these floating bottom gates. For SOP applications, fully LTPS panel process compatible MNOS OTP cell with three-order read current difference, fast program efficiency, good data retention characteristics and high disturb immunity is demonstrated. For the high resolution AMOLED displays, efficient blanket boosting scheme is successfully applied to a 2.4-inch 2T1C AMOLED panel with illumination non-uniformity improving from 8.1% to 4.9%. This highly efficient trimming method can achieve uniform drive current without any additional compensation circuitry or external memory and fully compatible to current LTPS backplane for AMOLED display.
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12

WANG, SIAO-SHIN, and 王曉詩. "Investigation on Testing Parameters Optimum for LTPS TFT-LCD." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/39626741470208554762.

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碩士
國立臺灣科技大學
電子工程系
95
In this dissertation, the major purpose of this paper is to find out the bester parameter of LTPS panel. From the formula, Cs=Qcs/Vcs, Qcs=I*T, and Vcs=(I*T)/Cs. Find out the current and the time affect the change of voltage. So we design the different voltage and time for the Cs. Experiment on the change voltage, in order to make the parameter will be right, that LTPS panel must be working normal. So the range of the voltage on this experiment, different times affect the display of the colors. If the voltage too high or too low either the time too long or too short, that the result will be not correct. In this dissertation, using the electricity to test the panel by the tester system is better than the optics, and extracts the parameter more correct and quicker. So we test panel by the electricity tester system to get the best parameter.
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13

Liu, Yu-Min, and 劉聿民. "Investigation on LTPS-TFTs With High-κ Gate Dielectrics." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/09326493248521225783.

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碩士
國立交通大學
電子物理系所
98
In this thesis, p-channel LTPS-TFTs with different thickness of the HfO2 gate dielectrics were fabricated and investigated. We compared the electrical characteristics and the NBTI reliability issue of the p-channel LTPS-TFTs with the different thickness of HfO2 gate dielectrics. As for the electrical characteristics, we found that the peak transconductance (Gm_max) increases with the HfO2-thickness. This phenomenon violates the well known knowledge that the gate control ability should be enhanced with a higher gate capacitance. Therefore, it is worthwhile to investigate the mechanism of this phenomenon. We found that the phase change of the HfO2 layers contributes to the Gm_max degradation of the TFTs with the thin HfO2 layer. Besides, it was found that the enhanced Gm_max ¬of the p-channel TFTs with the thicker HfO2 layer is related to the intrinsic charged oxygen vacancies in the HfO2 layer. Finally, the degradation mechanism of the NBTI stress was systematically studied. It was found that the behavior of Vth variation, S.S. degradation and the Gm_max degradation are mainly dependent on the thickness of the HfO2 layer, stress temperature and the stress bias.
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Huang, Shu-Mei, and 黃淑美. "DC model and small signal model for LTPS TFT." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/14659468524303026145.

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碩士
國立臺灣大學
電機工程學研究所
97
Low-temperature poly-silicon (LTPS) is becoming a standard technology for the fabrication of thin-film transistors (TFTs) used in active matrix liquid crystal displays and in active matrix organic light emissive displays. In order to be able to simulate large number of matrix pixels or integrated drivers, this model is simple enough to allow simulator convergence. A analytical model for the DC characteristics of both n- and p-channel LTPS TFT is described. Our approach results in a physically based model with some parameters, which are related to the device structure and fabrication process. The DC model describes all regimes of operation: linear, saturation, and Kink. The effects of temperature and channel length are also included in our model. This thesis also contains the small-signal modeling. This method consists in a direct determination of all the FET parasitic elements. The knowledge of these parasitic element values allows us to determine the intrinsic parameters after a few simple matrix manipulations. Then all the extrinsic and intrinsic components are determined.
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曹虹娟. "Study of LTPS TFTs Degradation Under Gate Pulse Stress." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65929546162389490519.

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16

Hsu, Wei-Jen, and 許維仁. "Design of driving circuits for LCD in LTPS technology." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/23157525422253412205.

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碩士
國立交通大學
電子工程系
91
In this thesis, the possibility to implement the driving circuits for LCD in LTPS technology is discussed. The driving circuits for LCD can be divided into two groups, the gate driver and the data driver. Gate driver includes shift registers, level shifters, and output buffers. Data driver consists of shift registers, latches, level shifters, a digital to analog converter, and output buffers. The design of output buffers in the source driver is focused in this thesis. Considering the characteristic of liquid crystal molecule to electrical field and the quality of display, the output buffer must satisfy a particular input pattern and operating method. Moreover, it should achieve low quiescent power and small circuit layout area. A class-AB output buffer, which can be operated with high slew rate, low power and small layout area, has been designed and realized in VIS 0.35μm 2P4M 18V process. However, in LTPS technology the current source is significantly affected by threshold voltage drift and the kink effect. Therefore, a proposed way to design output voltage buffer is to use bias current source as less as possible. Thus, a class-B output buffer has been proposed and implemented in Toppoly 6μm LTPS 1P2M process. In order to compare both of their performance, these two buffers with the same loading are measured. Finally, according to the characteristic of TFT, its body is connected out to control the threshold voltage of device. Four kinds of level shifters to proof our idea have been designed to apply them in the gate driver of LCD. The measurement results confirm that the level shifters can be operated with lower input signals by applying adapted bias voltage to body.
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17

Sung, Wen-Hsiang, and 宋文祥. "Fluorine Effects on the Characterization of LTPS Thin-Film Transistors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/01051365330051622172.

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碩士
長庚大學
電子工程研究所
95
In LTPS TFTs research, the gate oxides were usually deposited as TEOS or PECVD oxide and so on. As the same, EOT shrinking trend in CMOS technology, hafnium oxide (HfO2) was applied as gate insulators of LTPS TFT to have better performance. However, many researchers have found that the etching rates of HfO2 with post-deposition-anneal (PDA) or thermal budget process decrease rapid in dilute HF solutions, so the etching of thick HfO2 is an issue for process integration of LTPS TFTs. Therefore, the additional O2 ion-bombardment process is proposed to enhance the etching rate for HfO2 films of as-deposited and PDA 600℃with dilute HF and SF6 dry etching by two-step etching method. In this thesis, we also demonstrated that it has been improved which including electric field of breakdown, trapping rate and Weibull distribution of charge-to-breakdown for polyoxide capacitors, consequently the off-state current, on-state breakdown voltage and grain-boundary trap-density are also improved on LTPS TFTs by CF4 plasma pre-treatment. These improvements have been attributed to reduce grain-boundary trap-density effectively and produce strong Si-F bond than Si-H bond at interface region. Finally, the Negative Bias Temperature Instability (NBTI)reliability experiment has been finished discussion for conventional and fluorine implantation of p-channel LTPS TFTs. The variation of subthreshold swing, threshold voltage shift, field-effect mobility and interface trap states for fluorine implantation of LTPS TFTs are relative decreased than conventional LTPS TFTs under NBTI stress. These improvements have been attributed strong Si-F bond to replace weak Si-H bond at interface and grain-boundary region.
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18

Chang, Yi-Ching, and 張宜菁. "Study of Drain Leakage Current Suppression Method for LTPS TFTs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/69885569746691550537.

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碩士
國立清華大學
電子工程研究所
98
LTPS-TFTs, due to the high density defects located at the grain boundary and the in-grain as well as sharper drain junction, exhibit unique off-sate leakage current characteristics. The two-dimensional process simulator was adopted for constructing the poly-Si TFT structure, and then electric characteristics of the device were then evaluated by the 2D-device simulator. In this simulation, it was found that by introducing hot holes in the dielectric film, GIDL can be effectively suppressed. Through a series of simulations, the amount as well as the location of the position charge stored in the dielectric layer for the best suppression effect is analyzed. Based on the experimental results, the GIDL current can be significantly suppressed after band-to-band hot hole (BBHH) stress. This stress method is able to increase the on/off ratio of the LTPS-TFTs. Finally, the speed of hot hole injected and the stability of the suppression effect is investigated.
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19

Tsao, Mu-Ying, and 曹沐瀠. "Study of Photo Drain Leakage Current Suppression in LTPS TFTs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/93538695478004758966.

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Abstract:
碩士
國立清華大學
電子工程研究所
99
The performance level and reliability of low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) have greatly improve in recent years as a result of intensive research for the integration of high speed circuits on glass substrates (SOP). With their high mobility and operation stability, LTPS-TFTs have been used extensively in small-to-medium display panels. In display applications, LTPS TFTs are exposed to fairly strong backlight from the back plane and/or ambient light. Under illumination, photon-induced carrier generation on the poly-Si body can induce large off-state leakage current, much higher than that in a dark environment. High off-state leakage current in these TFTs not only lead to increased standby power, but also cause operation errors as well as degradations in display quality. The introduction of a bottom shielding gate is expected to eliminate photo-induced leakage effectively. However, the subsequent additional drain turn-on effect can become problematic for the TFT driving circuits. In this study, we investigate the design of the bottom shielding gate to optimize the off-state drain leakage current suppression as well as minimizing the drain turn-on effect. Asymmetric shielding gates and surround structures are found to be a promising solution to alleviate the drain turn-on problem. Dual and double gate designs are also effective and reliable methods to minimize the off-state photo leakage current without enhancing the drain turn on effect.
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20

Huang, Jun-Hao, and 黃鈞顥. "Electrical Measurement and TCAD Simulation for LTPS Thin Film Transistor." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/29qkzu.

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Abstract:
碩士
國立中興大學
光電工程研究所
101
The present study focuses on the relationship between low temperature poly-Si thin film transistor (LTPS N-TFTs) channel direction and carrier mobility. First, we study related knowledge from the literature as well as introduce the background and process technology regarding thin film transistors. We also introduce the reduction of the grain boundary defect. Our study is broken down into two steps. The first step, we observe the relationship between LTPS N-TFTs and its electron characteristics. Then, we define some electron parameters that we want to know. From the ID-VG and ID-VD measurement results, we show that the drain current of LTPS N-TFTs will be an up- and down-swing curve. The smallest current occurs while the channel direction is equal to 0°. When the channel direction is equal to 45°, it has the largest drain current and the highest carrier mobility. Additionally, the drain current is reduced again at the channel direction when it is equal to 90°. The second step, we fit the measured result with a Sentaurus TCAD to simulate its electron characteristics. We establish a trap model to help us describe its grain trap state. As a result, the different channel directions have different trap state influences on carrier mobility that results in different drain currents.
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21

Liang, Hsing-Yi, and 梁馨宜. "Study of Channel-width-dependent Reliability Behavior of LTPS TFTs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/55435106310280633596.

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Abstract:
碩士
國立清華大學
電子工程研究所
95
Sequential lateral solidification (SLS) technology developed for crystallizing amorphous Si enlarges grain size and controls the position of grain boundaries effectively. However, thin-film transistors made by SLS suffer reliability issues possibly due to the innate sub-grain boundaries parallel to the drain current direction as a result of this unique solidification process. In this thesis, we observed channel-width-dependent degradation on these devices after hot carrier stress. A degradation model was proposed and verified by comparing the measured characteristic with the simulated behavior on the proposed sub-circuit, which successfully explains the degraded transistor behavior and its width dependence.
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22

Huang, Ju-Lin, and 黃如琳. "On-Glass Driving Circuits Design for LCD in LTPS Technology." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/35aahk.

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Abstract:
碩士
國立交通大學
電子工程系所
92
In this thesis, on-glass driving circuits for LCD are designed and implemented in low temperature poly silicon (LTPS) technology. The driving circuits for LCD are divided into two parts, gate driver and source driver. Gate driver includes shift registers, level shifters, and output buffers. Source driver is composed of shift registers, latches, level shifters, a digital to analog converter, and output buffers. The implement of the on-glass source driver is the focus in this thesis. First, two circuits, which are slew rate enhancement output buffer and low power class-B output buffer, are designed to drive the heavy loading of LCD. Second, a threshold voltage compensation circuit is proposed to solve the drift of the threshold voltage in LTPS process. Third, due to the nonlinear relationship between transparency and voltage across liquid crystal, a digital to analog converter with gamma correction is adopted to compensate this effect. Finally, level shifters using body-bias technique are also proposed. According to TSMC 0.35-μm CMOS HV process, the operational speed and power consumption of level shifters in different body-bias voltages are simulated and analyzed. All of above circuits have been implemented in TOPPOLY 6-μm or 3-�慆 LTPS process. Moreover, in order to satisfy the high resolution LCD, source driver usually employs the specification for reduced swing differential signaling (RSDS) as the transition interface in the data receiver. Besides, the application of the specification for RSDS will increase the data transition speed and reduce the electric magnetic interference (EMI) effect. So, a fundamental RSDS receiver in TOPPOLY 6-μm LTPS process is also included in this thesis.
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23

Cheng, Chia-Pin, and 鄭枷彬. "Study on the Feasibility of LTPS TFTs for Light Sensing Application." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/07568578777051280982.

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Abstract:
碩士
國立交通大學
顯示科技研究所
96
Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have attracted much attention in the application on the integrated peripheral circuits of display electronics such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to its better current driving compared with amorphous silicon (a-Si) TFTs. Various attempts have been reported to integrate display circuits to peripheral area of the glass substrate. In addition to the peripheral area integration, circuit integration to pixel is considered to be required to realize so-called high-value added display or sheet computer having input function, especially in mobile equipments. Integration of LTPS optical sensor is considered to have a potential to be a key technology for various kinds of advanced functions such as ambient light sensors, image scanners, touch panel, etc. An ambient light-sensing function, which is one of several high-value added functions, can contribute to low power consumption and improve visibility by detecting ambient light around the display panel and controlling the brightness of the display panel. In this thesis, we present a detailed experimental study of the LTPS TFTs behavior under halogen lamp illumination and identify the different TFT operating regimes. We also propose a light-sensing circuit using the identical LTPS TFTs fabrication processes without any extra cost. The proposed circuit, which has a source follower, can sense the photo leakage current under different illumination intensities and convert the current to analog voltage signal and then digital one. Through the measurement of the proposed circuit under light variation from 0 to 31320 lx, we confirmed that the proposed light-sensing circuit can perform sensing and readout operations accurately. However, we also consider the device variations such as threshold voltage (Vth) shift and OFF current variation and propose the calibration methods to reduce the illumination intensity error from 4700 lx to 1200 lx and compensate the Vth shift variation.
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24

Chuang, Jen-Chi, and 莊仁吉. "Evaluations of the Leakage Current and Reliability on NILC-LTPS TFTs." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/87511909053949182271.

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Abstract:
碩士
國立交通大學
工學院碩士在職專班半導體材料與製程設備組
97
TFT display panels are widely used for consumer products on worldwide market. Among various techniques of fabricating Low Temperature Polycrystalline Silicon(LTPS) thin film to obtain higher performance TFTs, Nickel metal-Induced Lateral Crystallization(NILC) attracted considerable interest for their better uniformity and crystal quality acquired at lower annealing temperature and shorter annealing time. However, in the processing of NILC Poly-Si, residual Ni trapped by the grain boundaries and defects leads to introduce deep level states and results in degradation of the device performance. Therefore, it’s very important to fabricate NILC-LTPS TFT with higher performance and quality by reducing Ni contaminations and dangling bonds of NILC Poly-Si thin film. This study mainly provide simple and effective procedures to figure out the leakage current paths of NILC-LTPS TFT by using performance improved TFT samples with various process splits. Then, the influence of device reliability would be also observed. The leakage paths of NILC-LTPS TFT are divided 4 parts to do discussion. (1)Gate oxide leakage current, which is from bad oxide etching profile, or bad oxide growth quality. (2)Gate induced drain leakage current, which is from higher electric filed applied between gate and drain to induce drain leakage current. (3)Junction leakage current, which is from thermionic emission, thermionic field emission, and pure tunneling of the PN junction. (4)Channel leakage current, which is from electric field punch through, drain indruced grain barrier lowing, and metal contaminations. Using electrical measurement methods to figure out which one is key factor. TFTs performance would be degraded under frequently operation with effects of electric filed and temperature, then induced on-current reducing, threshold voltage raising, and leakage current increasing. Herein, there are two parts to discuss device reliability. The first one is Bias Temperature Instability(BTI), which is a device degradation effect from dangling bonds of the interface between gate oxide and Poly-Si are generated by Si-H bonds broken under voltage bias gate and high temperature environment with combinated Hydrogen diffusing out. Another one is Hot Carriers effect Injection(HCI), which is degraded from interface trap states increased by gate oxide bombarding of impact ionization. The ionization electrons and holes are generated by impact from accelerating carriers to neutral atoms under high electric field of voltage bias drain on device on-state. Two experiement samples are demonstrated in this study. One is NILC Poly-Si with interface treatment of CF4 plamsa etching gas before gate oxide deposition. This method could improve device performance with reduction of Ni metal residues by slightly plasma bombarding and decrease of grain boundary trap states by bonding of Fluorine and Silicon. Another one is raising device performance with decrease of Ni contamination by amorphous Si gettering of source/drain side through metal contact via.
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25

Sun, Guo-Pei, and 孫國珮. "Study on the Mechanism of Unit-Lux Current for LTPS TFTs." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/36648877039719908362.

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Abstract:
碩士
國立交通大學
顯示科技研究所
97
Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been widely used on the active-matrix liquid-crystal displays due to the excellent current driving ability. In addition, all kinds of attempts of high added value functions like light sensor, touch panel, image scanner, etc. have been reported to integrate display circuits to peripheral area of the glass substrate. If we integrate the ambient light sensor with the same LTPS technology used to fabricate the display, the power consumption can be reduced, and the fabrication process can be simplified. Therefore, the photosensitivity of LTPS TFTs is a significant design consideration for achieving high-image-quality display panels In this thesis, first, we confirm that the photo leakage current occurs mainly on the drain side. Furthermore, photo current behaviors affected by extra defect states creation have been also investigated. Hot-Carrier and Self-Heating effects afford different types of defect states creation in the energy gap and change photo leakage current versus drain bias. Moreover, we also revise the empirical formula for ULC to provide even more accurate description of the photo induced current under the presentation of defect states and temperature. Thus, we proposed a ULC model for TFT versus the changing trend of fitting factors to explain these illumination behaviors.
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26

Yeh, Chi-Ruei, and 葉啟瑞. "Investigation on Reliability of LTPS-TFTs With High-k Gate Dielectrics." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65959513161143402530.

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Abstract:
碩士
國立交通大學
電子物理系所
97
In this dissertation, high performance p-channel low temperature poly-silicon thin-film transistors (LTPS-TFTs) with high-κ gate dielectrics are fabricated and investigated. In order to enhance the characteristics of LTPS-TFTs, we adopted the employment of HfO2 gate dielectric and the novel crystallization methods, metal-induced laterally crystallization (MILC), to fabricate high performance devices. High filed effect mobility μFE ~ 215 cm2/V-s, ultra-low subthreshold swing S.S. ~ 107 mV/decade, and low threshold voltage VTH ~ -0.75 V are derived from MILC-TFT with HfO2 gate dielectric without any defect passivation methods. Negative bias temperature instability (NBTI) degradation mechanism in solid-phase crystallization (SPC) and MILC LTPS-TFTs with HfO2 gate dielectric has been studied systematically with a conventional DC measurement technique. We used the previously empirical formula for traditional NBTI in SiO2 to analyze the high-κ gate dielectric in our experiment. The results showed that NBTI degradation is more dominated by the generation of interface trap states (NIT) and the MILC transistors have more stability characteristic than SPC during the NBTI stress. Finally, the drain bias effects on NBTI degradation mechanism is also investigated. The results showed that drain bias can reduced the vertical electric field across gate dielectric and improved the NBTI-induced degradation. From experimental data, the NBTI model with drain bias effect is established. A good fit on the threshold voltage shift (ΔVTH) prediction is obtained and confirms our theory.
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27

Wu, Hung-Yu, and 吳鴻佑. "Fabrication and Characterization of High Performance Double Channels LTPS NILC TFTs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/94494419734939568332.

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Abstract:
碩士
國立交通大學
工學院碩士在職專班半導體材料與製程設備組
99
In this research, we mainly discuss methods to produce a Low-Temperature Polycrystalline Silicon Thin Film Transistor(LTPS TFT) with better electric properties by using Nickel-Induced Lateral Crystallization ( NILC) and the construction of double channel. We also discuss factors that improve NILC’s electric properties and its new construction. The design of using double-channel in the new construction, which enables the combination of Field Induced Drain (FID) and Raised Source/Drain (RSD) should provide below three benefits: 1. Reduce the electric field to lower the threshold voltage, 2. promote the carrier mobility, 3. decrease the kink effect, and reduce the subthreshold swing. Moreover, due to the less deep state of dangling bonds, the accumulation of positive charge, and donor-like defect, NILC gains higher mobility and subthreshold swing and smaller threshold voltage. At first, the paper will discuss the performances of electric properties with single channel and double channel. Secondly, our experiment proved that the component of double channel improved electric properties better than the component of single channel. Finally, we compared the TFT elements of NILC method and SPC method. As the result, we found out that NILC gained better electric properties due to the larger grain size, and so on. By combining the new findings from the results, we claim that the Double Channels LTPS NILC TFTs with the combination of NILC method, FID, and the construction of RSD will improve electric properties greatly, such as, lowering the voltage, promoting the carrier mobility, reducing kink effect, and minimizing the subthreshold swing; which proved the design of the experiment to be true and accurate.
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28

廖清泉. "Electrical Properties and Reliability Studies of P-Channel LTPS-TFT Devices." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/77527355275359353509.

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Abstract:
碩士
明新科技大學
光電科技產業研發碩士專班
99
This paper presents the illumination reliability and DC bias stability of P-TFT devices doped with B2H6 and un-doped with B2H6. Photo reliability results indicate that the threshold voltage (Vth), of the p-TFT device was shifted to positive values by increasing illumination intensity, and C-V curves will be in accordance with the Vth shift to positive voltage. Off current (Ioff) and sub-threshold swing (S.S.) of p-TFT devices were increased with increasing illumination intensity. The photons impacted with P-N junction, creating electron-hole pairs (EHPs) and contributing into the normal current, therefore Ioff was increased. By comparing devices’ channel doping processes with B2H6 or not, p-TFT devices doped with B2H6 had larger Vth shift, variations of S.S. and off current than those of the un-doped devices after illuminations. The reason why the doped p-TFT devices revealed much photo sensitivity is B2H6 dosage doping directly inside the channel of p-TFT grain boundaries creating deep states and capture electron caused larger Vth shift and worse device degradation. The hot carrier stress and self-heating stress test p-TFT devices were carried out as a DC bias stability measurement. The hot carrier stress results show some electron-hole pairs would be generated by impact ionization near the drain and then electron got trapped in the gate oxide near the drain junction, formation of the interface traps, causing lower Ioff, and increasing field effect mobility. The CGD curve increases slightly when the gate voltage is smaller than the VFB while in the region the CGS curve almost remains the same. Hydrogen released from the p-TFT devices generating high temperature after self-heating stress, some electron-hole pairs would be generated by impact ionization near the drain and p-TFT grain boundaries creating trap states capture hole. Therefore, Vth values shift to negative voltage and S.S. values increases, whereas the field effect mobility (u) and drive current (Ion) decrease after the self-heating stress. Both of CGS and CGD curves will be in accordance with the Vth shift to negative voltage. However, electrons got trapped in the gate oxide near the source junction, and formation of the interface traps. The CGS curve increases slightly by the interface traps. Comparing with device degradation mechanisms after these two DC bias effects, the hot carrier effect and the self-heating effects generated the interface traps in the drain and the source junction, respectively, and causing the individual CGD curve and CGS curve increase slightly, then more upward shift after further illumination.
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29

廖盛斌. "Study of LTPS TFT Process by Using Semi-Exposure Mask Technology." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/51692350326449652170.

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Abstract:
碩士
國立交通大學
平面顯示技術碩士學位學程
100
This paper is discussed how to reduce the LTPS TFT process in order to make cost down, reduce the process time and increase the production value. For this purpose, I propose the New(1) and New(2) LTPS TFT process flow, using gray tone mask to merge two PEP photo process into one and skip photo process technology . Application of these technologies can reduce 1 to 2 photo process, so it is better than normal LTPS TFT process. About the gray tone mask, we use the special property of gray tone mask. The bi-layer making photoresist remain could merge the photo process of Poly-Si and NMOS souse/drain define or PMOS NMOS souse/drain define into one. About the channel doping, we could skip the channel doping mask and skip one photo process. To adjust channel doping dosage to make the threshold voltage of NMOS and PMOS balance. Besides, under some reliability test like PGBS (Positive Gate Bias Stress), NGBS (Negative Gate Bias Stress) and GDBS (Gate and Drain Bias Stress), we can fine the LTPS TFT performance of New(1) and New(2) are similar to normal LTPS TFT process. At last, according to the experiment result, we know the technology of gray tone mask and skip photo process could reduce the array process substantially. And it also could reduce the production cost, process time and the production valve. In TFT performance, we find out that the TFT performance of gray tone mask as well as normal LTPS TFT process.
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30

Lin, Yu-Ta, and 林佑達. "Design and Realization of Capacitive Sensor Readout Circuit in LTPS Technology." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/33089706727969712311.

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Abstract:
碩士
國立交通大學
電子研究所
99
Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been widely investigated as a material for portable systems, such as digital camera, mobile phone, personal digital assistants (PDAs), notebook, and so on, because the electron mobility of LTPS TFTs is about 100 times faster than that of the conventional amorphous silicon TFTs. Furthermore, LTPS technology can achieve slim, compact, and high-resolution display by integrating the driving circuits on peripheral area of the display. This technology will also become more suitable for realization of System-on-Panel (SOP) applications. With SOP technique, circuits for various functions can be integrated on glass substrate to become value-added displays. Also, the input display technology creates opportunities for new applications such as a scanner for recording of text or images for on-line shops and touch-sensing circuits for detecting the position of finger or pen. Recently, integrating touch panel into glass substrate has attracted much attentions because of the aforesaid advantages. Touch panels used in mobile applications are mainly resistive or capacitive. Although resistive touch panel can achieve low cost with rarely malfunction, it has some drawbacks including serious glare, low transmittance, and single touch only. On the other hand, capacitive touch panel can realize multi-touch functionality easily which allows user to operate information instruments more intuitively. Because most LTPS TFTs are based on excimer laser crystallized poly-Si, random orientation of poly-Si grains, grain size variation, and incomplete termination of grain boundaries would lead to a quite large threshold voltage variation of TFT device which contributes to serious impact on the accuracy of analog circuits. In this work, a new readout circuit for capacitive sensor on glass in LTPS fabrication process has been proposed. The switch capacitance (SC) technique is used to compensate the threshold voltage variation effect. Different values of the sensed capacitance can be judged by ADC. In this way, the overall resolution for touch panel can be enhanced by interpolation method.
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31

Wang, Shou-Kuan, and 王守寬. "Engineering in channel layer for the performance improvement of LTPS-TFTs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/98596469846390340717.

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Abstract:
碩士
國立臺灣科技大學
光電工程研究所
98
In order to improve performance and reliability of low temperature poly-Si thin film transistors (LTPS-TFTs). In this thesis, the Poly-Si channel was covered with Fluorosilicate glass (FSG). When the source and drain were activated, the fluorine would drive-in the channel. It could reduce the trap in the channel so that it would improve the performance and reliability of device. We further studied the effects by the concentration of fluorine. When we deposited the FSG, we changed the flow of CF4 to investigate the influence of device with different concentration of fluorine. We would demonstrate in this thesis. It was difficult for nitrogen to through the passivation layer to reach the channel layer by traditional N2 plasma treatment. So we also used the HC-CVD system to treat the channel with N2 plasma. Hence the nitrogen could enter the channel to become Si-N bonds so that it could reduce the trap in channel. Due to the theorem of HC-CVD, the damage of channel surface was very small. It was better than used the HDPCVD to treat channel with N2 plasma. The HC-CVD system had better performance and reliability than the HDPCVD system.
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32

Yang, Chun-chieh, and 楊鈞傑. "Performance Improvement of LTPS-TFTs with CF4 plasma treated Buffer Layer." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10704178456307935923.

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Abstract:
碩士
國立臺灣科技大學
電子工程系
97
In this thesis, we develop a novel fabrication process to incorporate Fluorine ions with LTPS-TFTs. We use this process to discuss the difficulty of fluorine’s incorporating, the enhancement to device electrical characteristics; and compare this process with conventional ones. Our process used the CF4 plasma treatment for the Buffer Layer, making fluorine ions incorporated into this film. Followed with the a-Si channel layer deposition, the Si-F bond was formed by the SPC process to passivate the defects in the channel film. Thus, the process can enhance the electrical characteristics of our device. Differ from conventional techniques which treat the channel film directly, this thesis focused on the treatments on the Buffer Layer. We reduced the damage caused by the CF4 plasma. At the same time, the performance improvement was maintained.
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33

Chiu, Hao-Lin, and 邱皓麟. "Study on the Behaviors of LTPS TFTs C-V degradation Characteristics." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/88718641641875057577.

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Abstract:
碩士
國立交通大學
光電工程系所
94
Low Temperature Polycrystalline Silicon (LTPS) thin film transistors (TFTs) have attracted much attention in the application on the integrated peripheral circuits of display electronics such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to its better current driving compared with a-Si (amorphous silicon) TFTs. In the chapter two of this thesis, the reliability of LTPS TFTs is studied in form of stress map by adopting the crosstie layout TFTs to get the more consistent reliability behaviors. This database of reliability is very helpful to evaluate the lifetime and operation conditions of LTPS TFTs. In addition, we will focus on the C-V characteristic of the low temperature poly-Si TFTs and have further discussion of C-V characteristic under the specific bias voltage. As the example with the characteristic of voltage of C-V curve, it is found that before and after this condition of operating, its CGS & CGD presented obvious shift, and about 40% of the increase appears near the initial voltage in CGS curve, but only about 10% of the increase appears in CGD curve. The result shows the difference of characteristics of the C-V curve of both ends of the device comes from self-heating stress condition, the voltage difference between gate/source is very large, so cause the increase of the defect of interfaces, form one section of behaviors of rising of CGS latter half. And the voltage between gate and drain is smaller than that of gate and source, so the influence is slightly. Characteristic of C-V curve received under the hot carrier effect can find that its CGS curve has not presented the obvious change, but CGD curve drops near the initial voltage, and it is interdependent to present obvious frequency. The description of these component degradation behaviors can be described with the degradation model that we propose, and in order to imitate its trend of simulation. Finally , take the place of the model of C-V curve with the degradation one in ring oscillator and with H-SPISE simulation, find that the influence on the circuit of the electric capacity is very enormous.
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34

Chen, Chien-Kun, and 陳建焜. "Study of N-type LTPS TFTs Degradation Under Gate Pulse Stress." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/51027282893763574472.

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Abstract:
碩士
國立交通大學
顯示科技研究所
94
Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode (AMOLED) displays. The significant advantages over amorphous silicon (a-Si) TFTs are in the higher current driving capability and the better reliability. In poly-Si TFT-controlled displays, poly-Si TFTs are used to implement pixel circuits and driving circuits on a single glass substrate to reduce system cost and posses compact module. Therefore, the poly-Si TFT is the best candidate to realize system–on–panel (SOP). However, unlike pixel TFTs, TFTs in driver circuits are subjected to high-frequency voltage pulses. Therefore, the degradation mechanism under dynamic operation should be understood in detail. In this thesis, the device degradation of low-temperature polycrystalline thin film transistor under AC stress has been investigated. The degree of degradation is concerned with the magnitude of the lateral transient electrical field and the variation of the number of the carriers near the source/drain. For the gate voltage swing of -15V to 15V, it is observed that the degradation depends on the falling time of the gate pulse but does not depend on the rising time. However, it is firstly observed that the degradation is both dependent of rising time and falling time if the voltage swings below the threshold voltage. TFT’s slicing model take channel resistance and oxide capacitance into consideration is proposed to explain the degradation of poly-Si TFTs under Gate Pulse Stress. A reasonable agreement between the experiment data and the simulation results reveals that the degradation is related to the transient electrical field and the various amount of the charge near the edges of the channel. In addition, a new index which can be simulated using a slicing model is proposed and it is almost proportional to the degradation degree. For the peripheral circuit in poly-Si panel, NAND and NOR logic gates are the fundamental elements. When input terminals A and B of NAND and NOR are 0 and 1, respectively, floating drain TFTs appear. Therefore, a new AC stress condition is needed to discuss, called floating drain AC stress. We will also discuss the phenomenon for poly-Si TFT under floating drain AC stress in the chapter 3.
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35

Yu, Cheng-huang, and 游政煌. "New Protection Eletric Circuit Design on LTPS TFT LCD Electro-Static Discharge." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/38263416205920625548.

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Abstract:
碩士
元智大學
電機工程學系
96
A new circuit design of electro static discharge (ESD) is proposed. In order to increase the ability of ESD protection, we design a diode ring in LTPS TFT LCD. LTPS TFT LCD is tested by ESD simulator and ESD current is measured by current probe. Without diode ring, the ESD simulator input voltage is 200V, a 844mA static current is obtained. With diode ring, when the static current equal to 844mA, the ESD simulator input voltage is 280V. In our new circuit design, the ESD simulator voltage has been elevated from 200V to 280V, which indicates a 40% voltage rise.
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36

Han-Ching, Ho, and 何漢清. "Study on the Thermal Effect of LTPS TFT for Temperature Sensor Application." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/27561247551797627004.

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Abstract:
碩士
國立交通大學
顯示科技研究所
96
Low Temperature Polycrystalline Silicon (LTPS) thin film transtrators (TFTs) have attracted much attention in the application on the integrated peripheral circuits of display electronics such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to its better current driving compared with a-Si (amorphous silicon) TFTs. Recently high-end flat panel display is what we are pursuing. Sensor on panel is one of value-added functions for display panel. Various sensors are created on panel such as ambient light sensor, image sensor, gas sensor and so on. In this thesis, we propose a temperature sensor circuit, which includes sensing, read out and digitization, can directly use LTPS TFTs identically fabricated with the pixel TFT. So we don’t need any additional cost. Considering the thermal characteristic and variation characteristic of LTPS TFTs, off region current is utilized. In addition a calibrate method is proposed to deal with the device variation. This method can reduce the sensing errors of measuring to 5℃.
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37

Lin, Tai-Ming, and 林代明. "PWM GRAY SCALE PIXEL CIRCUIT ANALYSIS AND SIMULATION FOR LTPS AMOLED PANEL." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/53079337094939498514.

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Abstract:
碩士
大同大學
通訊工程研究所
93
OLED is the promising flat panel display in the future. In this thesis, we adopt the Cadence simulator to analyze and simulate the proposed PWM gray scale pixel circuit based on Hitachi developed “Clamping Inverter Driving Circuit” to represent full color display, with modification for moving picture performance improvement, moreover a ac-driving method to prolong the OLED lifetime is included. The separate R, G, B emitters are adopted to display the full color and the pixel driving circuit are implemented by LTPS fabrication process, the component models are set up by CHUNGHWA PICTURE TUBES Ltd. The column driver LSI ( Novatek NT3947) and video processor chip (MXIC, MX88V44.) are now available to make the whole circuit design easily.
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38

Lin, Yu-Jung, and 林雨蓉. "The Study of Measurement System Analysis for Measurement Instrument Variation on LTPS." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/90704867182900901882.

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Abstract:
碩士
元智大學
化學工程與材料科學學系
97
Along with the rapid growth of the LTPS industry, the demand for quality level is getting higher and higher. To assure that our measurement system can obtain the correct and effective measurement data, this study will apply the MSA approach to improve the measurement capability of DMS, and take advantage of the ANOVA analysis of statistics method and Cause-and-Effect Diagram of Quality tools to evaluate the source of the measurement system’s variation, then improves it, not can only reduce the measurement system’s variation effectively by 32.18% and 59.74% reduces to 4.17% and 8.02%, but also to improve the reliability and accuracy of the measurement result. After steady state of measurement system, uses Standard Light Source Measurement System to find out the correlation and difference from the deviation analysis of all various optical measurement systems, as will forecast the optical measurements system’s luminance in the future the application in the company.
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39

Kuo, Yen-Ting, and 郭彥廷. "Design of all-digital phase-locked loop implemented in LTPS TFT process." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/08413357601583310406.

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Abstract:
碩士
國立臺灣大學
電子工程學研究所
97
The thesis presents an all-digital phase-locked loop (ADPLL) as a clock generator implemented in 3um LTPS TFT process. The output frequency range of the ADPLL is from 0.625MHz to 12MHz, the multiplication factors of the reference clock are 1 to 30, and the time resolution of the coarse-tuning part of the DCO is 5.6 ns and that of the fine-tuning part is 0.25ns by simulation. The measuring result of the time resolution of course-tuning part is 8ns. PLL is an essential module in many applications, and the trend of development of PLL is toward all-digital realization. The nature of digital circuits has high immunity against process deviation and it is easy for circuits to be ported among different processes.
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40

Lin, Chien-Wen, and 林俊文. "Study on the C-V characteristics for LTPS TFTs under DC stress." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/23498548437711108862.

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Abstract:
碩士
國立交通大學
電機學院光電顯示科技產業專班
95
Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode (AMOLED) displays. However, most of the previous reseaches focus on the current-voltage characteristics, while the discussion about capacitance - voltage degradation is few. In this thesis, the degradation of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) under DC stress is investigated with the measurement of the capacitance between the source and the gate (CGS), as well as the capacitance between the drain and the gate (CGD). The main degradation mechanisms of the DC stress are hot carrier effect and self-heating effect. This work focuses on the C-V behaviors of the LTPS TFTs with these two mechanisms and discovers that the C-V curves exhibit apparent frequency dependence. For the different stress conditions, the degradation mechanisms in the thin film transistor are discussed. With the concepts of circuitry, we develop a new thin film transistor electric circuit model, and explain the changes in adds under the different stress conditions in the C-V and I-V behaviors. The newly established thin film transistor electric circuit model can put in the middle of the simulation software to help designers with faster and convenient understanding device’s characteristics and design conditions. Hence, the designers can compute a more complex electric circuit within shorter design period to achieve the target of having an advanced breakthrough in designing system on panel (SOP) circuit. On the other hand, the technology development can help the display panel show the vivid images than the present product.
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41

Su, Ko-Ching, and 蘇可青. "Study on the LTPS TFT Circuits For X-ray Active Matrix Sensor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/14529320742343423292.

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Abstract:
碩士
國立交通大學
光電工程系所
94
The application of low-temperature poly-Si TFT circuits for the high resolution X-ray active matrix sensor is explored. The integration of poly-Si TFT circuit on the glass enables an easy connection for the sensor array with fine pixel pitch. A novel charge sensitive amplifier circuit employing poly-Si TFTs is proposed for the readout system of the active matrix sensor. It can considerably reduce the circuit’s sensitivity to unavoidable threshold voltage variations of the poly-Si TFTs. The TFT VTH mismatch which results in the offset voltage of the charge amplifier can also be depressed by the new circuit. However, the noise arisen from the VTH mismatch can be even larger than that from the VTH variation after compensation. For the higher bit digital X-ray image, it must be properly taken into consideration.
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42

Weng, Shih-Hsueh, and 翁世學. "The Fabrication and Stability Study of the Novel Structure of LTPS TFTs." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80519573963936569669.

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Abstract:
碩士
國立交通大學
電子工程系所
93
In this paper, a novel structure of the polycrystalline silicon thin-film transistors (Poly-Si TFT’s) with a thicker source/drain and a thin channel have been developed and investigated. In the proposed structure, the thick source/drain and a thin active region could be achieved with only four mask steps, which are less than conventional stagger TFT. The proposed TFT has and higher Swing (~1.51). The on/off ratio is 1.85x107 for Vgs= 5 V Moreover, the proposed TFT exhibits excellent current saturation characteristics at high bias (Vgs= 30 V) and has more than 2.96 times reduction in minimum off-state current compared to conventional TFT’s. Index Terms—stagger source/drain, On/Off current ratio, poly-Si TFT.
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43

Liu, Hung-Guang, and 劉宏光. "Study on the Simulation for the Variation in LTPS TFTs Digital Circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/72270255868511488104.

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Abstract:
碩士
國立交通大學
光電工程系所
93
Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs). The significant advantages over amorphous silicon (a-Si) TFTs are in the higher current driving capability and the better reliability. In poly-Si TFT-controlled displays, poly-Si TFTs are used to implement pixel circuits and driving circuits on a single glass substrate to reduce system cost and posses compact module. Therefore, the poly-Si TFT is the best candidate to realize system-on-panel (SoP). However, due to the irregularly distributed grain boundary, poly-Si TFTs have poor uniformity and suffer from huge variation. In this thesis, the device variation is described. Its influences on the digital circuits and circuit simulation techniques to estimate the circuit performance are also discussed. The purpose of this thesis is to develop a new simulation skill that the operation frequency and power consumption of an n-stage shift register can be obtained through simplifying propagation delay from an n-stage one to an one-stage one.
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44

Chiang, Keng-Ching, and 江耕慶. "The Test Structure For The SOG Application Of LTPS TFTs And Performance Analysis." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/25391429089605264854.

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Abstract:
碩士
中原大學
電子工程研究所
95
Most of the flat panel displayers (FPD) are active matrix liquid crystal displayer (AMLCD). The Major of the development is a-Si:H TFT, because it has some advantages, like stable process, better yield, and low cost. But the a-Si:H TFT’s mobility is very low, so it can’t be implement for the purpose of System-On-Panel (SOP). The next generation LCD will combine the drive circuit on the panel for cost down, and it will use the devices with higher mobility, like low temperature poly-silicon thin film transistor (LTPS TFT). It is hard to develop the LTPS TFT model because the process of LTPS TFT is not stable, and the characteristic of the device is different. So far as the RPI model can be referenced in the industry. For the disamenities of hard to development, we present a test structure to measurement device and analog integrated circuits. To observe the circuit’s performance. There are three topics in the test structure, which are the devices, subcircuit and analog integrated circuit. After the Layout, manufacture and package, we use the semiconductor parameter analysis measurement to measure the characteristic of the devices and subcircuit. The measurement of the analog integrated circuit use power supply, signal generators and oscilloscopes to observe the output waveform. Finally we gather statistics and analysis the data, and modeling with probability model, use the Monte Carlo analysis to verify with the designed circuit.
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45

楊子明. "Fabrication and Characterization of High Performance NILC LTPS Nanowire TFTs using Ni-Gettering." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/47797240542309690009.

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Abstract:
碩士
國立交通大學
工學院碩士在職專班半導體材料與製程設備組
97
In this thesis, fabrication and characterization of high performance NILC LTPS nanowire TFTs using Ni-gettering has been studied. Initially, we employ LTPS NILC technology to fabricate TFTs with poly-Si nanowire channels. It’s a simple method and low-cost process to manufacture the nanowire channels. The feature of process was the method of forming sidewall spacer of MOSFET. Simultaneously, we define source/drain and self-alignment form the poly-Si sidewall spacer nanowire channels for the bottom-gate TFT. Thus, we can simply control the width of sidewall spacer nanowire channel around 70 nm by etching condition. Moreover, due to NILC Poly-Si, residual Ni trapped by the grain boundaries and defects leads to introduce deep level states and results in degradation of the device performance. Therefore, in order to solve this issue, we develop a simple and effective gettering method to reduce the Ni-metal impurity contamination of the NILC poly-Si. Finally, we execute the NH3 plasma treatment to further improve the device performance. Through this way, we reveal that the NH3 plasma treatment can effectively improve the device performance, such as passivate the defects, reduce leakage current, enhance carrier mobility, increase on/off current ratio, and better subthreshold swing, etc.
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46

Chou, Tse-Heng, and 周澤亨. "Studies of Novel SiCN Ultraviolet Light Detectors and LTPS Mass Application Hydrogen Sensors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19081000956064163240.

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Abstract:
博士
國立成功大學
微電子工程研究所碩博士班
97
In this dissertation, we report the investigations of novel SiCN ultraviolet light detectors and LTPS (low temperature polysilicon) low cost hydrogen sensors. Four type structures including n-SiCN/p-PS/p-Si heterojunction, n-SiCN/p-SiCN homojunction, and n-SiCN/i-SiCN/p-SiCN and n-SiCN/i-SiCN/p-Si junctions, have been developed. Firstly, we study the n-SiCN/p-silicon heterojunction with porous silicon (PS) buffer layer for low cost and high temperature ultraviolet (UV) detecting applications. The PS layer and the cubic crystalline n-SiCN film were formed on the top of p-(100) silicon substrate by the electrochemical anodization and rapid thermal chemical vapor deposition (RTCVD) sequentially. The PS layer has a high resistivity to suppress the dark current, and provides sponge-like structure to limit strain and cracks development after the post growth cooling, thus favoring nucleation to result a better single crystal SiCN film. Consequently, the developed optical sensing device has a high room temperature (25 °C) photo/dark current ratio (PDCR) 85.4 with and without irradiation of and 254 nm UV light with 0.5 mW/cm2 optical power. Even though at 200 °C the ratio is still equal to 7.42. These results are better than the reported ZnO on GaAs substrate or β-SiC on Si substrate UV detectors without porous treatment. Next, a novel n-SiCN/p-SiCN homojunction was developed on Si substrate with RTCVD for low cost and high performance ultraviolet detecting applications. The current ratio of the junction under -5 V bias, with and without irradiation of 254 nm UV light are 1940, and 96.3 at room temperature, and 175 °C, respectively. Compared to the reported UV detectors with material of 4H-SiC or β-SiC, the developed n-SiCN/p-SiCN homojunction has better current ratio in both room and elevated temperature. To raise the detector’s PDCR, both n-SiCN/i-SiCN/p-SiCN and n-SiCN/i-SiCN/p-Si junctions were developed. The measured PDCR of n-SiCN/i-SiCN/p-SiCN and the n-SiCN/i-SiCN/p-Si junctions with and without irradiation of 254 nm UV light under -5 V bias and 0.5 mW/cm2 are 150.26 and 5.42, respectively. Compared to the reported UV detectors with 4H-SiC or β-SiC (3C-SiC), the developed n-SiCN/i-SiCN/p-SiCN homojunction has the better current ratio in both room and high temperatures. Additionally, the Pd/n-LTPS (MS) and Pd/TiO2/n-LTPS (MOS) Schottky diodes fabricated on a glass substrate for hydrogen sensing are reported. On the other hand, we also investigate the hydrogen detecting performance of Pd/n-LTPS/glass thin film Schottky diodes. The n-LTPS (n-type low temperature polysilicon) is an excimer laser annealed (ELA) and PH3 gas plasma treated amorphous silicon (a-Si) thin film. In addition, we used a TiO2 interface layer to improve hydrogen sensing ability significantly. At room temperature and -2 V bias, the developed MOS Schottky diode exhibited a high signal ratio of 1539.6% to 50 ppm of hydrogen gas, with a fast response time of 40 sec, respectively. The signal ratio is better or comparable with that of other reported MOS type hydrogen gas sensors prepared on Si or III-V compound substrate. Furthermore, the signal ratio is 7.6, 14, and 30 times over other interfering gases of C2H5OH, C2H4, and NH3 at room temperature and a concentration of 8000 ppm at -2 V bias, respectively. Thus, the developed MOS Schottky diode shows promise for the future development and commercialization of a low cost hydrogen sensor.
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47

Chiu, Chih-Chieh, and 邱志杰. "System-On-Panel Applications with Embedded Metal-Nitride-Oxide LTPS TFT Nonvolatile Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/54826963095107509332.

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Abstract:
碩士
國立清華大學
電子工程研究所
96
In this study, a nonvolatile memory realized by fully-compatible LTPS process is investigated for various novel applications. For data storage, the embedded N-channel Metal-Nitride-Oxide-Silicon (MNOS) One-Time-Programmable (OTP) cell arranged in a NOR array architecture is demonstrated. Furthermore, fast program efficiency and high disturb immunity are obtained by divided voltages on wordline (WL) and bitline (BL). Through channel FN programming, superior data retention as well as low power operation are therefore achieved. The new embedded MNOS cell has provided a promising one-time-programming memory solution on the LTPS panels’ applications. For AMOLED (Active Matrix Organic Light-Emitting Displays), the proposed innovative current boosting scheme can adjust the threshold voltage level of a P-channel TFT in the OLED driver circuit. Thus, the uniformity of the driving current can be greatly improved without any change on the conventional 2-TFTs and 1-capacitor pixel circuit. The mura recovery of operation can be performed during product testing steps without any external memory modules or additional compensation circuits. This current boosting scheme has been successfully verified in a 2.4-inch AMOLED panel with significant uniformity enhancement.
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48

Hu, Yu-fan, and 胡瑀梵. "Performance Improvement on Sub-Micron LTPS P-Type TFTs using Fluorine Implantation Treatment." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/a6km62.

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Abstract:
碩士
國立臺灣科技大學
電子工程系
99
In this thesis, the performance improvement of the sub-micron LTPS p-type TFTs with the fluorine implantation treatment was investigated. The method of this thesis was that using the pad oxide prevents the damage of the channel surface while the channel was treated with the fluorine implantation. When the source and drain were activated, the fluorine ions will diffuse and accumulate at the channel interface. Then, due to the formation of the strong Si-F bonds, it would suppress the hot carrier multiplication near drain side and the short channel effect in the sub-micron LTPS p-type TFTs. Thus, the electrical characteristics and reliability of the proposed the sub-micron LTPS p-type TFTs were improved effectively, especially for field effect mobility and on/off current ratio. Besides, we found an issue, the traps in the channel and the resistances of the channel were two factors which influence the on-current of the device. Without the fluorine implantation treatment, the traps in the channel layer would influence the on-current of the device for the different channel thickness. In contrast, after using fluorine implantation treatment, the resistances of the different channel layer would influence the on-current of the device because of the reduction of the traps in the channel.
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49

Guo, Bo-Liang, and 郭柏良. "The New Voltage Programming Pixel Circuit with LTPS-TFTs Driving for AMOLED Displays." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/t979us.

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Abstract:
碩士
國立臺灣科技大學
電子工程系
100
Active matrix organic light-emitting diode (AMOLED) has recently attracted much attention due to its high brightness, light weight, fast response-time, and wide viewing angle. Low-temperature polycrystalline-silicon (LTPS) thin-film transistors (LTPS-TFTs) have been widely considered as pixel elements for AMOLED due to their high current-driving capability. The high electron mobility of LTPS-TFTs can achieve larger aperture ratio for a given pixel size of AMOLED and a higher resolution display to get the better image quality. Furthermore, a very light-weight display with few external interconnections is possible, because the peripheral circuits and the pixel driver circuits both using LTPS-TFTs can be integrated onto the same substrate. However, the LTPS-TFTs still have the issue of non-uniformity of threshold voltage due to the excimer laser annealing (ELA) process. In the conventional two-TFTs pixel circuit for AMOLED, various threshold voltages of driving TFT (DTFT) cause the non-uniform gray-scale over the display area. In addition, the long time operation for OLED will cause the brightness to drop off as the OLED threshold voltage degradation. Therefore, in order to overcome the above-mentioned issues, we have proposed three novel voltage-modulated structures for AMOLED pixel circuit as 5T1C, 5T1C* and 6T1C. These circuits can compensate both the DTFT threshold voltage deviation and the OLED degradation. The proposed circuits are also verified by SPICE simulator. In the 5T1C simulation, results show that the average OLED current error rate under ΔVTH = ±0.33 V is 0.5%, the average OLED current error rate underΔVTH_O = +0.33 V is 10% and the average current error rate under IR Drop voltage = 0.3 V is 8%. It can effectively reproduces almost identical OLED current regardless of the DTFT threshold voltage deviation and OLED degradation. In the 5T1C* simulation results show that the average OLED current error rate under ΔVTH = ±0.33 V is 0.8%, the average OLED current error rate underΔVTH_O = +0.33 V is 4.7% and the average current error rate under IR Drop voltage = 0.3 V is 5.8%. It can effectively reproduces almost identical OLED current regardless of the DTFT threshold voltage deviation and OLED degradation. In the 6T1C simulation results show that the average OLED current error rate under ΔVTH = ±0.33 V is 3.7%, and the average current error rate under IR Drop voltage = 0.3 V is 8.9%. It can effectively reproduces almost identical OLED current regardless of the DTFT threshold voltage deviation and OLED degradation. The above results show that the image non-uniformity of AMOLED can be effectively improved at the same time by compensating the DTFT threshold voltage deviation and the OLED threshold voltage degradation. Thus, we believe that the proposed pixel circuit design has very high driving capability and is a promising candidate for the large size, high resolution AMOLED panels.
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50

Chou, Yen-Pang, and 周彥邦. "Statistical Study on the Characteristics and Reliability Behaviors of N-type LTPS TFTs." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/yv566u.

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Abstract:
碩士
國立交通大學
光電工程系所
94
Low Temperature Polycrystalline Silicon (LTPS) thin film transistors (TFTs) have attracted much attention in the application on the integrated peripheral circuits of display electronics such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to its better current driving compared with a-Si (amorphous silicon) TFTs. In this thesis, the variation characteristics of LTPS TFTs are statistically investigated. The differences of the threshold voltage and mobility with the same device distance are further studied. The difference shows the distribution much centered than the Gaussian distribution and a proper model is proposed to describe the variation behaviors with difference device distances, for which the R squares (Coefficient of Determination) are higher than 0.95, reflecting the validity of the model. Furthermore, the proposed models are used to simulate the performance of the differential pair, which is commonly used in driving of the panel. Simulation results show the effects of the variation behavior on the estimation of the circuit performance. Finally, the reliability of LTPS TFTs is studied in form of stress map by adopting the crosstie layout TFTs to get the more consistent reliability behaviors. This database of reliability is very helpful to evaluate the lifetime and operation conditions of LTPS TFTs.
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