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Journal articles on the topic 'Lut block'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Kubica, Marcin, and Dariusz Kania. "Technology Mapping of FSM Oriented to LUT-Based FPGA." Applied Sciences 10, no. 11 (2020): 3926. http://dx.doi.org/10.3390/app10113926.

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The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output fun

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2

Zia, Razia, Muzaffar Rao, Arshad Aziz, and Pervez Akhtar. "Efficient Utilization of FPGA Using LUT-6 Architecture." Applied Mechanics and Materials 241-244 (December 2012): 2548–54. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2548.

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Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions

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Amirhassankhani, Fatemeh, Baba Senowbari-Daryan, and Koorosh Rashidi. "Upper Triassic (Norian-Rhaetian) Foraminifera from the Nayband Formation of the Lut Block (Garm Ab section, Northeast Iran)." Carnets de géologie (Notebooks on geology) 23, no. 4 (2023): 77–95. http://dx.doi.org/10.2110/carnets.2023.2304.

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Studies of Nayband Formation from the Garm Ab section in Lut Block in Central Iran led to the identification of 26 foraminiferal taxa. Nine species are reported from Iran for the first time: Involutina ex gr. liassica (Jones), Involutina sp., Lamelliconus permodiscoides (Oberhauser), Palaeolituonella cf. meridionalis (Luperto), Palaeolituonella cf. angulata Senowbari-Daryan & Cacciatore, Gaudryinella cf. kotlensis Trifonova, Ammobaculites eumorphos Kristan-Tollmann, Frondicularia rhaetica Kristan-Tollmann, Frondicularia cf. xiphoidea Kristan-Tollmann, and Orthotrinacria ? expansa (Zaninett

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Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits." Electronics 11, no. 6 (2022): 950. http://dx.doi.org/10.3390/electronics11060950.

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One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to reduce the LUT count of three-block circuits of Mealy FSMs. The method is based on finding a partition of set of internal states by classes of compatible states. To reduce the LUT count, we propose a special kind of state code, named complex state codes. The complex codes include two parts. The first part includes the

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Manasi, R. Mali* Dr. S.D Pable Prof R.S Khule. "PERFORMANCE OPTIMIZATION OF LUT IN FPGA USING CNFET." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 761–67. https://doi.org/10.5281/zenodo.60127.

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A Leakage power dissipation is becoming a concern in field-programmable gate arrays (FPGAs) due to scaling in FPGA technology. Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of FPGAs (which arises due to their flexible structure), make them less appealing for extreme low power applications hence it is important to investigate ways of reducing FPGA power consumption. This paper proposes an energy efficient dual-threshold CarbonNanotube Field Effect Transistor (CNFET) based architecture of

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Hu, Yuzhu, Xiaoye Chen, Zongyuan Li, Songping Zheng, and Yongzhong Cheng. "Thermosensitive In Situ Gel Containing Luteolin Micelles is a Promising Efficient Agent for Colorectal Cancer Peritoneal Metastasis Treatment." Journal of Biomedical Nanotechnology 16, no. 1 (2020): 54–64. http://dx.doi.org/10.1166/jbn.2020.2870.

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Luteolin (Lut) is a natural flavonoid mainly extracted from vegetables and fruits. Lut shows great anti-tumor potential in many malignant cancers, which are hindered by poor water solubility and low bioavailability. Peritoneal metastasis is a challenge for colorectal cancer treatment, usually indicating unfavorable prognosis of patients. Methoxy poly(ethylene glycol)-poly(ε-caprolactone) micelles containing Luteolin (Lut-M) and thermosensitive Pluronic®F127 coated Lut-M (Lut-M-F127) were synthesized and applied in the local therapy of colorectal cancer. Drug release study of Lut-M-F127 and Lut

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Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment." Electronics 10, no. 8 (2021): 901. http://dx.doi.org/10.3390/electronics10080901.

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Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The propose

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Staworko, Michał, and Mariusz Rawski. "Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures." International Journal of Electronics and Telecommunications 58, no. 4 (2012): 335–44. http://dx.doi.org/10.2478/v10177-012-0046-y.

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Abstract Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomp

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Barkalov, Alexander, Larysa Titarenko, and Kamil Mielcarek. "Transforming Group Codes in Mealy Finite State Machines with Composite State Codes." Applied Sciences 15, no. 8 (2025): 4289. https://doi.org/10.3390/app15084289.

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A new state assignment method focusing on Mealy finite state machines (FSMs) is proposed. The proposed codes are an alternative to composite state codes (CSCs). CSCs are represented as concatenations of group codes and partial state codes. Both group and partial state codes are maximum binary codes. We propose encoding groups using one-hot codes. The main goal of this method is improving the value of the FSM cycle time without a significant degradation of the spatial characteristics. The method can be applied if FSM circuits are implemented using the look-up table (LUT) elements of field-progr

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Barkalov, Alexandr, Larysa Titarenko, Oleksandr Golovin, and Oleksandr Matvienko. "Address Translation in a Compositional Microprogram Control Unit." Cybernetics and Computer Technologies, no. 2 (June 6, 2025): 88–100. https://doi.org/10.34229/2707-451x.25.2.8.

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Introduction. Digital systems consist of combinational and sequential blocks. The most important sequential blocks include control units. Control unit circuits are not typical library components of CAD systems. Due to it, the designing a control unit circuit is a more labor-intensive process than implementing systems with such common blocks as registers, counters, arithmetic and logic blocks. The purpose of the article. When implementing digital systems, problems arise in optimizing their characteristics. This paper considers the problem of reducing hardware costs in the circuits of compositio

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Barkalov, Alexander, Larysa Titarenko, and Kazimierz Krzywicki. "Improving Hardware in LUT-Based Mealy FSMs." Applied Sciences 12, no. 16 (2022): 8065. http://dx.doi.org/10.3390/app12168065.

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The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the

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Singhal, Subodh Kumar, and Basant Kumar Mohanty. "Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic." Journal of Circuits, Systems and Computers 25, no. 07 (2016): 1650073. http://dx.doi.org/10.1142/s0218126616500730.

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In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixe

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Barkalov, Alexandr, Larysa Titarenko, Oleksandr Golovin, and Oleksandr Matvienko. "Optimization of the Microprogram Mealy Machine Circuit Based on LUT and EMB." Cybernetics and Computer Technologies, no. 2 (June 9, 2024): 87–100. http://dx.doi.org/10.34229/2707-451x.24.2.9.

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Introduction. A digital system is a collection of combinational and sequential blocks. Sequential blocks can be divided into library and non-standard classes. The first class includes, for example, counters or shift registers. To implement the circuits of such blocks, standard CAD programs are used. And for the second class, which is the control unit (CU), there are no standard library solutions. This explains the relevance of methods for synthesis and optimization of circuits of non-standard sequential blocks, such as CU. When synthesizing a finite state machine (FSM) circuit, a number of opt

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Barkalov, Alexander, Larysa Titarenko, and Kazimierz Krzywicki. "Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs." Electronics 11, no. 19 (2022): 3089. http://dx.doi.org/10.3390/electronics11193089.

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A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes. The second core uses extended state codes. Such an approach allows reducing the number of LUTs in the block of state codes’ transformation. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each partial fun

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Yang, Wu, Milad Tanavardi Nasab, and Himanshu Thapliyal. "Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications." Electronics 13, no. 7 (2024): 1309. http://dx.doi.org/10.3390/electronics13071309.

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Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is

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ESHRAGHI, Hassan, Ebrahim RASTAD, and Kamran MOTEVALI. "Auriferous sulfides from Hired gold mineralization, South Birjand, Lut block, Iran." Journal of Mineralogical and Petrological Sciences 105, no. 4 (2010): 167–74. http://dx.doi.org/10.2465/jmps.070414b.

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Chowdari Ch, Pratyusha, and J. B. Seventline. "Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures." F1000Research 12 (September 21, 2023): 1182. http://dx.doi.org/10.12688/f1000research.126067.1.

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Background: This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures for a general filter (without symmetry) and two symmetrical filters (diagonal and quadrantal symmetry) are implemented. The proposed architectures need fewer multipliers because of the symmetry of the filter coefficients. Methods: A distributed arithmetic (DA)- based multiplication method is used in the proposed architecture. A dual-port memory-based lookup table (DP-MLUT) is used in the multiplication instead of lookup-table

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Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.

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This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distribute

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Yu Hu, S. Das, S. Trimberger, and Lei He. "Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 4 (2009): 591–95. http://dx.doi.org/10.1109/tcad.2009.2014001.

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Mohanty, Basant K., Pramod Kumar Meher, and Sujit K. Patel. "LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 5 (2016): 1926–35. http://dx.doi.org/10.1109/tvlsi.2015.2472964.

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Rakanovic, Damjan M., Vuk Vranjkovic, and Rastislav J. R. Struharik. "Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning." Elektronika ir Elektrotechnika 27, no. 3 (2021): 57–70. http://dx.doi.org/10.5755/j02.eie.28922.

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Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelera

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Barkalov, Alexandr, Larysa Titarenko, Svitlana Saburova, Oleksandr Golovin, and Oleksandr Matvienko. "Optimization of the Microprogram Mealy Machine Circuit Based on LUT and EMB." Cybernetics and Computer Technologies, no. 4 (December 18, 2024): 121–33. https://doi.org/10.34229/2707-451x.24.4.11.

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Introduction. The control unit is the most important block of digital systems. Unlike other blocks, the control unit generates signals in each cycle of the system and therefore consumes a significant amount of electrical power. Currently, the problem of reducing power consumption is of particular importance. FPGA (field-programmable logic array) chips are widely used in the implementation of various digital systems. According to experts, these chips will be widely used in the design of digital devices for several decades to come. This factor determines the choice of this particular element bas

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Peroumal, Vijayakumar, Rajashree R, Anusha Kulkarni, and Prachi Thakur. "FPGA Implementation of Secure Block Creation Algorithm for Blockchain Technology." ECS Transactions 107, no. 1 (2022): 5519–31. http://dx.doi.org/10.1149/10701.5519ecst.

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Blockchain technology is essential to secure storage, authenticate data, and protect information from being misused and exploitation. Traditional methods of securing data using cryptographic algorithms include hashing functions like SHA-0, SHA-1, which have limitations like excess computational time, collision attacks, scalability, backtracking to retrieve the original message, etc. Using a combination of RSA and SHA together allows us to create a block on an FPGA, which when combined with other blocks establishes an encrypted Blockchain, which overcomes such limitations. Synthesis and impleme

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Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving Temporal Characteristics of Mealy FSM with Composite State Codes." Electronics 14, no. 7 (2025): 1406. https://doi.org/10.3390/electronics14071406.

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In this paper, we proposed a new state assignment method focusing on Mealy finite state machines (FSMs). The method makes it possible to improve the temporal characteristics of the circuits of FSMs, the internal states of which are encoded by the composite state codes (CSCs). These codes consist of class codes and partial state codes. Both class and partial state codes are maximum binary codes. We propose to encode classes by one-hot codes. The main goal of the method is improving the value of the FSM cycle time without any significant degradation of spatial characteristics. The method can be

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Behdani, Ensieh, Fatemeh Hadani, Marziyeh Notghi Moghaddam, and Ahmadreza Khazaei. "Calcareous nannofossil biostratigraphy of Baghamshah Formation in Eastern Iran, Lut Block (Birg Section)." Revista Brasileira de Paleontologia 25, no. 1 (2022): 51–60. http://dx.doi.org/10.4072/rbp.2022.1.04.

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Biostratigraphic studies of the Baghamshah Formation from the Birg section in the northwest of Birjand (Lut Block) are done here for the first time based on the calcareous nannofossils. In the studied section, 82 samples were taken, and smear slides were prepared. The examination of the collected samples resulted in the identification of 65 calcareous nannofossil and 11 didemnid ascidian spicules species belonging to 38 genera corresponding from CC1 to CC4b biozones with the age of early Berriasian to early Hauterivian, according to the Sissingh biozonation. The calcareous nannofossil assembla

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Babazadeh, S. A., and M. Soltani Najafabadi. "Biostratigraphy of Eocene Sedimentary Rocks Based on Alveolina in East Lut Block, Iran." Kharazmi Journal of Earth Sciences 1, no. 1 (2015): 1–20. http://dx.doi.org/10.29252/gnf.1.1.1.

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Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving Characteristics of FPGA-Based FSMs Representing Sequential Blocks of Cyber-Physical Systems." Applied Sciences 13, no. 18 (2023): 10200. http://dx.doi.org/10.3390/app131810200.

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This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of output collections are discussed. The method is based on using two LUT-based cores to implement systems of partial Boolean functions. One of the cores uses only maximum binary codes, while the second core is based on the use of extended state codes. The hardware reduction is based on diminishing the number of transformed maximum binary codes. This lead

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P., Indira. "DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR." International Journal of VLSI design & Communication Systems (VLSICS) 10, no. 5 (2019): 01–18. https://doi.org/10.5281/zenodo.3529340.

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Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fun

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Azzad, Bader Saeed. "Elevator controller based on implementing a random access memory in FPGA." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1053–62. https://doi.org/10.11591/ijece.v11i2.pp1053-1062.

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Previous techniques of elevator controllers suffer from two main challenges: processing time, and software size. In this work these challenges have been overcame by implementing a controller random access memory (RAM) in a fast FPGA for a proto-type of two-floors elevator, as known the RAM and FPGA are fast devices. A look-up-table LUT (which is fast technique) has been proposed for this work, this LUT has represented a proposed relation between 10 and 7 lines, the states of the sensors and switches have been represented by the 10 input lines, and the commands for the motors of slide door and

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Waseem, Khan, and Mirwani Mahnoor. "PROBING THE NATURE AND CHARACTERISTICS OF ACTIVE MUD VOLCANIC CLUSTERS IN MAKRAN COASTAL ZONE, PAKISTAN." International Journal of Research - Granthaalayah 8, no. 3 (2020): 214–22. https://doi.org/10.5281/zenodo.3734249.

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Makran Subduction Zone is formed in Late Cretaceous. It is divided into Eastern Makran at the southern edge of Helmand Block in Pakistan and the Western Makran at the southern edge of Lut Block in Iran. The velocity of convergence in Eastern and Western Makran are 42.0 mm/yr and 35.6 mm/yr repectively. Both segments are bound by strike-slip faults e.g. Ornach-Nal left lateral fault in the east and Minab right lateral in the west. Stratigraphically, the zone comprises Formations of ages ranging from Cretaceous to Holocene. In the Eastern Makran, most of the mud volcanoes are located along strik

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Trang, Hoang, and Nguyen Van Loi. "Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm." International Journal of Distributed Systems and Technologies 4, no. 1 (2013): 56–77. http://dx.doi.org/10.4018/jdst.2013010105.

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This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the autho

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Khosravi, Vahid, Aref Shirazi, Adel Shirazy, Ardeshir Hezarkhani, and Amin Beiranvand Pour. "Hybrid Fuzzy-Analytic Hierarchy Process (AHP) Model for Porphyry Copper Prospecting in Simorgh Area, Eastern Lut Block of Iran." Mining 2, no. 1 (2021): 1–12. http://dx.doi.org/10.3390/mining2010001.

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The eastern Lut block of Iran has a high potential for porphyry copper mineralization due to the subduction tectonic regime. It is located in an inaccessible region and has harsh arid conditions for traditional mineral exploration campaigns. The objective of this study is to use Advanced Spaceborne Thermal Emission and Reflection Radiometer (ASTER) remote sensing data for porphyry copper exploration in Simorgh Area, eastern Lut block of Iran. Hydrothermal alteration zones such as argillic, phyllic and propylitic zones associated with porphyry copper systems in the study were identified using f

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SHARIFI, Javad, Seyed Naser RAISOSSADAT, Maryam MORTAZAVI MEHRIZI, and Maryam MOTAMEDALSHARIATI. "Albian and Cenomanian ammonites of the eastern margin of the Lut block (East Iran)." Carnets de géologie (Notebooks on geology) 16, no. 25 (2016): 591–613. http://dx.doi.org/10.4267/2042/61850.

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Bröcker, Michael, Gholamreza Fotoohi Rad, Fateme Abbaslu, and Nikolay Rodionov. "Geochronology of high-grade metamorphic rocks from the Anjul area, Lut block, eastern Iran." Journal of Asian Earth Sciences 82 (March 2014): 151–62. http://dx.doi.org/10.1016/j.jseaes.2013.12.021.

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Moghimi, Ebrahim. "Comparative Study of Changing Drainage Basin System with Tectonic Forms, Case Study: Lut Block, Iran." American Journal of Applied Sciences 6, no. 6 (2009): 1270–76. http://dx.doi.org/10.3844/ajassp.2009.1270.1276.

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biabangard, habib, Ali Ahmadi, and Shahnaz Rimaz. "Petrology, Geochemistry and Thermobarometery of Abraq-Harmak Volcanic rocks, west of Lut block, Central Iran." Researches in Earth Sciences 10, no. 3 (2019): 45–64. http://dx.doi.org/10.52547/esrj.10.3.45.

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Akbari, AA, A. Malekzadeh Shafaroudi, and MH Karimpour. "Geology, alteration, mineralogy, texture and geochemistry studies in Ghoochi gold prospect, eastern Bajestan, Lut Block." Iranian Journal of Crystallography and Mineralogy 30, no. 3 (2022): 475–88. http://dx.doi.org/10.52547/ijcm.30.3.475.

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Arjmandzadeh, R., M. H. Karimpour, S. A. Mazaheri, J. F. Santos, J. M. Medina, and S. M. Homam. "Sr–Nd isotope geochemistry and petrogenesis of the Chah-Shaljami granitoids (Lut Block, Eastern Iran)." Journal of Asian Earth Sciences 41, no. 3 (2011): 283–96. http://dx.doi.org/10.1016/j.jseaes.2011.02.014.

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Khalatbari Jafari, Morteza, Zinat Kilani Jafari Sani, and Jafar Omrani. "Petrology and Geochemistry of the Eocene Volcanic Rocks in the West of Sechangi, Lut Block." Kharazmi Journal of Earth Sciences 5, no. 1 (2019): 19–54. http://dx.doi.org/10.29252/gnf.5.1.19.

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Asghar, Ali, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, and Muhammad Rashid. "Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing." International Journal of Reconfigurable Computing 2017 (2017): 1–9. http://dx.doi.org/10.1155/2017/7021056.

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In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of confi

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Rajesh, A., Basha SK Jameer, Xavier Francis, and Babu S. Hari. "A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 217–20. https://doi.org/10.35940/ijitee.L7985.1091220.

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This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as com

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Madasamy, Rajmohan, and Himanshu Shekhar. "Design of parallel and pipelined DA based OBC fir filter for software defined radio." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 3 (2019): 1228. http://dx.doi.org/10.11591/ijeecs.v14.i3.pp1228-1234.

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Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with th

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Irfan, Muhammad, Zahid Ullah, and Ray C. C. Cheung. "Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs." Electronics 8, no. 5 (2019): 584. http://dx.doi.org/10.3390/electronics8050584.

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Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in findin

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Morasa, Balaji, and Padmaja Nimmagadda. "Low power residue number system using lookup table decomposition and finite state machine based post computation." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 127. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp127-134.

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In this paper, memory optimization and architectural level modifications are introduced for realizing the low power <span lang="EN-US">residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The r

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ABDI, Maryam, and M. H. KARIMPOUR. "Petrochemical Characteristics and Timing of Middle Eocene Granitic Magmatism in Kooh-Shah, Lut Block, Eastern Iran." Acta Geologica Sinica - English Edition 87, no. 4 (2013): 1032–44. http://dx.doi.org/10.1111/1755-6724.12108.

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Ghasemi-Rozveh, T., M. M. Khatib, A. Yassaghi, and E. Gholami. "Geodynamics and underlying bedrock of the magnetically active crust layer of the Lut block, Eastern Iran." Geotectonics 50, no. 3 (2016): 327–35. http://dx.doi.org/10.1134/s0016852116030055.

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Yarahmadzahi, Hamed, Daniel Vachard, and Mohammad Nabi Gorgij. "First record of Sakmarian smaller foraminifers from the Sarab section (South Lut Block in Central Iran)." Arabian Journal of Geosciences 8, no. 5 (2014): 3119–27. http://dx.doi.org/10.1007/s12517-014-1431-x.

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Mirnejad, H., G. H. Blourian, M. Kheirkhah, M. A. Akrami, and F. Tutti. "Garnet-bearing rhyolite from Deh-Salm area, Lut block, Eastern Iran: anatexis of deep crustal rocks." Mineralogy and Petrology 94, no. 3-4 (2008): 259–69. http://dx.doi.org/10.1007/s00710-008-0015-4.

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Guo, Jing-Ming. "High efficiency ordered dither block truncation coding with dither array LUT and its scalable coding application." Digital Signal Processing 20, no. 1 (2010): 97–110. http://dx.doi.org/10.1016/j.dsp.2009.04.007.

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Sharifi, Javad, Seyed Naser Raisossadat, Maryam Mortazavi Mehrizi, and Maryam Motamedalshariati. "Carbon Isotope Stratigraphy of the Uppermost Aptian–Lower Cenomanian Strata from the Lut Block, East Iran." Journal of Earth Science 34, no. 6 (2023): 1793–99. http://dx.doi.org/10.1007/s12583-023-1911-4.

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