Relevant bibliographies by topics / LVTSCR

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Conference papers

Academic literature on the topic 'LVTSCR'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 February 2022

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Journal articles on the topic "LVTSCR"

1

Chen, Shen Li, and Chun Ju Lin. "Evaluation of ESD/LU Reliabilities by Different SCR Layout Types in a 0.35μm 3.3V CMOS Process." Advanced Materials Research 779-780 (September 2013): 1124–29. http://dx.doi.org/10.4028/www.scientific.net/amr.779-780.1124.

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This paper aimed at the evaluation of layout dependence on ESD/LU reliabilities in the 0.35μm 3.3V low-voltage triggered silicon-controlled-rectifier (LVTSCR) DUTs. In this work, the parameter of channel L in a pMOS and the parameter S of an SCR are varied to study the influence on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2), respectively. Eventually, it can be found that the layout illustration of type-2 has a higher It2than that of type-1, i.e., the ratio of (It2)type-2/(It2)type-1> 3 among all the LVTpSCRs. Meanwhile, the holding voltage of all SCR devices are latch-up free while operated at 3.3V. Therefore, the type-2 layouts of SCR devices are so excellent structure in the ESD/LU reliability considerations for this 0.35μm 3.3V CMOS process.
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Chen, Shen Li, and Der Ann Fran. "Implementation of ESD Protection for Output Driver ICs with SCR Circuits Techniques." Applied Mechanics and Materials 464 (November 2013): 139–44. http://dx.doi.org/10.4028/www.scientific.net/amm.464.139.

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In this paper, an output driver which drove a large current in DC brushless fan ICs was taken for the HBM ESD stress. The protection circuits of this IC were also designed to improve ESD robustness by various layout parameters and structures. From the ESD testing results, it was found that the positive Pad-to-VSS (PS) zapping mode was weakest for the output driver of DC brushless fan ICs during ESD stress. Eventually, protection circuits with a complementary low-voltage-triggered SCR (LVTSCR) were used to protect the whole-chip ESD stress. After a systematic improvement, an SCR structure of adding protection circuits can effectively protect the whole-chip ESD reliability, as compared with the original DUT; the ESD failure threshold (VESD) of PS mode is increased 314% in a best structure when an LVTSCR with the drain-tap S space is 4μm.
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Li, Li, Hongxia Liu, Cui Dong, and Wen Zhou. "Characterization analysis of UDSM LVTSCR under TLP stress." Journal of Semiconductors 32, no. 5 (May 2011): 054002. http://dx.doi.org/10.1088/1674-4926/32/5/054002.

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Ming-Dou Ker, Chung-Yu Wu, and Hun-Hsien Chang. "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI." IEEE Transactions on Electron Devices 43, no. 4 (April 1996): 588–98. http://dx.doi.org/10.1109/ted.1996.1210725.

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Vashchenko, V., A. Concannon, M. ter Beek, and P. Hopper. "LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits." Microelectronics Reliability 43, no. 1 (January 2003): 61–69. http://dx.doi.org/10.1016/s0026-2714(02)00125-7.

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Zhu, Ling, Hai-Lian Liang, Xiao-Feng Gu, and Jie Xu. "Design of a novel high holding voltage LVTSCR with embedded clamping diode." Chinese Physics B 29, no. 6 (June 2020): 068503. http://dx.doi.org/10.1088/1674-1056/ab836e.

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Lee, Joo-Young. "Analysis of SCR, MVSCR, LVTSCR With I-V Characteristic and Turn-On-Time." Journal of IKEEE 20, no. 3 (September 30, 2016): 295–98. http://dx.doi.org/10.7471/ikeee.2016.20.3.295.

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Guilhaume, A., P. Galy, JP Chante, B. Foucher, and F. Blanc. "Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges." Microelectronics Reliability 41, no. 9-10 (September 2001): 1433–37. http://dx.doi.org/10.1016/s0026-2714(01)00175-5.

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Vashchenko, V. A., A. Concannon, M. terBeek, and P. Hopper. "High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps." IEEE Transactions on Device and Materials Reliability 4, no. 2 (June 2004): 273–80. http://dx.doi.org/10.1109/tdmr.2004.826584.

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Li, Li, and Hongxia Liu. "A novel double-trench LVTSCR used in the ESD protection of a RFIC." Journal of Semiconductors 32, no. 10 (October 2011): 104005. http://dx.doi.org/10.1088/1674-4926/32/10/104005.

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Dissertations / Theses on the topic "LVTSCR"

1

Běťák, Petr. "Modelování a návrh ESD ochran v integrovaných obvodech." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-233447.

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The thesis introduces new semiconductor structures that are used as protections against Electrostatic Discharge occuring in integrated circuits. The fundamental structure for modeling and simulation has been lateral Silicon Controlled Rectifier. This SCR structure has been modificated to enable tuning of the triggering and holding voltages by changing geometrical mask dimensions. On the base of modeling and simulation the new proposed structures have been published. Also several protection structures have been designed to be manufactured and measured on a testchip. The final electrical behavior has been verified by measurement. Finally, the focus has been aided to protection circuit with bipolar transistor. This approach has been also simulated and verified by measurement. Advantages and disadvantages of the proposed protection structures are commented in the thesis.
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Kar, Rahul. "Diagnostics of subsynchronous vibrations in rotating machinery - methodologies to identify potential instability." Thesis, Texas A&M University, 2005. http://hdl.handle.net/1969.1/2596.

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Rotordynamic instability can be disastrous for the operation of high speed turbomachinery in the industry. Most ??instabilities?? are due to de-stabilizing cross coupled forces from variable fluid dynamic pressure around a rotor component, acting in the direction of the forward whirl and causing subsynchronous orbiting of the rotor. However, all subsynchronous whirling is not unstable and methods to diagnose the potentially unstable kind are critical to the health of the rotor-bearing system. The objective of this thesis is to explore means of diagnosing whether subsynchronous vibrations are benign or have the potential to become unstable. Several methods will be detailed to draw lines of demarcation between the two. Considerable focus of the research has been on subharmonic vibrations induced from non-linear bearing stiffness and the study of vibration signals typical to such cases. An analytical model of a short-rigid rotor with stiffness non-linearity is used for numerical simulations and the results are verified with actual experiments. Orbits filtered at the subsynchronous frequency are shown as a diagnostic tool to indicate benign vibrations as well as ??frequency tracking?? and agreement of the frequency with known eigenvalues. Several test rigs are utilized to practically demonstrate the above conclusions. A remarkable finding has been the possibility of diagnosing instability using the synchronous phase angle. The synchronous phase angle ?? is the angle by which the unbalance vector leads the vibration vector. Experiments have proved that ?? changes appreciably when there is a de-stabilizing cross coupled force acting on the rotor as compared to when there is none. A special technique to calculate the change in ?? with cross-coupling is outlined along with empirical results to exemplify the case. Subsequently, a correlation between the synchronous phase angle and the phase angle measured with most industrial balancing instruments is derived so that the actual measurement of the true phase angle is not a necessity for diagnosis. Requirements of advanced signal analysis techniques have led to the development of an extremely powerful rotordynamic measurement teststand ?? ??LVTRC??. The software was developed in tandem with this thesis project. It is a stand-alone application that can be used for field measurements and analysis by turbomachinery companies.
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Books on the topic "LVTSCR"

1

Harper, David E. Project LVTS Amtanks: LVT2, LVTA2. Moscow Hills, MO: Letterman Publications, 2003.

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2

Kamhi, Nadja. LVTS, the overnight market, and monetary policy. Ottawa: Bank of Canada, 2006.

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3

McPhail, Kim. Excess collateral in the LVTS: How much is too much? Ottawa: Bank of Canada, 2003.

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4

Arjani, Neville. Examining the trade-off between settlement delay and intraday liquidity in Canada's LVTS: A simulation approach. Ottawa: Bank of Canada, 2006.

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Arjani, Neville. Examining the trade-off between settlement delay and intraday liquidity in Canada's LVTS: A simulation approach. Ottawa: Bank of Canada, 2006.

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Arjani, Neville. Examining the trade-off between settlement delay and intraday liquidity in Canada's LVTS: A simulation approach. Ottawa, Ont: Bank of Canada, 2006.

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Conference papers on the topic "LVTSCR"

1

Huang, Meichen, Feibo Du, Fei Hou, Wenqiang Song, Jizhi Liu, and Zhiwei Liu. "Enhanced LVTSCR with High Holding Voltage in Advanced CMOS technology." In 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2019. http://dx.doi.org/10.1109/edssc.2019.8754362.

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Yang, Kai, Jizhi Liu, and Zhiwei Liu. "LVTSCR with High Holding Voltage for ESD Protection in 55nm CMOS Process." In 2019 8th International Symposium on Next Generation Electronics (ISNE). IEEE, 2019. http://dx.doi.org/10.1109/isne.2019.8896559.

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Zhou, Yuanzhong (Paul), Jean-Jacques Hajjar, Alan W. Righter, and Kenneth P. Lisiak. "Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models." In 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). IEEE, 2007. http://dx.doi.org/10.1109/eosesd.2007.4401749.

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Kadu, A. U., S. M. Turkane, S. D. Pable, and A. K. Kureshi. "Implementation of a novel co-design of LVTSCR for effective ESD protection in ultra-deep submicron IC." In 2015 International Conference on Industrial Instrumentation and Control (ICIC). IEEE, 2015. http://dx.doi.org/10.1109/iic.2015.7150588.

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5

Chen, Shen-Li, Chun-Ju Lin, Min-Hua Lee, and Yi-Sheng Lai. "Layout-type dependence on ESD/LU reliabilities for LVTnSCR devices." In 2013 1st International Future Energy Electronics Conference (IFEEC). IEEE, 2013. http://dx.doi.org/10.1109/ifeec.2013.6687601.

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Chen, Shen-Li, and Chun-Ju Lin. "Layout-type dependence on ESD/LU immunities for LVTnSCR devices in LV applications." In International Conference on Information Engineering. Southampton, UK: WIT Press, 2014. http://dx.doi.org/10.2495/icie130621.

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7

Li, Xiaojun, Alan Palazzolo, and Zhiyang Wang. "Rotating Machinery Monitoring and Fault Diagnosis With Neural Network Enhanced Fuzzy Logic Expert System." In ASME Turbo Expo 2016: Turbomachinery Technical Conference and Exposition. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/gt2016-58102.

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This paper presents an intelligent monitoring and fault diagnosis approach for rotating machinery by utilizing artificial neural networks and fuzzy logic expert systems (FLES). A recurrent neural network (RNN) is introduced to filter the input signal before they are forwarded to the expert system. The RNN is trained based on existing operational data so that it can adapt to a specific machine’s configurations and conditions. The RNN is able to generate proper baseline signal even if the machine is not under the exact same condition. A fuzzy logical expert system is then used for diagnosis based on the residual signal generated by the RNN. The system is incorporated into an existing comprehensive roto-dynamics software package named LVTRC.
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