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Relevant bibliographies by topics / Managed memory / Dissertations / Theses

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Dissertations / Theses on the topic 'Managed memory'

Author: Grafiati

Published: 26 June 2021

Last updated: 29 July 2025

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1

Jost, Tiago Trevisan. "SoMMA : a software managed memory architecture for multi-issue processors." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/170975.

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Processadores embarcados utilizam eficientemente o paralelismo a nível de instrução para atender as necessidades de desempenho e energia em aplicações atuais. Embora a melhoria de performance seja um dos principais objetivos em processadores em geral, ela pode levar a um impacto negativo no consumo de energia, uma restrição crítica para sistemas atuais. Nesta dissertação, apresentamos o SoMMA, uma arquitetura de memória gerenciada por software para processadores embarcados capaz de reduz consumo de energia e energy-delay product (EDP), enquanto ainda aumenta a banda de memória. A solução combi

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Barua, Rajeev K. (Rajeev Kumar). "Maps : a compiler-managed memory system for software-exposed architectures." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/37194.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.<br>Includes bibliographical references (p. 155-161).<br>Microprocessors must exploit both instruction-level parallelism (ILP) and memory parallelism for high performance. Sophisticated techniques for ILP have boosted the ability of modern-day microprocessors to exploit ILP when available. Unfortunately, improvements in memory parallelism in microprocessors have lagged behind. This thesis explains why memory parallelism is hard to exploit in microprocessors and advocate bank-expose

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Nagel, Fabian Oliver. "Efficient query processing in managed runtimes." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/15869.

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This thesis presents strategies to improve the query evaluation performance over huge volumes of relational-like data that is stored in the memory space of managed applications. Storing and processing application data in the memory space of managed applications is motivated by the convergence of two recent trends in data management. First, dropping DRAM prices have led to memory capacities that allow the entire working set of an application to fit into main memory and to the emergence of in-memory database systems (IMDBs). Second, language-integrated query transparently integrates query proces

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Rose, Benjamin Aaron. "Intra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchies." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/32824.

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The use of asymmetric multi-core processors with on-chip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise applications. The focus of current research has been on making efficient use of individual systems, and porting applications to asymmetric processors. The use of these asymmetric processors, like the Cell processor, in a cluster setting is the inspiration for the Cell Connector framework presented in this thesis. Cell Connector adopts a streaming approach for providing data to compute nodes with high computing potent

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Sandhu, Tahir S. Drake Frederick D. "Beyond American Memory technologies of library and office automation and their impact on multimedia computing for public education in the United States, 1963-present /." Normal, Ill. Illinois State University, 2001. http://wwwlib.umi.com/cr/ilstu/fullcit?p3006627.

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Thesis (D.A.)--Illinois State University, 2001.<br>Title from title page screen, viewed April 18, 2006. Dissertation Committee: Frederick D. Drake (chair), Lawrence McBride, John B. Freed. Includes bibliographical references (leaves 351-398) and abstract. Also available in print.

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Nejadfard, Kian. "Context-aware automated refactoring for unified memory allocation in NVIDIA CUDA programs." Cleveland State University / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=csu1624622944458295.

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7

Ayers, Andrew Edward. "M̲, a memory manager for Ḻ". Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/45691.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.<br>Characters with an underscore appear as italic on the t.p.<br>Bibliography: leaves 94-95.<br>by Andrew Edward Ayers.<br>M.S.

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Harrison, Pascale. "How individuals with Fibromyalgia manage their memory problems." Thesis, University of the West of England, Bristol, 2012. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.572883.

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Background: Previous studies have reported that there is both objective and subjective evidence that individuals with Fibromyalgia (FM) suffer from memory problems (Landro et al 1997; Katz et al 2004; Munoz et al 2005). The current literature has not examined how individuals cope with these difficulties. Aims of the study: The three aims were to: 1) measure the perceptions of managing memory problems for a FM population; 2) examine their coping response/strategies to establish if the responses can be explained by Models of Stress, Coping and Adjustment (The SRM and Transactional Model of Stres

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9

Muthukumaraswamy, Sivakumar Vijay. "An Evaluation of the Linux Virtual Memory Manager to Determine Suitability for Runtime Variation of Memory." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/31608.

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Systems that support virtual memory virtualize the available physical memory such that the applications running on them operate under the assumption that these systems have a larger amount of memory available than is actually present. The memory managers of these systems manage the virtual and the physical address spaces and are responsible for converting the virtual addresses used by the applications to the physical addresses used by the hardware. The memory managers assume that the amount of physical memory is constant and does not change during their period of operation. Some operating scen

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Rezaei, Mehran. "Intelligent Memory Manager: Towards improving the locality behavior of allocation-intensive applications." Thesis, University of North Texas, 2004. https://digital.library.unt.edu/ark:/67531/metadc4491/.

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Dynamic memory management required by allocation-intensive (i.e., Object Oriented and linked data structured) applications has led to a large number of research trends. Memory performance due to the cache misses in these applications continues to lag in terms of execution cycles as ever increasing CPU-Memory speed gap continues to grow. Sophisticated prefetcing techniques, data relocations, and multithreaded architectures have tried to address memory latency. These techniques are not completely successful since they require either extra hardware/software in the system or special properties in

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Zhang, Q. "Memory management architecture for next generation networks traffic managers." Thesis, Queen's University Belfast, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.557859.

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The trend of moving conventionallP networks towards Next Generation Networks (NGNs) has highlighted the need for more sophisticated Traffic Managers (TMs) to guarantee better network and Quality of Service (QoS); these have to be scalable to support increasing link bandwidth and to cater for more diverse emerging applications. Current TM solutions though, are limited and not flexible enough to support new TM functionality or QoS with increasing diversity at faster speeds. This thesis investigates efficient and flexible memory management architectures that are critical in determining scalabilit

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Beu, Jesse Garrett. "Design of heterogeneous coherence hierarchies using manager-client pairing." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47710.

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Over the past ten years, the architecture community has witnessed the end of single-threaded performance scaling and a subsequent shift in focus toward multicore and manycore processing. While this is an exciting time for architects, with many new opportunities and design spaces to explore, this brings with it some new challenges. One area that is especially impacted is the memory subsystem. Specifically, the design, verification, and evaluation of cache coherence protocols becomes very challenging as cores become more numerous and more diverse. This dissertation examines these issues and

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El-Shambakey, Mohammed Talat. "Real-Time Software Transactional Memory: Contention Managers, Time Bounds, and Implementations." Diss., Virginia Tech, 2013. http://hdl.handle.net/10919/23867.

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Lock-based concurrency control suffers from programmability, scalability, and composability challenges. These challenges are exacerbated in emerging multicore architectures, on which improved software performance must be achieved by exposing greater concurrency. Transactional memory (TM) is an emerging alternative synchronization model for shared memory objects that promises to alleviate these difficulties. In this dissertation, we consider software transactional memory (STM) for concurrency control in multicore real-time software, and present a suite of real-time STM contention managers

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Tsegaye, Melekam Asrat. "A model for a context aware machine-based personal memory manager and its implementation using a visual programming environment." Thesis, Rhodes University, 2007. http://hdl.handle.net/10962/d1006563.

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Memory is a part of cognition. It is essential for an individual to function normally in society. It encompasses an individual's lifetime experience, thus defining his identity. This thesis develops the concept of a machine-based personal memory manager which captures and manages an individual's day-to-day external memories. Rather than accumulating large amounts of data which has to be mined for useful memories, the machine-based memory manager automatically organizes memories as they are captured to enable their quick retrieval and use. The main functions of the machine-based memory manager

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BINHOTE, JULIANA MOLINA. "WHO BUILDS AND MANAGES THE HISTORY AND MEMORY OF ORGANIZATIONS?: A STUDY OF THE PRODUCTION COMPANIES OF ORGANIZATIONAL HISTORIES." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2017. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=33116@1.

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A literatura predominante em Administração preconiza que a vantagem competitiva das organizações depende da capacidade da organização aprender a aprender e dinamizar seus processos e rotinas organizacionais de forma a internalizar o conhecimento gerado pela interação de seus atores organizacionais e o ambiente externo. Essa preocupação tem gerado diversos estudos voltados para a forma pela qual esse conhecimento é gerado, organizado e armazenado e, voltando-se cada vez mais para o papel da história na estratégia da empresa e na construção de sentido organizacional interno e externo através da

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Manickavasagam, Senthilkumar. ""a+b" arithmetic - Theory and implementation." Ohio University / OhioLINK, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1178051605.

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Jardim, Mara Publio de Souza Veiga. "O guardião da Memória." Pontifícia Universidade Católica de Goiás, 2004. http://localhost:8080/tede/handle/tede/2279.

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Made available in DSpace on 2016-08-10T10:36:37Z (GMT). No. of bitstreams: 1 Mara Publio de Souza Veiga Jardim.pdf: 521940 bytes, checksum: 2334a45d36bbcf3b613c37f4edb31756 (MD5) Previous issue date: 2004-08-09<br>After a survey on the feast of the Holy Ghost, carried out in the city of Santa Cruz de Goiás, a small city in the interior of the State, it was possible to see the shaping of a figure who became both the theme and the object of this dissertation. Centering the discussion upon cultural assets, memory and identity, I identified and nominated a character who represents a new category

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Martins, Tiago Ferreira. "Processamento analítico de dados em aplicações de em aplicações de monitorização de performance de redes utilizando in-memory data grids." Master's thesis, Universidade de Aveiro, 2016. http://hdl.handle.net/10773/22719.

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Mestrado em Sistemas de Informação<br>Nos últimos anos, assiste-se a um forte incremento no que diz respeito ao volume de dados e sua respetiva valorização por parte das organizações, sobretudo em aplicações de monitorização de performance de redes, como se observa na ferramenta Nokia Performance Manager (NPM). A situação atual justifica-se com o crescimento do setor das telecomunicações, com a necessidade de dar resposta à constante evolução das tecnologias de rede 2G, 3G e atualmente o 4G ou LTE, no processo de centralização, processamento e armazenamento de dados ou indicadores de performan

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Lindh, Jayesh. "Våra viktigaste arbeten och arbetsplatser i livet : En självbiografisk minnesstudie." Thesis, Högskolan i Gävle, Avdelningen för arbetshälsovetenskap och psykologi, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-30709.

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Syftet med studien var att undersöka våra viktigaste positiva och negativa självbiografiska arbetsplatsminnen hos chefer och ej-chefer relaterade till arbetsrelaterad identitet och arbetsplatsminnens fenomenologi. Totalt deltog 194 personer, 124 män och 70 kvinnor i åldern 25 - 65 år i studien. Mätinstrumentet för studien bestod av en enkät i tre delar vilken innehöll frågor baserat på tidigare forskning. De positiva arbetsplatsminnena (80%) innehöll i huvudsak två teman, arbetsmiljö och mina arbetsuppgifter medans de negativa arbetsplatsminnena (20%) visade mer tydligt att en majoritet av min

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Houvet-Carrau, Christiane. "Capital social de l'entreprise familiale : les patrimoines individuels d'habitudes des dirigeants membres de la famille comme clé d'exploration des dimensions cognitive et relationnelle." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0013.

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Cette thèse propose une exploration du lien entre le capital social familial et les dimensionscognitive et relationnelle du capital social organisationnel de l'entreprise familiale (EF). La rechercheconduite allie fondamentaux théoriques de l'EF et théories de la sociologie, psychosociologie etpsychanalyse. En considérant que la famille, via sa culture, fournit un socle de lectures partagées dela réalité et influence les schèmes d'action et de pensée de ses membres, la question se pose del'impact sur le construit socio-culturel de l'EF, de l’entrechoquement ou de la superposition de cesschèmes

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"Scratchpad Management in Software Managed Manycore Architectures." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.46214.

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abstract: Caches have long been used to reduce memory access latency. However, the increased complexity of cache coherence brings significant challenges in processor design as the number of cores increases. While making caches scalable is still an important research problem, some researchers are exploring the possibility of a more power-efficient SRAM called scratchpad memories or SPMs. SPMs consume significantly less area, and are more energy-efficient per access than caches, and therefore make the design of on-chip memories much simpler. Unlike caches, which fetch data from memories automati

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"Compiler and Runtime for Memory Management on Software Managed Manycore Processors." Doctoral diss., 2014. http://hdl.handle.net/2286/R.I.24758.

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abstract: We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale to hundreds and thousands of cores. In addition, caches and coherence logic already take 20-50% of the total power consumption of the processor and 30-60% of die area. Therefore, a more scalable architecture is needed for manycore architectures. Software Managed Manycore (SMM)

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Lashgar, Ahmad. "Addressing software-managed cache development effort in GPGPUs." Thesis, 2017. https://dspace.library.uvic.ca//handle/1828/8483.

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GPU Computing promises very high performance per watt for highly-parallelizable workloads. Nowadays, there are various programming models developed to utilize the computational power of GPGPUs. Low-level programming models provide full control over GPU resources and allow programmers to achieve peak performance of the chip. In contrast, high-level programming models hide GPU-specific programming details and allow programmers to mainly express parallelism. Later, the compiler parses the parallelization notes and translates them to low-level programming models. This saves tremendous develop

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Sartor, Jennifer Bedke. "Exploiting language abstraction to optimize memory efficiency." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-08-1919.

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The programming language and underlying hardware determine application performance, and both are undergoing revolutionary shifts. As applications have become more sophisticated and capable, programmers have chosen managed languages in many domains for ease of development. These languages abstract memory management from the programmer, which can introduce time and space overhead but also provide opportunities for dynamic optimization. Optimizing memory performance is in part paramount because hardware is reaching physical limits. Recent trends towards chip multiprocessor machines exacerbate

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"Optimizing Heap Data Management on Software Managed Manycore Architectures." Master's thesis, 2017. http://hdl.handle.net/2286/R.I.45507.

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abstract: Caches pose a serious limitation in scaling many-core architectures since the demand of area and power for maintaining cache coherence increases rapidly with the number of cores. Scratch-Pad Memories (SPMs) provide a cheaper and lower power alternative that can be used to build a more scalable many-core architecture. The trade-off of substituting SPMs for caches is however that the data must be explicitly managed in software. Heap management on SPM poses a major challenge due to the highly dynamic nature of of heap data access. Most existing heap management techniques implement a sof

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Ji, Wei-Jhong, and 紀韋仲. "Hardware Garbage Collecting Memory Manager for a Java Processor." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/36uqu5.

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碩士<br>國立交通大學<br>資訊科學與工程研究所<br>106<br>This thesis is developed based on a Java Application IP(JAIP). We propose two component to manage heap space for JAIP. One is Garbage Collection Unit with reference counting algorithm and one is Memory Management Unit. Memory Management Unit provides an interface for creating objects and manages the heap space. Garbage Collection Unit collects garbage objects in background in order to reduce overheads. In this thesis, we used Free lists(BRAM) to record free space. If heap allocation size is less than 32 words, JAIP can efficiently allocate small memory bloc

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Huetter, RJ. "RHmalloc : a very large, highly concurrent dynamic memory manager." Thesis, 2005. http://hdl.handle.net/10453/37375.

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University of Technology, Sydney. Dept. of Software Engineering.<br>Dynamic memory management (DMM) is a fundamental aspect of computing, directly affecting the capability, performance and reliability of virtually every system in existence today. Yet oddly, the fifty year research into DMM has not taken memory capacity into account, having fallen significantly behind hardware trends. Comparatively little research work on scalable DMM has been conducted – of the order of ten papers exist on this topic – all of which focus on CPU scalability only; the largest heap reported in the literature to d

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Tsegaye, Melekam Asrat. "A model for a context aware machine-based personal memory manager and its implementation using a visual programming environment /." 2006. http://eprints.ru.ac.za/887/.

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Gerace, Adam. "The influence of past experience on the process of perspective taking." 2009. http://arrow.unisa.edu.au/vital/access/manager/Repository/unisa:38313.

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Perspective taking, the main cognitive component of empathy, is considered within the psychological literature to be a significant part of human interaction. Despite extensive investigation into the outcomes of this construct, the process by which people take another's psychological point of view has received comparatively little attention. The purpose of this thesis is to investigate in three studies what the individual does when attempting to take the perspective of another person. The first study investigated the particular strategies which individuals use when engaging in perspective-takin

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Ramashekar, Thejas. "Automatic Data Allocation, Buffer Management And Data Movement For Multi-GPU Machines." Thesis, 2013. https://etd.iisc.ac.in/handle/2005/2627.

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Multi-GPU machines are being increasingly used in high performance computing. These machines are being used both as standalone work stations to run computations on medium to large data sizes (tens of gigabytes) and as a node in a CPU-Multi GPU cluster handling very large data sizes (hundreds of gigabytes to a few terabytes). Each GPU in such a machine has its own memory and does not share the address space either with the host CPU or other GPUs. Hence, applications utilizing multiple GPUs have to manually allocate and managed at a on each GPU. A significant body of scientific applications tha

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Ramashekar, Thejas. "Automatic Data Allocation, Buffer Management And Data Movement For Multi-GPU Machines." Thesis, 2013. http://etd.iisc.ernet.in/handle/2005/2627.

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Multi-GPU machines are being increasingly used in high performance computing. These machines are being used both as standalone work stations to run computations on medium to large data sizes (tens of gigabytes) and as a node in a CPU-Multi GPU cluster handling very large data sizes (hundreds of gigabytes to a few terabytes). Each GPU in such a machine has its own memory and does not share the address space either with the host CPU or other GPUs. Hence, applications utilizing multiple GPUs have to manually allocate and managed at a on each GPU. A significant body of scientific applications that

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Panwar, Ashish. "A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation." Thesis, 2015. http://etd.iisc.ac.in/handle/2005/3873.

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Large physical memory modules are necessary to meet performance demands of today's ap- plications but can be a major bottleneck in terms of power consumption during idle periods or when systems are running with workloads which do not stress all the plugged memory resources. Contribution of physical memory in overall system power consumption becomes even more signi cant when CPU cores run on low power modes during idle periods with hardware support like Dynamic Voltage Frequency Scaling. Our experiments show that even 10% of memory allocations can make references to all the banks of physical me

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Panwar, Ashish. "A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation." Thesis, 2015. http://etd.iisc.ernet.in/2005/3873.

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Large physical memory modules are necessary to meet performance demands of today's ap- plications but can be a major bottleneck in terms of power consumption during idle periods or when systems are running with workloads which do not stress all the plugged memory resources. Contribution of physical memory in overall system power consumption becomes even more signi cant when CPU cores run on low power modes during idle periods with hardware support like Dynamic Voltage Frequency Scaling. Our experiments show that even 10% of memory allocations can make references to all the banks of physical me

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La, Porta Louisa Carlotta. "Why some teams work better than others: An investigation of voice, TMS and leadership on team performance." Master's thesis, 2020. http://hdl.handle.net/10071/20694.

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Teams have become the standard way of working in organizations and therefore the question of what differentiates highly performing units from other teams has attracted much research attention. Especially the utilization of knowledge such as team members sharing their knowledge and the awareness of other members’ expertise can be decisive for team performance. Looking into the relationship between team member’s behaviors, team cognition and self-management encouraged by the leader, this study connects three streams of literature, namely voice, TMS and leadership, to reach a better underst

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Patel, Naman. "A Case for Protecting Huge Pages from the Kernel." Thesis, 2016. http://etd.iisc.ac.in/handle/2005/2936.

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Modern architectures support multiple size pages to facilitate applications that use large chunks of contiguous memory either for buffer allocation, application specific memory management, in-memory caching or garbage collection. Most general purpose processors support larger page sizes, for e.g. x86 architecture supports 2MB and 1GB pages while PowerPC architecture supports 64KB, 16MB, 16GB pages. Such larger size pages are also known as superpages or huge pages. With the help of huge pages TLB reach can be increased significantly. The Linux kernel can transparently use these huge pages to si

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Patel, Naman. "A Case for Protecting Huge Pages from the Kernel." Thesis, 2016. http://etd.iisc.ernet.in/handle/2005/2936.

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Modern architectures support multiple size pages to facilitate applications that use large chunks of contiguous memory either for buffer allocation, application specific memory management, in-memory caching or garbage collection. Most general purpose processors support larger page sizes, for e.g. x86 architecture supports 2MB and 1GB pages while PowerPC architecture supports 64KB, 16MB, 16GB pages. Such larger size pages are also known as superpages or huge pages. With the help of huge pages TLB reach can be increased significantly. The Linux kernel can transparently use these huge pages to si

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Farrell, Robert. "Making Change Happen in the Middle." 2013. http://hdl.handle.net/10150/299589.

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This paper seeks to provide library managers with a theoretical framework for thinking about how change is effected by those in middle management positions. Starting from the principles that change takes place within socio-culturally bounded contexts and is most successful when approached indirectly, two scenarios characteristic of many situations requiring change middle managers commonly face are then put forward. Following each scenario, a possible solution or path towards change is advanced in order to provide the reader with models for putting into practice the theoretical ideas presented.

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Kraai, Vuyokazi, Sinval Benjamin Kahn, and Ramokhojoane Paul Motsoeneng. "Succession planning a development tool for developing middle managers in the Department of Science and Technology." Diss., 2015. http://hdl.handle.net/10500/19172.

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The aim of this research is to investigate how succession planning can be used as a developmental tool in developing middle managers in the Department of Science and Technology (DST). The research shows that the DST has good strategies and policies in place for the development and retention of its employees, although there is no succession planning tool or system in place. Proposed interventions to address identified gaps in terms of succession planning include a quota system of positions that should be filled by internal candidates to encourage employees’ buy-in to succession planning; incu

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Sanchez, Sandra. "Maestría En Gestión Pública: Una Contribución de Memoria para la Cualificación de la Administración Pública." Master's thesis, 2019. http://hdl.handle.net/10400.26/31319.

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The following work, analyzes the academic courses offered by Colombia Universities for public servants or those aspiring to become public servents. The undergraduate, specialization and Master's programme curricula in universities running these programmes have been compared to similar courses offered in some of the best national and international universities to assess their effectiveness educational In the last decade, public management has taken great relevance in the administration and control of public goods, for which, specific knowledge is required for the performance of public servants

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Kraai, Vuyokazi. "Succession planning : a development tool for developing middle managers in the Department of Science and Technology." Diss., 2015. http://hdl.handle.net/10500/19172.

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The aim of this research is to investigate how succession planning can be used as a developmental tool in developing middle managers in the Department of Science and Technology (DST). The research shows that the DST has good strategies and policies in place for the development and retention of its employees, although there is no succession planning tool or system in place. Proposed interventions to address identified gaps in terms of succession planning include a quota system of positions that should be filled by internal candidates to encourage employees’ buy-in to succession planning; incu

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Dharmadeep, M. C. "Optimizations In Storage Area Networks And Direct Attached Storage." Thesis, 2007. https://etd.iisc.ac.in/handle/2005/574.

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The thesis consists of three parts. In the first part, we introduce the notion of device-cache-aware schedulers. Modern disk subsystems have many megabytes of memory for various purposes such as prefetching and caching. Current disk scheduling algorithms make decisions oblivious of the underlying device cache algorithms. In this thesis, we propose a scheduler architecture that is aware of underlying device cache. We also describe how the underlying device cache parameters can be automatically deduced and incorporated into the scheduling algorithm. In this thesis, we have only considered ada

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Dharmadeep, M. C. "Optimizations In Storage Area Networks And Direct Attached Storage." Thesis, 2007. http://hdl.handle.net/2005/574.

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Abstract:

The thesis consists of three parts. In the first part, we introduce the notion of device-cache-aware schedulers. Modern disk subsystems have many megabytes of memory for various purposes such as prefetching and caching. Current disk scheduling algorithms make decisions oblivious of the underlying device cache algorithms. In this thesis, we propose a scheduler architecture that is aware of underlying device cache. We also describe how the underlying device cache parameters can be automatically deduced and incorporated into the scheduling algorithm. In this thesis, we have only considered adapt

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