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Relevant bibliographies by topics / Manchester carry chain

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Journal articles
Dissertations / Theses
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Academic literature on the topic 'Manchester carry chain'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Manchester carry chain"

1

Escribá, J., and J. A. Carrasco. "Self-timed Manchester chain carry propagate adder." Electronics Letters 32, no. 8 (1996): 708. http://dx.doi.org/10.1049/el:19960512.

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Das, P., A. L. Bhalerao, A. Mane, A. A Angeline, and V. S. K. Bhaaskaran. "Design of Manchester Carry Chain Adder using High speed Domino Logic." IOP Conference Series: Materials Science and Engineering 561 (November 12, 2019): 012125. http://dx.doi.org/10.1088/1757-899x/561/1/012125.

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Bharathan, Kala, and R. Seshasayanan. "Optimized Double Domino Manchester Carry Chain Adders in 45 nm Technology." Journal of Computational and Theoretical Nanoscience 13, no. 12 (2016): 9199–206. http://dx.doi.org/10.1166/jctn.2016.6304.

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Blair, G. M. "Circuit improvements for high-speed domino logic: for the Manchester carry chain." Electronics Letters 34, no. 3 (1998): 247. http://dx.doi.org/10.1049/el:19980236.

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Lou, J. H., and J. B. Kuo. "A 1.5-V bootstrapped pass-transistor-based Manchester carry chain circuit suitable for implementing low-voltage carry look-ahead adders." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 45, no. 11 (1998): 1191–94. http://dx.doi.org/10.1109/81.735441.

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Neeraj, Jain, Gour Puran, and Shrman Brahmi. "A High Speed Low Power Adder in Multi Output Domino Logic." International Journal of Computer Applications 105, no. 7 (2014): 30–33. https://doi.org/10.5281/zenodo.33240.

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Speed and power is the major constraint in modern digital design so it is required to design the high speed, less number of transistors as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power cons

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Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manc

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8

"DESIGN OF RELIABLE AND EFFICIENT MANCHESTER CARRY CHAIN ADDER BASED 8-BIT ALU FOR HIGH SPEED APPLICATIONS." Journal of VLSI Circuits and Systems 01, no. 01 (2019). http://dx.doi.org/10.31838/jvcs/01.01.01.

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Neeraj, Jain, Gour Puran, and Shrman Brahmi. "A High Speed Low Power Adder in Multi Output Domino Logic." International Journal of Scientific Research Engineering & Technology, November 3, 2014, 16–18. https://doi.org/10.5281/zenodo.33083.

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Speed and power is the major constraint in modern digital design. We have to design the high speed, less number of transistor as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power consumption in

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10

Taha, Berk Astam. "Analogies Between Peter Jackson's movie adaptation of The Lord of the Rings and Jeanette Winterson's novel Weight." November 24, 2022. https://doi.org/10.5281/zenodo.7358319.

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<strong>Taha Berk Astam – i.berkastam@gmail.com</strong> <strong>Yuzuncu Yil University Faculty of Literature Department of English Language and Literature</strong>   <strong>Analogies Between Peter Jackson's movie adaptation of <em>The Lord of the Rings</em> and Jeanette Winterson's novel <em>Weight</em></strong>   <strong>Abstract</strong>   Analogies between Peter Jackson’s famous fantasy film trilogy, <em>The Lord of the Rings</em>, adapted from J.R.R. Tolkien’s trilogy-novel with the same title, and Jeanette Winterson’s acclaimed novel <em>We

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Dissertations / Theses on the topic "Manchester carry chain"

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Meruguboina, Dronacharya. "EFFICIENT DESIGN OF CARRY SELECT ADDER USING DOMINO MANCHESTER CARRY CHAIN." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/theses/2125.

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Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will

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Chang, Yow-Min, and 張佑民. "Manchester Carry Chain Adder Research." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/65144323390590147038.

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碩士<br>國立交通大學<br>電子工程系<br>88<br>This thesis discusses the adder based on Manchester carry chain. The Manchester carry chain circuit based on pass-transistors and dynamic logic techniques have the smallest transistor count among all carry look-ahead circuits including domino and other static techniques. We introduce new bypass circuit、new output buffer and carry-chain buffer. Then we design a 64-b adder based on the circuits introduced on the thesis. The analysis data based on TSMC 0.6μm SPDM CMOS technology got by HSPICE.

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Book chapters on the topic "Manchester carry chain"

1

Asha, J., Kala Bharathan, and Anuja T. Samuel. "A Low-Power High-Speed Double Manchester Carry Chain with Carry-Skip Using D3L." In Advances in Intelligent Systems and Computing. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2526-3_4.

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Conference papers on the topic "Manchester carry chain"

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S, Abhinav, Busam Karthikeya, Ishan Acharyya, Anushka Tripathi, and Abhishek Srivastava. "Design of Manchester Carry Chain Hybrid Adder for MASH 1-1-1 Delta Sigma Modulator for Fractional-N Frequency Synthesizers." In 2025 38th International Conference on VLSI Design and 2025 24th International Conference on Embedded Systems (VLSID). IEEE, 2025. https://doi.org/10.1109/vlsid64188.2025.00039.

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Asha, J., and Jawahar Senthilkumar. "High speed Manchester Carry chain with carry-skip capability." In 2015 International Conference on Circuit, Power and Computing Technologies (ICCPCT). IEEE, 2015. http://dx.doi.org/10.1109/iccpct.2015.7159396.

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A., Harikrishnan, and Sourabh Sethi. "Sizing techniques for delay optimisation of 4-bit dynamic CMOS Manchester carry chain." In 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN). IEEE, 2019. http://dx.doi.org/10.1109/vitecon.2019.8899634.

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Vallabhuni, Rajeev Ratna, A. Karthik, CH V. Sai Kumar, B. Varun, P. Veerendra, and Srisailam Nayak. "Comparative Analysis of 8-Bit Manchester Carry Chain Adder Using FinFET at 18nm Technology." In 2020 3rd International Conference on Intelligent Sustainable Systems (ICISS). IEEE, 2020. http://dx.doi.org/10.1109/iciss49785.2020.9316061.

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Katreepalli, Raghava, and Themistoklis Haniotakis. "Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder." In 2017 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2017. http://dx.doi.org/10.1109/iccsp.2017.8286618.

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