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Journal articles on the topic 'Mémoire non volatile, NVM'

Author: Grafiati

Published: 23 June 2022

Last updated: 28 July 2025

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1

Shao, Zili, and Yuan-Hao Chang. "Non-Volatile memory (NVM) technologies." Journal of Systems Architecture 71 (November 2016): 1. http://dx.doi.org/10.1016/j.sysarc.2016.11.007.

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2

Chu, Zhaole, Yongping Luo, and Peiquan Jin. "An Efficient Sorting Algorithm for Non-Volatile Memory." International Journal of Software Engineering and Knowledge Engineering 31, no. 11n12 (2021): 1603–21. http://dx.doi.org/10.1142/s0218194021400143.

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Non-volatile memory (NVM) has emerged as an alternative of the next-generation memory due to its non-volatility, byte addressability, high storage-density, and low-energy consumption. However, NVM also has some limitations, e.g. asymmetric read and write latency. Therefore, at present, it is not realistic to completely replace DRAM with NVM in computer systems. A more feasible scheme is to adopt the hybrid memory architecture composed of NVM and DRAM. Following the assumption of hybrid memory architecture, in this paper, we propose an NVM-friendly sorting algorithm called NVMSorting. Particula

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3

Kawata, Hirotaka, Gaku Nakagawa, and Shuichi Oikawa. "Using DRAM as Cache for Non-Volatile Main Memory Swapping." International Journal of Software Innovation 4, no. 1 (2016): 61–71. http://dx.doi.org/10.4018/ijsi.2016010105.

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The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the p

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Li, Xiaochang, and Zhengjun Zhai. "UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory." Electronics 10, no. 15 (2021): 1760. http://dx.doi.org/10.3390/electronics10151760.

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During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applicatio

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Tyler, Neil. "Adding NVM Functions." New Electronics 51, no. 19 (2019): 8. http://dx.doi.org/10.12968/s0047-9624(22)61453-6.

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6

He, Qinlu, Huiguo Dong, Genqing Bian, et al. "The Research of Spark Memory Optimization Based on Non-Volatile Memory." Journal of Nanoelectronics and Optoelectronics 17, no. 1 (2022): 30–39. http://dx.doi.org/10.1166/jno.2022.3166.

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With the advent of the significant data era, more and more data information needs to be processed, bringing tremendous challenges to storage and computing. The spark amount of data is getting larger and larger, and the I/O bottleneck of computing and scheduling from the disk has increasingly become an essential factor restricting performance. The spark came into being and proposed in-memory computing, which significantly improved the computing speed. In addition, the high rate of the memory is easy to lose without power, and the small but expensive feature is also an urgent need to improve. Th

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Haywood Dadzie, Thomas, Jiwon Lee, Jihye Kim, and Hyunok Oh. "NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory." Electronics 9, no. 8 (2020): 1304. http://dx.doi.org/10.3390/electronics9081304.

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The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM

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Jin, Kailun, Yajuan Du, Mingzhe Zhang, Zhenghao Yin, and Rachata Ausavarungnirun. "Relieving Compression-Induced Local Wear on Non-Volatile Memory Block via Sliding Writes." Micromachines 14, no. 3 (2023): 568. http://dx.doi.org/10.3390/mi14030568.

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Due to its non-volatility and large capacity, NVM devices gradually take place at various levels of memories. However, their limited endurance is still a big concern for large-scale data centres. Compression algorithms have been used to save NVM space and enhance the efficiency of those lifetime extension methods. However, their own influence on the NVM lifetime is not clear. In order to fully investigate the impact of compression on NVM, this paper first studies bit flips involved in several typical compression algorithms. It is found that more bit flips would happen in the shrunken area of a

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9

Jung, Myoungsoo, Ellis H. Wilson, Wonil Choi, et al. "Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory." Scientific Programming 22, no. 2 (2014): 125–39. http://dx.doi.org/10.1155/2014/303810.

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Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this

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Zheng, Bolong, Yongyong Gao, Jingyi Wan, et al. "DecLog: Decentralized Logging in Non-Volatile Memory for Time Series Database Systems." Proceedings of the VLDB Endowment 17, no. 1 (2023): 1–14. http://dx.doi.org/10.14778/3617838.3617839.

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Growing demands for the efficient processing of extreme-scale time series workloads call for more capable time series database management systems (TSDBMS). Specifically, to maintain consistency and durability of transaction processing, systems employ write-ahead logging (WAL) whereby transactions are committed only after the related log entries are flushed to disk. However, when faced with massive I/O, this becomes a throughput bottleneck. Recent advances in byte-addressable Non-Volatile Memory (NVM) provide opportunities to improve logging performance by persisting logs to NVM instead. Existi

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11

Bittman, Daniel, Peter Alvaro, Pankaj Mehra, Darrell D. E. Long, and Ethan L. Miller. "Twizzler: A Data-centric OS for Non-volatile Memory." ACM Transactions on Storage 17, no. 2 (2021): 1–31. http://dx.doi.org/10.1145/3454129.

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Byte-addressable, non-volatile memory (NVM) presents an opportunity to rethink the entire system stack. We present Twizzler, an operating system redesign for this near-future. Twizzler removes the kernel from the I/O path, provides programs with memory-style access to persistent data using small (64 bit), object-relative cross-object pointers, and enables simple and efficient long-term sharing of data both between applications and between runs of an application. Twizzler provides a clean-slate programming model for persistent data, realizing the vision of Unix in a world of persistent RAM. We

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Bez, Roberto, Emilio Camerlenghi, and Agostino Pirovano. "Materials and Processes for Non-Volatile Memories." Materials Science Forum 608 (December 2008): 111–32. http://dx.doi.org/10.4028/www.scientific.net/msf.608.111.

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The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics

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Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang, and Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory." Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.

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NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.

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Ding, Chen, Jiguang Wan, and Rui Yan. "HybridKV: An Efficient Key-Value Store with HybridTree Index Structure Based on Non-Volatile Memory." Journal of Physics: Conference Series 2025, no. 1 (2021): 012093. http://dx.doi.org/10.1088/1742-6596/2025/1/012093.

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Abstract Non-Volatile Memory (NVM) is a new type of storage media with non-volatile data, higher storage density, better performance and concurrency. Persistent key-value stores designed for earlier storage devices, using Log-Structured Merge Tree (LSM-Tree), have serious read-write amplification problem and do not take full advantage of these new devices. Existing works on NVM index structure are mostly based on Radix-Tree or B+-Tree, index structure based on Radix-Tree has better performance but takes up more space. In this paper, we present a new index structure named HybridTree on NVM. Hyb

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Ye, Chencheng, Yuanchao Xu, Xipeng Shen, Hai Jin, Xiaofei Liao, and Yan Solihin. "Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory." ACM Transactions on Architecture and Code Optimization 19, no. 2 (2022): 1–26. http://dx.doi.org/10.1145/3511706.

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This article points out an important threat that application-level Garbage Collection (GC) creates to the use of non-volatile memory (NVM). Data movements incurred by GC may invalidate the pointers to objects on NVM and, hence, harm the reusability of persistent data across executions. The article proposes the concept of movement-oblivious addressing (MOA), and develops and compares three novel solutions to materialize the concept for solving the addressability problem. It evaluates the designs on five benchmarks and a real-world application. The results demonstrate the promise of the proposed

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Naqi, Muhammad, Nayoung Kwon, Sung Jung, et al. "High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles." Nanomaterials 11, no. 5 (2021): 1101. http://dx.doi.org/10.3390/nano11051101.

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Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from −20 V to +20 V back and fo

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17

Ando, Takashi. "(Invited) Non-Volatile Memory Technology for Analog in-Memory Compute." ECS Meeting Abstracts MA2025-01, no. 31 (2025): 1587. https://doi.org/10.1149/ma2025-01311587mtgabs.

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IBM is pioneering an analog in-memory compute technology that promises to considerably reduce the energy consumption needed for AI workloads by performing the computation directly in memory using resistive non-volatile memory (NVM) devices [1]. We have derived requirements for Resistive Processing Unit (RPU) devices that can simultaneously store and process data locally and in parallel, thus providing significant acceleration for deep neural network training [2]. For demonstration of analog in-memory computing applications at scale, the conventional CMOS and memory technologies should be fully

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18

Gong, Cihun-Siyong, Yung-Chang Chang, Li-Ren Huang, et al. "Two Dimensional Parity Check with Variable Length Error Detection Code for the Non-Volatile Memory of Smart Data." Applied Sciences 8, no. 8 (2018): 1211. http://dx.doi.org/10.3390/app8081211.

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This paper proposes a novel technology of memory protection for the Non-Volatile Memory (NVM), applied to smart sensors and smart data. Based on the asymmetry of failure rate between the statuses of bit-0 and bit-1 in the non-volatile memory, as a result of the pollution of the radiation of cosmic ray, a two-dimensional parity with variable length error detection code (2D-VLEDC) for memory protection is proposed. 2D-VLEDC has the feature of variable length of redundant bits varied with content of data word in the NVM. The experimental results show that the same error detection quality could be

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19

Wei, Jianhao, Qian Zhang, Yiwen Xiang, and Xueqing Gong. "FIR: Achieving High Throughput and Fast Recovery in a Non-Volatile Memory Online Transaction Processing Engine." Electronics 14, no. 1 (2024): 39. https://doi.org/10.3390/electronics14010039.

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Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) have not fully leveraged hardware characteristics, resulting in an imbalance between throughput and recovery performance. In this paper, we conclude with the reason why existing designs fail to achieve both: placing indexes on NVM results in numerous random writes and write amplification for index updates, leading to a decrease in system performance. Placing indexes on dynamic random access memory (DRAM) results in much time consumption for rebuilding indexes during recovery. To addr

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20

Liu, Gang, Leying Chen, and Shimin Chen. "Zen." Proceedings of the VLDB Endowment 14, no. 5 (2021): 835–48. http://dx.doi.org/10.14778/3446095.3446105.

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Emerging <u>N</u>on-<u>V</u>olatile <u>M</u>emory (NVM) technologies like 3DX-point promise significant performance potential for OLTP databases. However, transactional databases need to be redesigned because the key assumptions that non-volatile storage is orders of magnitude slower than DRAM and only supports blocked-oriented access have changed. NVMs are byte-addressable and almost as fast as DRAM. The capacity of NVM is much (4-16x) larger than DRAM. Such NVM characteristics make it possible to build OLTP database entirely in NVM main memory. This paper

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Gong, Caixin, Chengjin Tian, Zhengheng Wang, et al. "Tair-PMem." Proceedings of the VLDB Endowment 15, no. 12 (2022): 3346–58. http://dx.doi.org/10.14778/3554821.3554827.

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In-memory databases (IMDBs) have been the backbone of modern systems that demand high throughput and low latency. Because of the cost and volatility of DRAM, IMDBs become incompetent when dealing with workloads that require large data volume and strict durability. The emergence of non-volatile memory (NVM) brings new opportunities for IMDBs to tackle this situation. However, it is non-trivial to build an NVM-based IMDB, due to performance degradation, NVM programming complexity, and other challenges. In this paper, we present Tair-PMem , an NVM-based enterprise-strength database atop Redis, th

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Khan, Mohammad Nasim Imtiaz, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. "Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (2021): 38. http://dx.doi.org/10.3390/jlpea11040038.

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Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First,

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Ge, Fen, Lei Wang, Ning Wu, and Fang Zhou. "A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs." Electronics 8, no. 6 (2019): 639. http://dx.doi.org/10.3390/electronics8060639.

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Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, w

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Zhang, Zhou, Zhaole Chu, Peiquan Jin, et al. "PLIN." Proceedings of the VLDB Endowment 16, no. 2 (2022): 243–55. http://dx.doi.org/10.14778/3565816.3565826.

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Non-Volatile Memory (NVM) has emerged as an alternative to next-generation main memories. Although many tree indices have been proposed for NVM, they generally use B+-tree-like structures. To further improve the performance of NVM-aware indices, we consider integrating learned indexes into NVM. The challenges of such an integration are two fold: (1) existing NVM indices rely on small nodes to accelerate insertions with crash consistency, but learned indices use huge nodes to obtain a flat structure. (2) the node structure of learned indices is not NVM friendly, meaning that accessing a learned

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Karacali, Hüseyin, Nevzat Dönüm, and Efecan Cebel. "Full Efficient NVM Usage For MCU." European Journal of Research and Development 3, no. 1 (2023): 115–28. http://dx.doi.org/10.56038/ejrnd.v3i1.245.

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Non-volatile memory (NVM) is a type of computer memory that has the ability to retain stored data even when power is disconnected. Its significance is growing due to the increasing need for fast storage and access to large volumes of data. To maximize the potential of NVM, efficient usage is crucial, which involves optimizing data structures, reducing read and write operations, and minimizing data transfer between NVM-connected applications in areas where low latency and high throughput is essential, such as in-memory databases, high-performance computing, and real-time analytics. Improving NV

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Nassar, Hassan, Lars Bauer, and Jörg Henkel. "ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF." ACM Transactions on Embedded Computing Systems 22, no. 5s (2023): 1–23. http://dx.doi.org/10.1145/3609388.

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Physical Unclonable Functions (PUFs) have been widely considered an attractive security primitive. They use the deviations in the fabrication process to have unique responses from each device. Due to their nature, they serve as a DNA-like identity of the device. But PUFs have also been targeted for attacks. It has been proven that machine learning (ML) can be used to effectively model a PUF design and predict its behavior, leading to leakage of the internal secrets. To combat such attacks, several designs have been proposed to make it harder to model PUFs. One design direction is to use Non-Vo

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Zhao, Xuefeng, Di Wang, Hao Zhang, et al. "Tailoring skyrmion motion dynamics via magnetoelectric coupling: Toward highly energy-efficient and reliable non-volatile memory applications." Journal of Applied Physics 132, no. 8 (2022): 084902. http://dx.doi.org/10.1063/5.0103237.

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Owing to the intriguing physical properties and significant spintronic applications, magnetic skyrmions have recently drawn intensive attention. Particularly, the skyrmion-based non-volatile memory (Sky-NVM) devices promise to be spintronic building blocks with high efficiency. However, tailoring Sky-NVM to achieve an energy-efficient and reliable operation in a synthetic, CMOS compatible, and magnetic-field-free integration is a challenging issue. Here, we report a new type of compact Sky-NVM with tailored skyrmion motion dynamics via in-plane strain gradient engineering. The skyrmion motion

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Cai, Tao, Qingjian He, Dejiao Niu, Fuli Chen, Jie Wang, and Lei Li. "A New Embedded Key–Value Store for NVM Device Simulator." Micromachines 11, no. 12 (2020): 1075. http://dx.doi.org/10.3390/mi11121075.

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The non-volatile memory (NVM) device is a useful way to solve the memory wall in computers. However, the current I/O software stack in operating systems becomes a performance bottleneck for applications based on NVM devices, especially for key–value stores. We analyzed the characteristics of key–value stores and NVM devices and designed a new embedded key–value store for an NVM device simulator named PMEKV. The embedded processor in NVM devices was used to manage key–value pairs to reduce the data transfer between NVM devices and key–value applications. Meanwhile, it also cut down the data cop

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Kargar, Saeed, and Faisal Nawab. "Hamming Tree: The Case for Energy-Aware Indexing for NVMs." Proceedings of the ACM on Management of Data 1, no. 2 (2023): 1–27. http://dx.doi.org/10.1145/3589327.

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Non-volatile memory (NVM) technologies are widely adopted in data storage solutions and battery-powered mobile and IoT devices. Wear-out and energy efficiency are two vital challenges facing the use of NVM. In Hamming Tree, we propose a software-level memory-aware solution that picks the memory segment of where a write operation is applied judiciously to minimize bit flipping. It has been shown that reducing bit flips leads to reducing energy consumption and improving write endurance. We performed real evaluations on an Optane memory device that show that Hamming Tree can achieve up to 67.8% r

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Koutsoukos, Dimitrios, Raghav Bhartia, Michal Friedman, Ana Klimovic, and Gustavo Alonso. "NVM: Is it Not Very Meaningful for Databases?" Proceedings of the VLDB Endowment 16, no. 10 (2023): 2444–57. http://dx.doi.org/10.14778/3603581.3603586.

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Persistent or Non Volatile Memory (PMEM) offers expanded memory capacity and faster access to persistent storage. However, there is no comprehensive empirical analysis of existing database engines under different PMEM modes, to understand how databases can benefit from the various hardware configurations. To this end, we analyze multiple different engines under common benchmarks with PMEM in AppDirect mode and Memory mode. Our results show that PMEM in Memory mode does not offer any clear performance advantage despite the larger volatile memory capacity. Also, using PMEM as persistent storage

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Zhu, Guangyu, Jaehyun Han, Sangjin Lee, and Yongseok Son. "An Empirical Evaluation of NVM-Aware File Systems on Intel Optane DC Persistent Memory Modules." Electronics 10, no. 16 (2021): 1977. http://dx.doi.org/10.3390/electronics10161977.

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The emergence of non-volatile memories (NVM) brings new opportunities and challenges to data management system design. As an important part of the data management systems, several new file systems are developed to take advantage of the characteristics of NVM. However, these NVM-aware file systems are usually designed and evaluated based on simulations or emulations. In order to explore the performance and characteristics of these file systems on real hardware, in this article, we provide an empirical evaluation of NVM-aware file systems on the first commercially available byte-addressable NVM

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32

Chen, An. "A review of emerging non-volatile memory (NVM) technologies and applications." Solid-State Electronics 125 (November 2016): 25–38. http://dx.doi.org/10.1016/j.sse.2016.07.006.

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Du, Mingzhe, and Michael L. Scott. "Buffered Persistence in B+ Trees." Proceedings of the ACM on Management of Data 2, no. 6 (2024): 1–24. https://doi.org/10.1145/3698801.

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Non-volatile Memory (NVM) offers the opportunity to build large, durable B+ trees with markedly higher performance and faster post-crash recovery than is possible with traditional disk- or flash-based persistence. Unfortunately, cache flush and fence instructions, required for crash consistency and failure atomicity on many machines, introduce substantial overhead not present in non-persistent trees, and force additional NVM reads and writes. The overhead is particularly pronounced in workloads that benefit from cache reuse due to good temporal locality or small working sets---traits commonly

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Lei, Mengya, Fan Li, Fang Wang, Dan Feng, Xiaomin Zou, and Renzhi Xiao. "SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM." ACM Transactions on Architecture and Code Optimization 19, no. 1 (2022): 1–26. http://dx.doi.org/10.1145/3488724.

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Data security is an indispensable part of non-volatile memory (NVM) systems. However, implementing data security efficiently on NVM is challenging, since we have to guarantee the consistency of user data and the related security metadata. Existing consistency schemes ignore the recoverability of the SGX style integrity tree (SIT) and the access correlation between metadata blocks, thereby generating unnecessary NVM write traffic. In this article, we propose SecNVM, an efficient and write-friendly metadata crash consistency scheme for secure NVM. SecNVM utilizes the observation that for a lazil

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Wan, Zhe, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, and Vwani P. Roychowdhury. "Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines." ACM Journal on Emerging Technologies in Computing Systems 18, no. 2 (2022): 1–23. http://dx.doi.org/10.1145/3502721.

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Recently, analog compute-in-memory (CIM) architectures based on emerging analog non-volatile memory (NVM) technologies have been explored for deep neural networks (DNNs) to improve scalability, speed, and energy efficiency. Such architectures, however, leverage charge conservation, an operation with infinite resolution, and thus are susceptible to errors. Thus, the inherent stochasticity in any analog NVM used to execute DNNs, will compromise performance. Several reports have demonstrated the use of analog NVM for CIM in a limited scale. It is unclear whether the uncertainties in computations

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Karacali, Huseyin, Nevzat Donum, and Efecan Cebel. "Secure and Efficient NVM Usage for Embedded Systems Using AES-128 and Huffman Compression." European Journal of Research and Development 3, no. 4 (2023): 333–56. http://dx.doi.org/10.56038/ejrnd.v3i4.281.

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Embedded systems are customized systems designed to meet functionality and specific usage purposes. These systems often grapple with challenges such as power interruptions, limited memory space, and the expectation of a long operational lifespan. It is in this context that Non-Volatile Memory (NVM) plays a vital role. NVM is a type of memory that ensures data persistence even in situations of temporary power loss or signal interruptions. Efficiently utilizing NVM is a critical necessity for the effectiveness and reliability of these systems. Efficient utilization of NVM necessitates the effect

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Bahn, Hyokyung, and Kyungwoon Cho. "Implications of NVM Based Storage on Memory Subsystem Management." Applied Sciences 10, no. 3 (2020): 999. http://dx.doi.org/10.3390/app10030999.

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Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by t

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Yang, Yuming, KIM Foong Kong, Young Way Teh, Guanyu Zhou, Nianhong Yu, and Kankan Yu. "A New Integration Scheme to Prevent Chemical Attack on Floating Polysilicon Gate of Non-Volatile Memory." ECS Meeting Abstracts MA2024-01, no. 30 (2024): 1498. http://dx.doi.org/10.1149/ma2024-01301498mtgabs.

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Silicon pitting has been observed on floating gate polysilicon layer of embedded non-volatile memory(e-NVM) process due to chemical attack caused by HBr residual interacting with moisture. This paper successfully demonstrates a new integration scheme for a robust floating gate process against silicon attack for embedded stacked/split gate non-volatile memory process. Firstly, CF4 was introduced into floating gate polysilicon etch recipe to replace HBr, which has been CMOS gate polysilicon etch gas in traditional logic process due to the advantage of higher selectivity despite the disadvantage

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Nagashio, Kosuke. "(Invited, Digital Presentation) 50 Ns Ultrafast Memory Operation in 2D Heterostructured Non-Volatile Memory Device." ECS Meeting Abstracts MA2022-01, no. 10 (2022): 785. http://dx.doi.org/10.1149/ma2022-0110785mtgabs.

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2D heterostructures have been extensively investigated as next-generation non-volatile memory (NVM) devices. In the last decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate voltage (V FG) trajectory measurements [1,2]. Systematic comparisons of MoTe2, WSe2, and MoS2 channel devices revealed that the tunneling be

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Park, Joong-Hyun, Myung-Hun Shin, and Jun-Sin Yi. "The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide." Nanomaterials 9, no. 5 (2019): 784. http://dx.doi.org/10.3390/nano9050784.

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We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the ga

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Zhang, Baoquan, and David H. C. Du. "NVLSM: A Persistent Memory Key-Value Store Using Log-Structured Merge Tree with Accumulative Compaction." ACM Transactions on Storage 17, no. 3 (2021): 1–26. http://dx.doi.org/10.1145/3453300.

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Computer systems utilizing byte-addressable Non-Volatile Memory ( NVM ) as memory/storage can provide low-latency data persistence. The widely used key-value stores using Log-Structured Merge Tree ( LSM-Tree ) are still beneficial for NVM systems in aspects of the space and write efficiency. However, the significant write amplification introduced by the leveled compaction of LSM-Tree degrades the write performance of the key-value store and shortens the lifetime of the NVM devices. The existing studies propose new compaction methods to reduce write amplification. Unfortunately, they result in

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Chen, Wei-Ming, Tei-Wei Kuo, and Pi-Cheng Hsiu. "Heterogeneity-aware Multicore Synchronization for Intermittent Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–22. http://dx.doi.org/10.1145/3476992.

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Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In partic

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Ievtukh, V. A., A. N. Nazarov, V. I. Turchanikov, and V. S. Lysenko. "Nanocluster NVM Cells Metrology: Window Formation, Relaxation and Charge Retention Measurements." Advanced Materials Research 718-720 (July 2013): 1118–23. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.1118.

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In the paper a measurement technique for study main technical and physical parameters of nanocluster non-volatile memory capacitance cell is presented. The charging/discharging process features associated with nanoclusters (nanocrystals) incorporated into gate dielectric are discussed. Original equipment for fast capacitance measurements based on computer interfaces is considers.

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Chi, Ye, Haikun Liu, Ganwei Peng, Xiaofei Liao, and Hai Jin. "Transformer: An OS-Supported Reconfigurable Hybrid Memory Architecture." Applied Sciences 12, no. 24 (2022): 12995. http://dx.doi.org/10.3390/app122412995.

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Non-volatile memories (NVMs) have aroused vast interest in hybrid memory systems due to their promising features of byte-addressability, high storage density, low cost per byte, and near-zero standby energy consumption. However, since NVMs have limited write endurance, high write latency, and high write energy consumption, it is still challenging to directly replace traditional dynamic random access memory (DRAM) with NVMs. Many studies propose to utilize NVM and DRAM in a hybrid memory system, and explore sophisticated memory management schemes to alleviate the impact of slow NVM on the perfo

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Hu, Hongyang, Chuancai Feng, Haiyang Zhou, et al. "Simulation of a Fully Digital Computing-in-Memory for Non-Volatile Memory for Artificial Intelligence Edge Applications." Micromachines 14, no. 6 (2023): 1175. http://dx.doi.org/10.3390/mi14061175.

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In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. In this paper, we propose a fully digital non-volatile CIM (DNV-CIM) macro with compressed coding look-up table (LUT) multiplier (CCLUTM) using the 40 nm technology, which is highly compatible with the standard commodity NOR Flash memory. We also provide a continuous accumulation

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Angizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben, and Deliang Fan. "MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (2022): 1–18. http://dx.doi.org/10.1145/3484222.

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Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time,

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Wu, Chien-Hung, Song-Nian Kuo, Kow-Ming Chang, et al. "Investigation of Microwave Annealing on Resistive Random Access Memory Device with Atmospheric Pressure Plasma Enhanced Chemical Vapor Deposition Deposited IGZO Layer." Journal of Nanoscience and Nanotechnology 20, no. 7 (2020): 4244–47. http://dx.doi.org/10.1166/jnn.2020.17561.

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Non-volatile memory (NVM) is essential in almost every consumer electronic products. The most prevalent NVM used nowadays is flash memory (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Letters, 9(1), p.526). However, some bottlenecks of flash memory have been identified, such as high operation voltage, low operation speed, and poor retention time. Resistive random access memory (RRAM) is considered to be the most promising one to become the next generation NVM device since its simple structure, fast program/erase speed, and low power consumptio

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Zha, Xiaojing, and Hao Ye. "FeFET-Based Computing-in-Memory Unit Circuit and Its Application." Nanomaterials 15, no. 4 (2025): 319. https://doi.org/10.3390/nano15040319.

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With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and

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Bauer, Anton J., Martin Lemberger, Tobias Erlbacher, and Wenke Weinreich. "High-K: Latest Developments and Perspectives." Materials Science Forum 573-574 (March 2008): 165–80. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.165.

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The paper reviews recent progress and current challenges in implementing high-k dielectrics in microelectronics. Logic devices, non-volatile-memories, DRAMs and low power mixedsignal components are found to be the technologies where high-k dielectrics are implemented or will be introduced soon. Two gate architectures have to be considerd: MOS with metal as gate electrode and MIM. In particular, Hf-silicates for logic and NVM devices in conventional MOS architecture and ZrO2 for DRAM cells in MIM architecture are discussed.

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Elyasi, Mehrdad, Chengkuo Lee, Cheng-Yu Hsieh, and Dim-Lee Kwong. "Multi-bit memory cell using long-range non-anchored actuation for high temperature applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (2013): 000152–59. http://dx.doi.org/10.4071/hiten-ta18.

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A novel micro-electro-mechanical (MEM) based non-volatile memory (NVM) is proposed. The storage principle is based on Lorentz's transduction, utilizing long-range motion of a non-anchored element which has current carrying sliding contact with a conductive path. Position of the moving element indicates the stored data in the multi-bit cell. Data is written in the cell with displacing the moving element by Lorentz's force, is read by utilizing differential port resistances, and is held by adhesion forces. Data writing at up to 300°C, and data retention and reading for higher temperatures are re

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