Relevant bibliographies by topics / Memory accesses

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Memory accesses'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "Memory accesses"

1

Heirman, Wim, Stijn Eyerman, Kristof Du Bois, and Ibrahim Hur. "Automatic Sublining for Efficient Sparse Memory Accesses." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–23. http://dx.doi.org/10.1145/3452141.

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Sparse memory accesses, which are scattered accesses to single elements of a large data structure, are a challenge for current processor architectures. Their lack of spatial and temporal locality and their irregularity makes caches and traditional stream prefetchers useless. Furthermore, performing standard caching and prefetching on sparse accesses wastes precious memory bandwidth and thrashes caches, deteriorating performance for regular accesses. Bypassing prefetchers and caches for sparse accesses, and fetching only a single element (e.g., 8 B) from main memory (subline access), can solve
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Achermann, Reto, Lukas Humbel, David Cock, and Timothy Roscoe. "Formalizing Memory Accesses and Interrupts." Electronic Proceedings in Theoretical Computer Science 244 (March 15, 2017): 66–116. http://dx.doi.org/10.4204/eptcs.244.4.

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Kim, Bo-Sung, and Jun-Dong Cho. "Maximizing Memory Data Reuse for Lower Power Motion Estimation." VLSI Design 14, no. 3 (2002): 299–305. http://dx.doi.org/10.1080/10655140290011096.

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This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an inefficiently large number of external memory accesses. Recently, to reduce the number of accesses in one search block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new appr
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CHOI, YOONSEO, and TAEWHAN KIM. "MEMORY ACCESS DRIVEN STORAGE ASSIGNMENT FOR VARIABLES IN EMBEDDED SYSTEM DESIGN." Journal of Circuits, Systems and Computers 15, no. 02 (2006): 145–68. http://dx.doi.org/10.1142/s0218126606003003.

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In this paper, we address the DRAM storage assignment problems of variables with an objective of maximizing the number of page/burst mode accesses. Specifically, (1) we solve the problem of variable alignment to memory for maximizing the use of page accesses by proposing a technique, called zone_alignment, which is based on the combination of an efficient 0-1 ILP (integer linear programming) formulation and the utilization of temporal locality of variables' accesses in code and (2) the approach used in (1) is then applied to solve the problem of variable alignment for maximizing the use of bur
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Tao, Jie, Wolfgang Karl, and Martin Schulz. "Memory Access Behavior Analysis of NUMA-Based Shared Memory Programs." Scientific Programming 10, no. 1 (2002): 45–53. http://dx.doi.org/10.1155/2002/790749.

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Shared memory applications running transparently on top of NUMA architectures often face severe performance problems due to bad data locality and excessive remote memory accesses. Optimizations with respect to data locality are therefore necessary, but require a fundamental understanding of an application's memory access behavior. The information necessary for this cannot be obtained using simple code instrumentation due to the implicit nature of the communication handled by the NUMA hardware, the large amount of traffic produced at runtime, and the fine access granularity in shared memory cod
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Cavus, Mustafa, Resit Sendag, and Joshua J. Yi. "Informed Prefetching for Indirect Memory Accesses." ACM Transactions on Architecture and Code Optimization 17, no. 1 (2020): 1–29. http://dx.doi.org/10.1145/3374216.

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Lin, Yuan, and David Padua. "Compiler analysis of irregular memory accesses." ACM SIGPLAN Notices 35, no. 5 (2000): 157–68. http://dx.doi.org/10.1145/358438.349322.

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Ainsworth, Sam, and Timothy M. Jones. "Software Prefetching for Indirect Memory Accesses." ACM Transactions on Computer Systems 36, no. 3 (2019): 1–34. http://dx.doi.org/10.1145/3319393.

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Esakkimuthu, G., H. S. Kim, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. "Investigating Memory System Energy Behavior Using Software and Hardware Optimizations." VLSI Design 12, no. 2 (2001): 151–65. http://dx.doi.org/10.1155/2001/70310.

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Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms and three widely used compiler optimization techniques used to reduce the memory system energy. Our presentation is in two parts. First, we focus on a set of memory-intensive benchmark codes and investigate their memory system energy behavior due to data accesses under hardware and compiler optimizations. Then, using four motion estimation codes, we look at the influenc
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Chen, Wei-Ming, Tei-Wei Kuo, and Pi-Cheng Hsiu. "Heterogeneity-aware Multicore Synchronization for Intermittent Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–22. http://dx.doi.org/10.1145/3476992.

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Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In partic
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Dissertations / Theses on the topic "Memory accesses"

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Österberg, Erik. "Profiling memory accesses on the ODROID-XU4." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-332800.

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Decoupled Access-Execute(DAE) is an innovative approach to optimize energy consumption of computer programs by splitting the program into two tasks; the first task is to access data, this is profoundly memory-bound and can be done with energy efficient cores. The second task is to execute and compute the data, which iscompute-bound and can be done with powerful cores. This thesis work aims todevelop a profiling tool that can measure the efficiency of DAE by investigating thecache misses in the original code and the DAE code (in the access and executephases). This was achieved by measuring the
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Ang, Su-Shin. "Handling data dependent memory accesses in custom hardware applications." Thesis, Imperial College London, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.501122.

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Lim, Nien Yi. "Separating instruction fetches from memory accesses ILAR (Instruction Line Associative Registers) /." Lexington, Ky. : [University of Kentucky Libraries], 2009. http://hdl.handle.net/10225/1121.

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Thesis (M.S.)--University of Kentucky, 2009.<br>Title from document title page (viewed on May 6, 2010). Document formatted into pages; contains: viii, 59 p. : ill. (some col.). Includes abstract and vita. Includes bibliographical references (p. 56-58).
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Jiang, Peng. "Enabling Efficient Parallelism for Applications with Dependences and Irregular Memory Accesses." The Ohio State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1563461701172592.

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Cramer, Tim Verfasser], Matthias [Akademischer Betreuer] Müller, and Joost-Pieter [Akademischer Betreuer] [Katoen. "Analyzing memory accesses for performance and correctness of parallel programs / Tim Cramer ; Matthias Müller, Joost-Pieter Katoen." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1161412042/34.

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Cramer, Tim [Verfasser], Matthias Akademischer Betreuer] Müller, and Joost-Pieter [Akademischer Betreuer] [Katoen. "Analyzing memory accesses for performance and correctness of parallel programs / Tim Cramer ; Matthias Müller, Joost-Pieter Katoen." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1161412042/34.

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Segura, Salvador Albert. "High-performance and energy-efficient irregular graph processing on GPU architectures." Doctoral thesis, Universitat Politècnica de Catalunya, 2021. http://hdl.handle.net/10803/671449.

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Graph processing is an established and prominent domain that is the foundation of new emerging applications in areas such as Data Analytics and Machine Learning, empowering applications such as road navigation, social networks and automatic speech recognition. The large amount of data employed in these domains requires high throughput architectures such as GPGPU. Although the processing of large graph-based workloads exhibits a high degree of parallelism, memory access patterns tend to be highly irregular, leading to poor efficiency due to memory divergence.In order to ameliorate these issues,
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Collington, James Robert. "Optically accessed electronic memory." Thesis, University of Cambridge, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.627357.

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Ali, Nawab. "Improving paging performance of memor-intensive applications with memory access pattern guided page replacement." Cincinnati, Ohio : University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=ucin1092701375.

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Bendifallah, Zakaria. "Généralisation de l’analyse de performance décrémentale vers l’analyse différentielle." Thesis, Versailles-St Quentin en Yvelines, 2015. http://www.theses.fr/2015VERS038V/document.

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Une des étapes les plus cruciales dans le processus d’analyse des performances d’une application est la détection des goulets d’étranglement. Un goulet étant tout évènement qui contribue à l’allongement temps d’exécution, la détection de ses causes est importante pour les développeurs d’applications afin de comprendre les défauts de conception et de génération de code. Cependant, la détection de goulets devient un art difficile. Dans le passé, des techniques qui reposaient sur le comptage du nombre d’évènements, arrivaient facilement à trouver les goulets. Maintenant, la complexité accrue des
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Books on the topic "Memory accesses"

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Gössel, Michael. Memory architecture & parallel access. Elsevier, 1994.

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Semiconductor, National. Random access memory databook. National Semiconductor, 1987.

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Denning, Peter J. Is random access memory random? Research Institute for Advanced Computer Science, NASA Ames Research Center, 1986.

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Sangyōshō, Japan Keizai. DRAM no juyō to kyōkyū no kankei oyobi sorera ga kokunai kakaku ni ataeta eikyō tō ni tsuite no teiryōteki bunseki to genʼin tankyū: Hōkokusho. Nomura Sōgō Kenkyūjo, 2005.

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Random thoughts: RAM random access memory. Nidahas Publication, 2005.

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Handōtai memori. Koronasha, 2008.

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1978-, Kishi Hirofumi, ed. Teikō henka memori no chiteki zairyō sekkei: Intelligent/directed materials design for resistance random access memory. Ōsaka Daigaku Shuppankai, 2012.

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Nonvolatile memories: Materials, device and applications. American Scientific Publishers, 2012.

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Kanad, Chakraborty, ed. Testing and testable design of high-density random-access memories. Kluwer Academic, 1996.

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Inc, Toshiba America, and Toshiba America. Toshiba MOS memory products data book. Toshiba America, 1987.

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Book chapters on the topic "Memory accesses"

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Balakrishnan, Gogul, and Thomas Reps. "Analyzing Memory Accesses in x86 Executables." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-24723-4_2.

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Venable, Michael, Mohamed R. Chouchane, Md Enamul Karim, and Arun Lakhotia. "Analyzing Memory Accesses in Obfuscated x86 Executables." In Detection of Intrusions and Malware, and Vulnerability Assessment. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11506881_1.

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Unsal, Osman S., Zhenlin Wang, Israel Koren, C. Mani Krishna, and Csaba Andras Moritz. "An Analysis of Scalar Memory Accesses in Embedded and Multimedia Systems." In High Performance Memory Systems. Springer New York, 2004. http://dx.doi.org/10.1007/978-1-4419-8987-1_13.

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Gesellensetter, Lars, and Sabine Glesner. "Interprocedural Speculative Optimization of Memory Accesses to Global Variables." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-85451-7_38.

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Wu, Lin, Qingfeng Zhuge, Edwin H. M. Sha, and Zhilong Sun. "Efficient Scheduling with Intensive In-Memory File Accesses Considering Bandwidth Constraint on Memory Bus." In Algorithms and Architectures for Parallel Processing. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-27122-4_39.

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Chi, Chi-Hung, and Jun-Li Yuan. "Sequential Unification and Aggressive Lookahead Mechanisms for Data Memory Accesses." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48387-x_3.

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Paulino, Nuno, João Canas Ferreira, and João M. P. Cardoso. "Architecture for Transparent Binary Acceleration of Loops with Memory Accesses." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36812-7_12.

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Chen, Chien-Ting, Yoshi Shih-Chieh Huang, Yuan-Ying Chang, et al. "Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs." In Advanced Information Systems Engineering. Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-44917-2_15.

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Mazurek, Przemysław. "Optimization of Memory Accesses for CUDA Architecture and Image Warping Algorithms." In Advances in Intelligent Systems and Computing. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-32384-3_16.

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Abdulla, Parosh Aziz, Mohamed Faouzi Atig, Adwait Godbole, S. Krishna, and Viktor Vafeiadis. "The Decidability of Verification under PS 2.0." In Programming Languages and Systems. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-72019-3_1.

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AbstractWe consider the reachability problem for finite-state multi-threaded programs under thepromising semantics() of Lee et al., which captures most common program transformations. Since reachability is already known to be undecidable in the fragment of with only release-acquire accesses (-), we consider the fragment with only relaxed accesses and promises (). We show that reachability under is undecidable in general and that it becomes decidable, albeit non-primitive recursive, if we bound the number of promises.Given these results, we consider a bounded version of the reachability problem. To this end, we bound both the number of promises and of “view-switches”, i.e., the number of times the processes may switch their local views of the global memory. We provide a code-to-code translation from an input program under (with relaxed and release-acquire memory accesses along with promises) to a program under SC, thereby reducing the bounded reachability problem under to the bounded context-switching problem under SC. We have implemented a tool and tested it on a set of benchmarks, demonstrating that typical bugs in programs can be found with a small bound.
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Conference papers on the topic "Memory accesses"

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Srivastava, Ajitesh, Angelos Lazaris, Benjamin Brooks, Rajgopal Kannan, and Viktor K. Prasanna. "Predicting memory accesses." In MEMSYS '19: The International Symposium on Memory Systems. ACM, 2019. http://dx.doi.org/10.1145/3357526.3357549.

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Akin, Berkin, Chiachen Chou, Jongsoo Park, Christopher J. Hughes, and Rajat Agarwal. "Dynamic fine-grained sparse memory accesses." In MEMSYS '18: The International Symposium on Memory Systems. ACM, 2018. http://dx.doi.org/10.1145/3240302.3240416.

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Ko, Yohan, Hyunjun Kim, and Hwansoo Han. "Escalating Memory Accesses to Shared Memory by Profiling Reuse." In IMCOM '16: The 10th International Conference on Ubiquitous Information Management and Communication. ACM, 2016. http://dx.doi.org/10.1145/2857546.2857579.

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Ainsworth, Sam, and Timothy M. Jones. "Software prefetching for indirect memory accesses." In 2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO). IEEE, 2017. http://dx.doi.org/10.1109/cgo.2017.7863749.

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Lin, Yuan, and David Padua. "Compiler analysis of irregular memory accesses." In the ACM SIGPLAN 2000 conference. ACM Press, 2000. http://dx.doi.org/10.1145/349299.349322.

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Halstead, Robert J., Jason Villarreal, and Walid Najjar. "Exploring irregular memory accesses on FPGAs." In the first workshop. ACM Press, 2011. http://dx.doi.org/10.1145/2089142.2089151.

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Goel, S., M. Shaaban, T. Darwish, H. Mahmoud, and M. Bayoumi. "Memory accesses reduction for MIME algorithm." In 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698). IEEE, 2003. http://dx.doi.org/10.1109/icme.2003.1221739.

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Noll, Stefan, Jens Teubner, Norman May, and Alexander Böhm. "Analyzing memory accesses with modern processors." In SIGMOD/PODS '20: International Conference on Management of Data. ACM, 2020. http://dx.doi.org/10.1145/3399666.3399896.

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Guo, Xiaomei, and Haiyun Han. "The Research of a Memory Accesses Behavior on Non-Uniform Memory Access Architecture." In 2019 10th International Conference on Information Technology in Medicine and Education (ITME). IEEE, 2019. http://dx.doi.org/10.1109/itme.2019.00174.

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Jorda, Jacques, and Abdelaziz M'zoughi. "Isomorphic Recursive Splitting: Conflict-Free Memory Accesses for Structured Memory." In 2012 41st International Conference on Parallel Processing Workshops (ICPPW). IEEE, 2012. http://dx.doi.org/10.1109/icppw.2012.78.

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Reports on the topic "Memory accesses"

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Balakrishnan, Gogul, and Thomas Reps. Analyzing Memory Accesses in x86 Executables. Defense Technical Information Center, 2006. http://dx.doi.org/10.21236/ada449077.

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Cypher, Robert. Valiant's Maximum Algorithm with Sequential Memory Accesses. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada203713.

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Daily, Jeffrey, and Dan Berghofer. Efficient Memory Access with NumPy Global Arrays using Local Memory Access. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1136617.

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Psaltis, Demetri. Holographic Random Access Memory. Defense Technical Information Center, 1997. http://dx.doi.org/10.21236/ada329446.

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Cerjan, C., and B. P. Law. Magnetic Random Access Memory (MRAM) Device Development. Office of Scientific and Technical Information (OSTI), 2000. http://dx.doi.org/10.2172/15006522.

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Recio, R., B. Metzler, P. Culley, J. Hilland, and D. Garcia. A Remote Direct Memory Access Protocol Specification. RFC Editor, 2007. http://dx.doi.org/10.17487/rfc5040.

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Shah, H., F. Marti, W. Noureddine, A. Eiriksson, and R. Sharp. Remote Direct Memory Access (RDMA) Protocol Extensions. RFC Editor, 2014. http://dx.doi.org/10.17487/rfc7306.

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Donohoe, Gregory W. Magnetic Random Access Memory for Embedded Computing. Defense Technical Information Center, 2007. http://dx.doi.org/10.21236/ada474855.

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Kelsey, John, and Bruce Schneier. Authenticating Secure Tokens Using Slow Memory Access. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada385266.

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Sharp, R., and S. Wise. Enhanced Remote Direct Memory Access (RDMA) Connection Establishment. Edited by A. Kanevsky and C. Bestler. RFC Editor, 2012. http://dx.doi.org/10.17487/rfc6581.

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