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Journal articles on the topic 'Memory accesses'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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1

Heirman, Wim, Stijn Eyerman, Kristof Du Bois, and Ibrahim Hur. "Automatic Sublining for Efficient Sparse Memory Accesses." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–23. http://dx.doi.org/10.1145/3452141.

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Sparse memory accesses, which are scattered accesses to single elements of a large data structure, are a challenge for current processor architectures. Their lack of spatial and temporal locality and their irregularity makes caches and traditional stream prefetchers useless. Furthermore, performing standard caching and prefetching on sparse accesses wastes precious memory bandwidth and thrashes caches, deteriorating performance for regular accesses. Bypassing prefetchers and caches for sparse accesses, and fetching only a single element (e.g., 8 B) from main memory (subline access), can solve

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Achermann, Reto, Lukas Humbel, David Cock, and Timothy Roscoe. "Formalizing Memory Accesses and Interrupts." Electronic Proceedings in Theoretical Computer Science 244 (March 15, 2017): 66–116. http://dx.doi.org/10.4204/eptcs.244.4.

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3

Kim, Bo-Sung, and Jun-Dong Cho. "Maximizing Memory Data Reuse for Lower Power Motion Estimation." VLSI Design 14, no. 3 (2002): 299–305. http://dx.doi.org/10.1080/10655140290011096.

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This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an inefficiently large number of external memory accesses. Recently, to reduce the number of accesses in one search block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new appr

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CHOI, YOONSEO, and TAEWHAN KIM. "MEMORY ACCESS DRIVEN STORAGE ASSIGNMENT FOR VARIABLES IN EMBEDDED SYSTEM DESIGN." Journal of Circuits, Systems and Computers 15, no. 02 (2006): 145–68. http://dx.doi.org/10.1142/s0218126606003003.

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In this paper, we address the DRAM storage assignment problems of variables with an objective of maximizing the number of page/burst mode accesses. Specifically, (1) we solve the problem of variable alignment to memory for maximizing the use of page accesses by proposing a technique, called zone_alignment, which is based on the combination of an efficient 0-1 ILP (integer linear programming) formulation and the utilization of temporal locality of variables' accesses in code and (2) the approach used in (1) is then applied to solve the problem of variable alignment for maximizing the use of bur

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Tao, Jie, Wolfgang Karl, and Martin Schulz. "Memory Access Behavior Analysis of NUMA-Based Shared Memory Programs." Scientific Programming 10, no. 1 (2002): 45–53. http://dx.doi.org/10.1155/2002/790749.

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Shared memory applications running transparently on top of NUMA architectures often face severe performance problems due to bad data locality and excessive remote memory accesses. Optimizations with respect to data locality are therefore necessary, but require a fundamental understanding of an application's memory access behavior. The information necessary for this cannot be obtained using simple code instrumentation due to the implicit nature of the communication handled by the NUMA hardware, the large amount of traffic produced at runtime, and the fine access granularity in shared memory cod

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Cavus, Mustafa, Resit Sendag, and Joshua J. Yi. "Informed Prefetching for Indirect Memory Accesses." ACM Transactions on Architecture and Code Optimization 17, no. 1 (2020): 1–29. http://dx.doi.org/10.1145/3374216.

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7

Lin, Yuan, and David Padua. "Compiler analysis of irregular memory accesses." ACM SIGPLAN Notices 35, no. 5 (2000): 157–68. http://dx.doi.org/10.1145/358438.349322.

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8

Ainsworth, Sam, and Timothy M. Jones. "Software Prefetching for Indirect Memory Accesses." ACM Transactions on Computer Systems 36, no. 3 (2019): 1–34. http://dx.doi.org/10.1145/3319393.

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Esakkimuthu, G., H. S. Kim, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. "Investigating Memory System Energy Behavior Using Software and Hardware Optimizations." VLSI Design 12, no. 2 (2001): 151–65. http://dx.doi.org/10.1155/2001/70310.

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Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms and three widely used compiler optimization techniques used to reduce the memory system energy. Our presentation is in two parts. First, we focus on a set of memory-intensive benchmark codes and investigate their memory system energy behavior due to data accesses under hardware and compiler optimizations. Then, using four motion estimation codes, we look at the influenc

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Chen, Wei-Ming, Tei-Wei Kuo, and Pi-Cheng Hsiu. "Heterogeneity-aware Multicore Synchronization for Intermittent Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–22. http://dx.doi.org/10.1145/3476992.

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Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In partic

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Carter, John B., Wilson C. Hsieh, Leigh B. Stoller, Mark Swanson, Lixin Zhang, and Sally A. McKee. "Impulse: Memory System Support for Scientific Applications." Scientific Programming 7, no. 3-4 (1999): 195–209. http://dx.doi.org/10.1155/1999/209416.

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Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application‐specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In thi

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12

Saeed, Ahmed, Ali Ahmadinia, and Mike Just. "Tag-Protector: An Effective and Dynamic Detection of Illegal Memory Accesses through Compile Time Code Instrumentation." Advances in Software Engineering 2016 (June 19, 2016): 1–19. http://dx.doi.org/10.1155/2016/9842936.

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Programming languages permitting immediate memory accesses through pointers often result in applications having memory-related errors, which may lead to unpredictable failures and security vulnerabilities. A lightweight solution is presented in this paper to tackle such illegal memory accesses dynamically in C/C++ based applications. We propose a new and effective method of instrumenting an application’s source code at compile time in order to detect illegal spatial and temporal memory accesses. It is based on creating tags to be coupled with each memory allocation and then placing additional

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13

Jung, Tina, Fabian Ritter, and Sebastian Hack. "PICO." ACM Transactions on Architecture and Code Optimization 18, no. 4 (2021): 1–27. http://dx.doi.org/10.1145/3460434.

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Memory safety violations such as buffer overflows are a threat to security to this day. A common solution to ensure memory safety for C is code instrumentation. However, this often causes high execution-time overhead and is therefore rarely used in production. Static analyses can reduce this overhead by proving some memory accesses in bounds at compile time. In practice, however, static analyses may fail to verify in-bounds accesses due to over-approximation. Therefore, it is important to additionally optimize the checks that reside in the program. In this article, we present PICO, an approach

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Kortelainen, Matti J., and Martin Kwok. "Performance of CUDA Unified Memory in CMS Heterogeneous Pixel Reconstruction." EPJ Web of Conferences 251 (2021): 03035. http://dx.doi.org/10.1051/epjconf/202125103035.

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The management of separate memory spaces of CPUs and GPUs brings an additional burden to the development of software for GPUs. To help with this, CUDA unified memory provides a single address space that can be accessed from both CPU and GPU. The automatic data transfer mechanism is based on page faults generated by the memory accesses. This mechanism has a performance cost, that can be with explicit memory prefetch requests. Various hints on the inteded usage of the memory regions can also be given to further improve the performance. The overall effect of unified memory compared to an explicit

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15

Franco, Juliana, and Sophia Drossopoulou. "Behavioural types for non-uniform memory accesses." Electronic Proceedings in Theoretical Computer Science 203 (February 10, 2016): 109–20. http://dx.doi.org/10.4204/eptcs.203.9.

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16

Ha, Phuong Hoai, Philippas Tsigas, and Otto J. Anshus. "The Synchronization Power of Coalesced Memory Accesses." IEEE Transactions on Parallel and Distributed Systems 21, no. 7 (2010): 939–53. http://dx.doi.org/10.1109/tpds.2009.135.

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17

Harrison, Peter G., Naresh M. Patel, and Soraya Zertal. "Response time distribution of flash memory accesses." Performance Evaluation 67, no. 4 (2010): 248–59. http://dx.doi.org/10.1016/j.peva.2009.10.003.

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18

Almog, Eli, and Hadas Shachnai. "Scheduling memory accesses through a shared bus." Performance Evaluation 46, no. 2-3 (2001): 193–218. http://dx.doi.org/10.1016/s0166-5316(01)00050-5.

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19

Fiorin, Leandro, Gianluca Palermo, Slobodan Lukovic, Valerio Catalano, and Cristina Silvano. "Secure Memory Accesses on Networks-on-Chip." IEEE Transactions on Computers 57, no. 9 (2008): 1216–29. http://dx.doi.org/10.1109/tc.2008.69.

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20

Nazaré, Henrique, Izabela Maffra, Willer Santos, Leonardo Barbosa, Laure Gonnord, and Fernando Magno Quintão Pereira. "Validation of memory accesses through symbolic analyses." ACM SIGPLAN Notices 49, no. 10 (2014): 791–809. http://dx.doi.org/10.1145/2714064.2660205.

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21

El-Zawawy, Mohamed A. "Frequent Statement and Dereference Elimination for Imperative and Object-Oriented Distributed Programs." Scientific World Journal 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/839121.

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This paper introduces new approaches for the analysis offrequent statement and dereference eliminationfor imperative and object-oriented distributed programs running on parallel machines equipped with hierarchical memories. The paper uses languages whose address spaces are globally partitioned. Distributed programs allow defining data layout and threads writing to and reading from other thread memories. Three type systems (for imperative distributed programs) are the tools of the proposed techniques. The first type system defines for every program point a set of calculated (ready) statements a

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22

Bivens, Kristin Marie, and Kelli Cargile Cook. "Coordinating Distributed Memory." Journal of Business and Technical Communication 32, no. 3 (2018): 285–307. http://dx.doi.org/10.1177/1050651918762028.

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This case study of an environmental engineer’s proposal-writing process reveals how the engineer (Beatrice) reifies, archives, and accesses her distributed memory across physical and digital sources in order to write proposals. Based on the authors’ observations of Beatrice’s proposal-writing process and their interviews with her, they arrived at three key conclusions: Beatrice distributes her memory across multiple physical and digital sources, the (spreadsheet) product calculator helps Beatrice to manage her cognitive load and relieve her working memory, and the product calculator allows Bea

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23

Kim, DaeHwan. "Experiences of the GPU Thread Configuration and Shared Memory." European Journal of Engineering Research and Science 3, no. 7 (2018): 12. http://dx.doi.org/10.24018/ejers.2018.3.7.788.

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Nowadays, GPU processors are widely used for general-purpose parallel computation applications. In the GPU programming, thread and block configuration is one of the most important decisions to be made, which increases parallelism and hides instruction latency. However, in many cases, it is often difficult to have sufficient parallelism to hide all the latencies, where the high latencies are often caused by the global memory accesses. In order to reduce the number of those accesses, the shared memory is instead used which is much faster than the global memory being located on a chip. The perfor

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24

Ahmadi, Mahmood, and Stephan Wong. "A Cache Architecture for Counting Bloom Filters: Theory and Application." Journal of Electrical and Computer Engineering 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/475865.

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Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, for example, utilizing multilevel memory hierarchies, special hardware architectures, and hardware threading. In this paper, we introduce a multilevel memory architecture for counting Bloom filters. Based on the probabilities of incrementing of the counters in the counting Bloom filter, a multi-level cache architecture called the cached counting Bloom filter (CCBF) is presented, where each cache level stores the items with the

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25

Park, Moonju. "Limiting CPU Frequency Scaling Considering Main Memory Accesses." KIISE Transactions on Computing Practices 20, no. 9 (2014): 483–91. http://dx.doi.org/10.5626/ktcp.2014.20.9.483.

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26

Takakubo, Hajime, Cong-Kha Pham, and Katsufusa Shono. "A bitmap memory bank which allows block accesses." Electronics and Communications in Japan (Part II: Electronics) 74, no. 8 (1991): 88–98. http://dx.doi.org/10.1002/ecjb.4420740811.

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27

CRAUSER, A., P. FERRAGINA, K. MEHLHORN, U. MEYER, and E. A. RAMOS. "RANDOMIZED EXTERNAL-MEMORY ALGORITHMS FOR LINE SEGMENT INTERSECTION AND OTHER GEOMETRIC PROBLEMS." International Journal of Computational Geometry & Applications 11, no. 03 (2001): 305–37. http://dx.doi.org/10.1142/s0218195901000523.

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We show that the well-known random incremental construction of Clarkson and Shor18 can be adapted to provide efficient external-memory algorithms for some geometric problems. In particular, as the main result, we obtain an optimal randomized algorithm for the problem of computing the trapezoidal decomposition determined by a set of N line segments in the plane with K pairwise intersections, that requires [Formula: see text] expected disk accesses, where M is the size of the available internal memory and B is the size of the block transfer. The approach is sufficiently general to derive algorit

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Ditmar, Johan, Steve McKeever, and Alex Wilson. "Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation." International Journal of Reconfigurable Computing 2008 (2008): 1–14. http://dx.doi.org/10.1155/2008/674340.

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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involv

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Fang, Juan, Jiajia Lu, Mengxuan Wang, and Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.

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With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia an

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Prihozhy, A. A. "Simulation of direct mapped, k-way and fully associative cache on all pairs shortest paths algorithms." «System analysis and applied information science», no. 4 (December 30, 2019): 10–18. http://dx.doi.org/10.21122/2309-4923-2019-4-10-18.

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Caches are intermediate level between fast CPU and slow main memory. It aims to store copies of frequently used data and to reduce the access time to the main memory. Caches are capable of exploiting temporal and spatial localities during program execution. When the processor accesses memory, the cache behavior depends on if the data is in cache: a cache hit occurs if it is, and, a cache miss occurs, otherwise. In the last case, the cache may have to evict other data. The misses produce processor stalls and slow down the computations. The replacement policy chooses a data to evict, trying to p

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Yazdani, Samar, Joël Cambonie, and Bernard Pottier. "Coordinated concurrent memory accesses on a reconfigurable multimedia accelerator." Microprocessors and Microsystems 33, no. 1 (2009): 13–23. http://dx.doi.org/10.1016/j.micpro.2008.08.005.

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32

Hollevoet, L., K. Denolf, F. Cotthoor, A. Dewilde, and F. Louagie. "Cut memory accesses for lower-power displays [handheld devices]." Electronics Systems and Software 2, no. 5 (2004): 20–24. http://dx.doi.org/10.1049/ess:20040503.

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33

Wang, Meng, Zili Shao, and Jingling Xue. "On Reducing Hidden Redundant Memory Accesses for DSP Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 6 (2011): 997–1010. http://dx.doi.org/10.1109/tvlsi.2010.2043963.

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34

Brorsson, Mats, and Per Stenström. "Characterising and modelling shared memory accesses in multiprocessor programs." Parallel Computing 22, no. 6 (1996): 869–93. http://dx.doi.org/10.1016/0167-8191(96)00025-7.

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35

Dias, Ricardo, João Lourenço, and Gonçalo Cunha. "Developing libraries using software transactional memory." Computer Science and Information Systems 5, no. 2 (2008): 103–17. http://dx.doi.org/10.2298/csis0802103d.

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Software transactional memory is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM). This paper discusses how to support revertible operations, such as memory allocation and release, within software libraries that will be used in software memory transactional contexts. The proposal is based in the extension of the transaction life cycle state diagram with new states associated to the execution of user-defined handlers. The proposed approach is evaluated in terms of functionality and performance by way of

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Daylight, E. G., D. Atienza, A. Vandecappelle, F. Catthoor, and J. M. Mendias. "Memory-access-aware data structure transformations for embedded software with dynamic data accesses." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 3 (2004): 269–80. http://dx.doi.org/10.1109/tvlsi.2004.824303.

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37

Azevedo, Arnaldo, and Ben Juurlink. "A Multidimensional Software Cache for Scratchpad-Based Systems." International Journal of Embedded and Real-Time Communication Systems 1, no. 4 (2010): 1–20. http://dx.doi.org/10.4018/jertcs.2010100101.

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In many kernels of multimedia applications, the working set is predictable, making it possible to schedule the data transfers before the computation. Many other kernels, however, process data that is known just before it is needed or have working sets that do not fit in the scratchpad memory. Furthermore, multimedia kernels often access two or higher dimensional data structures and conventional software caches have difficulties to exploit the data locality exhibited by these kernels. For such kernels, the authors present a Multidimensional Software Cache (MDSC), which stores 1- 4 dimensional b

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38

Fujieda, Naoki, Ryo Yamauchi, Hiroki Fujita, and Shuichi Ichikawa. "A Virtual Cache for Overlapped Memory Accesses of Path ORAM." International Journal of Networking and Computing 7, no. 2 (2017): 106–23. http://dx.doi.org/10.15803/ijnc.7.2_106.

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Peters, Benjamin, Benjamin Rahm, Stefan Czoschke, Catherine Barnes, Jochen Kaiser, and Christoph Bledowski. "Sequential whole report accesses different states in visual working memory." Journal of Experimental Psychology: Learning, Memory, and Cognition 44, no. 4 (2018): 588–603. http://dx.doi.org/10.1037/xlm0000466.

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40

Zhu, Jingchen, Guangyu Sun, Xian Zhang, et al. "Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (2020): 2279–92. http://dx.doi.org/10.1109/tcad.2019.2948914.

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41

Harper, D. T. "Block, multistride vector, and FFT accesses in parallel memory systems." IEEE Transactions on Parallel and Distributed Systems 2, no. 1 (1991): 43–51. http://dx.doi.org/10.1109/71.80188.

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42

Zhuge, Qingfeng, Hao Zhang, Edwin Hsing-Mean Sha, Rui Xu, Jun Liu, and Shengyu Zhang. "Exploring Efficient Architectures on Remote In-Memory NVM over RDMA." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–20. http://dx.doi.org/10.1145/3477004.

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Efficiently accessing remote file data remains a challenging problem for data processing systems. Development of technologies in non-volatile dual in-line memory modules (NVDIMMs), in-memory file systems, and RDMA networks provide new opportunities towards solving the problem of remote data access. A general understanding about NVDIMMs, such as Intel Optane DC Persistent Memory (DCPM), is that they expand main memory capacity with a cost of multiple times lower performance than DRAM. With an in-depth exploration presented in this paper, however, we show an interesting finding that the potentia

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Cho, Won, and Joonho Kong. "Memory and Cache Contention Denial-of-Service Attack in Mobile Edge Devices." Applied Sciences 11, no. 5 (2021): 2385. http://dx.doi.org/10.3390/app11052385.

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In this paper, we introduce a memory and cache contention denial-of-service attack and its hardware-based countermeasure. Our attack can significantly degrade the performance of the benign programs by hindering the shared resource accesses of the benign programs. It can be achieved by a simple C-based malicious code while degrading the performance of the benign programs by 47.6% on average. As another side-effect, our attack also leads to greater energy consumption of the system by 2.1× on average, which may cause shorter battery life in the mobile edge devices. We also propose detection and m

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Mittal, Shaily, and Nitin. "Memory Map: A Multiprocessor Cache Simulator." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.

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Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an opti

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MOTLAGH, BAHMAN S., and RONALD F. DeMARA. "PERFORMANCE OF SCALABLE SHARED-MEMORY ARCHITECTURES." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 1–22. http://dx.doi.org/10.1142/s0218126600000068.

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Analytical models were developed and simulations of memory latency were performed for Uniform Memory Access (UMA), Non-Uniform Memory Access (NUMA), Local-Remote-Global (LRG), and RCR architectures for hit rates from 0.1 to 0.9 in steps of 0.1, memory access times of 10 to 100 ns, proportions of read/write access from 0.01 to 0.1, and block sizes of 8 to 64 words. The RCR architecture provides favorable performance over UMA and NUMA architectures for all ranges of application and system parameters. RCR outperforms LRG architectures when the hit rates of the processor cache exceed 80%and replic

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Rahozin, D. V., and A. Yu Doroshenko. "Extended performance accounting using Valgrind tool." PROBLEMS IN PROGRAMMING, no. 2 (June 2021): 054–62. http://dx.doi.org/10.15407/pp2021.02.054.

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Modern workloads, parallel or sequential, usually suffer from insufficient memory and computing performance. Common trends to improve workload performance include the utilizations of complex functional units or coprocessors, which are able not only to provide accelerated computations but also independently fetch data from memory generating complex address patterns, with or without support of control flow operations. Such coprocessors usually are not adopted by optimizing compilers and should be utilized by special application interfaces by hand. On the other hand, memory bottlenecks may be avo

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Li, Shuo, Nong Xiao, Peng Wang, et al. "RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses." IEEE Transactions on Computers 68, no. 2 (2019): 239–54. http://dx.doi.org/10.1109/tc.2018.2868368.

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48

Souahi, Mohamed Salah, and Mohamed Ben Mohammed. "NUCA-2A: A New Adaptive and Behavior Aware Block Placement Process." Recent Patents on Computer Science 12, no. 2 (2019): 101–9. http://dx.doi.org/10.2174/2213275911666181114113340.

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Background: The last three decades were marked by a spectacular evolution of CPUs. Both cores number on chip and shared Low Level Cache (LLC) size are increasing what makes LLC the bottleneck's system. One major weakness of future cache memory hierarchies will be to carry out memory blocks availability for vertical requests, with no consideration to horizontal proximity to cores. Simulations show that some LLC accesses cost more latency cycles than off-chip accesses. Objective: This paper presents a new adaptive and blocks behavior aware process, called NUCA-2A. It manages blocks in LLC in a p

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Qian, Cheng, Libo Huang, Qi Yu, and Zhiying Wang. "CHAM: Improving Prefetch Efficiency Using a Composite Hierarchy-Aware Method." Journal of Circuits, Systems and Computers 27, no. 07 (2018): 1850114. http://dx.doi.org/10.1142/s0218126618501141.

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Hardware prefetching has always been a crucial mechanism to improve processor performance. However, an efficient prefetch operation requires a guarantee of high prefetch accuracy; otherwise, it may degrade system performance. Prior studies propose an adaptive priority controlling method to make better use of prefetch accesses, which improves performance in two-level cache systems. However, this method does not perform well in a more complex memory hierarchy, such as a three-level cache system. Thus, it is still necessary to explore the efficiency of prefetch, in particular, in complex hierarch

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FRAGUELA, BASILIO B., RAMÓN DOALLO, and EMILIO L. ZAPATA. "MEMORY HIERARCHY PERFORMANCE PREDICTION FOR BLOCKED SPARSE ALGORITHMS." Parallel Processing Letters 09, no. 03 (1999): 347–60. http://dx.doi.org/10.1142/s0129626499000323.

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Abstract:

Nowadays the performance gap between processors and main memory makes an efficient usage of the memory hierarchy necessary for good program performance. Several techniques have been proposed for this purpose. Nevertheless most of them consider only regular access patterns, while many scientific and numerical applications give place to irregular patterns. A typical case is that of indirect accesses due to the use of compressed storage formats for sparse matrices. This paper describes an analytic approach to model both regular and irregular access patterns. The application modeled is an optimize

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