Relevant bibliographies by topics / Memory and power applications

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Memory and power applications'

Author: Grafiati
Published: 7 July 2024
Last updated: 31 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Memory and power applications.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Memory and power applications"

1

Zhang, Kaiqiang, Dongyang Ou, Congfeng Jiang, Yeliang Qiu, and Longchuan Yan. "Power and Performance Evaluation of Memory-Intensive Applications." Energies 14, no. 14 (2021): 4089. http://dx.doi.org/10.3390/en14144089.

Full text
Abstract:
In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memor
APA, Harvard, Vancouver, ISO, and other styles
2

Kumar, S., M. Santhanalakshmi, and R. Navaneethakrishnan. "Content addressable memory for energy efficient computing applications." Scientific Temper 14, no. 02 (2023): 430–36. http://dx.doi.org/10.58414/scientifictemper.2023.14.2.30.

Full text
Abstract:
Content Addressable Memory (CAM) also known as associate memory isa special kind of semiconductor memory device that works differently from conventional Random Access Memory (RAM). A Content Addressable Memory is a memory unit that matches content over a single clock rather than using addresses. Its inherent parallel search mechanism makes it more advantageous than RAM in terms of speed of search operation. Designers aim to reduce two design characteristics: increasing silicon size and power consumption. As the need for CAM increases, the problem of power consumption also increases. Recent res
APA, Harvard, Vancouver, ISO, and other styles
3

Zuo, Ze Yu, Wei Hu, Rui Xin Hu, Heng Xiong, Wen Bin Du, and Xiu Cai. "Efficient Scratchpad Memory Management for Mobile Multimedia Application." Advanced Materials Research 748 (August 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amr.748.932.

Full text
Abstract:
Mobile devices have been popular in recent years and the proliferation of mobile devices inspires the interest in mobile multimedia applications. However, memory is always the bottleneck in the traditional memory hierarchy. Scratchpad memory (SPM) is a promising on-chip SRAM to solve such problem. It has faster access time and less power-consumption compared to cache and off-chip memory. In this paper, we propose the efficient scratchpad memory management approach for mobile multimedia applications. SPM is partitioned for the assignment of the slices of the applications based on the profiling
APA, Harvard, Vancouver, ISO, and other styles
4

Kumar Lamba, Anil, and Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.

Full text
Abstract:
The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less powe
APA, Harvard, Vancouver, ISO, and other styles
5

Tyler, Neil. "Tempo Targets Low-Power Chips for AI Applications." New Electronics 52, no. 13 (2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61557-8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Tatas, K., D. Soudris, and A. Thanailakis. "Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms." Journal of Embedded Computing 1, no. 3 (2005): 353–62. https://doi.org/10.3233/emc-2005-00038.

Full text
Abstract:
An optimization methodology that combines high-level exploration with Register Transfer Level (RTL) design for the power-efficient estimation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. A case study of three popular multimedia kernels is performed for a number of different FPGA devices. Comparisons among implementations w
APA, Harvard, Vancouver, ISO, and other styles
7

Fang, Juan, Jiajia Lu, Mengxuan Wang, and Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.

Full text
Abstract:
With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia an
APA, Harvard, Vancouver, ISO, and other styles
8

Birla, Shilpi. "Variability aware FinFET SRAM cell with improved stability and power for low power applications." Circuit World 45, no. 4 (2019): 196–207. http://dx.doi.org/10.1108/cw-12-2018-0098.

Full text
Abstract:
Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered t
APA, Harvard, Vancouver, ISO, and other styles
9

Marchal, P., J. I. Gomez, D. Atienza, S. Mamagkakis, and F. Catthoor. "Power aware data and memory management for dynamic applications." IEE Proceedings - Computers and Digital Techniques 152, no. 2 (2005): 224. http://dx.doi.org/10.1049/ip-cdt:20045077.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

K, Bharathi, and Vijayakumar S. "QCA Design of Encoder for Low Power Memory Applications." International Journal of Electronics and Communication Engineering 3, no. 11 (2016): 13–15. http://dx.doi.org/10.14445/23488549/ijece-v3i11p114.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Memory and power applications"

1

Wang, Xin. "Power Efficient Embedded Memory Design for Mobile Video Applications." Thesis, North Dakota State University, 2015. https://hdl.handle.net/10365/27621.

Full text
Abstract:
This thesis mainly addresses the issue of low-power technology for streaming media applications. In order to ensure high output video quality under low-voltage supply, the proposed 8-bit pixel memory is sized by different bit positions. A novel MSEpixel estimation method is then developed according to bit failure rates to directly evaluate the video quality for every 8-bit sizing combination. Based on this estimation, one area-priory and one quality-priority mobile video applications are proposed by SPIDER algorithms. The results show that both luma and chroma data should be considered.
APA, Harvard, Vancouver, ISO, and other styles
2

SELMO, SIMONE. "Functional analysis of In-based nanowires for low power phase change memory applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/153247.

Full text
Abstract:
Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to
APA, Harvard, Vancouver, ISO, and other styles
3

Morrison, Matthew Arthur. "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications." Scholar Commons, 2013. https://scholarcommons.usf.edu/etd/5082.

Full text
Abstract:
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Adiabatic logic is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architectures. Production of cost-effective Secure Integrated Chips, such as Smart Cards,
APA, Harvard, Vancouver, ISO, and other styles
4

Ramclam, Kenneth M. "Low-Power and Robust Level-Shifter with Contention Mitigation for Memory and Standalone Applications." Scholar Commons, 2015. https://scholarcommons.usf.edu/etd/5555.

Full text
Abstract:
The scaling down of transistor sizes has imposed significant challenges in today's technology. Memories such as eDRAM, are experiencing poor retention time because of challenges such as reference voltage variation, high transistor leakage, and low cell capacitance. It can be seen that we must consider not only the first order effects, but also the second order effects to ensure we keep up with current technology trends such as Moore's law. In this thesis we explore various circuit level techniques on level shifters in order to achieve better retention time. With our research, we have addressed
APA, Harvard, Vancouver, ISO, and other styles
5

Lai, Farley. "Stream processing optimizations for mobile sensing applications." Diss., University of Iowa, 2017. https://ir.uiowa.edu/etd/5797.

Full text
Abstract:
Mobile sensing applications (MSAs) are an emerging class of applications that process continuous sensor data streams to make time-sensitive inferences. Representative application domains range from environmental monitoring, context-aware services to recognition of physical activities and social interactions. Example applications involve city air quality assessment, indoor localization, pedometer and speaker identification. The common application workflow is to read data streams from the sensors (e.g, accelerometers, microphone, GPS), extract statistical features, and then present the inferred
APA, Harvard, Vancouver, ISO, and other styles
6

Mandlekar, Anup Shrikant. "An Application Framework for a Power-Aware Processor Architecture." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34484.

Full text
Abstract:
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency, was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software applications to test the architecture performance.
APA, Harvard, Vancouver, ISO, and other styles
7

Cortes, Christoffer, and Adam Krauser. "Android : Resource Consumption in Native and Web Applications." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4681.

Full text
Abstract:
There is an ongoing debate by people in the industry whether to make native or web applications. These discussions mostly surround issues about development costs, user experience and capabilities. Another aspect of this debate is the fact that mobile devices have varying hardware specifications which is another factor to consider when making this decision. What we want to shed some light on is how performance is affected on the device when using these two different approaches of application development. The use of CPU/RAM and Energy is our primary concern and in our experiment we measure these
APA, Harvard, Vancouver, ISO, and other styles
8

Mugisha, Dieudonne Manzi. "Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime." DigitalCommons@USU, 2015. https://digitalcommons.usu.edu/etd/4550.

Full text
Abstract:
Near-Threshold Computing embodies an intriguing choice for mobile processors due to the promise of superior energy efficiency, extending the battery life of these devices while reducing the peak power draw. However, process, voltage, and temperature variations cause a significantly high failure rate of Level One cache cells in the near-threshold regime a stark contrast to designs in the super-threshold regime, where fault sites are rare. This thesis work shows that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. In addition, popular mobile benchm
APA, Harvard, Vancouver, ISO, and other styles
9

Mahato, Prabir. "Study and development of resistive memories for flexible electronic applications." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI134.

Full text
Abstract:
L’avènement de l’électronique flexible a entraîné des recherches rapides sur des capteurs, des dispositifs bio-implantables et portables pour l’évaluation de maladies telles que l’épilepsie, la maladie de Parkinson et les crises cardiaques. Les dispositifs de mémoire sont des composants majeurs dans tous les circuits électroniques, uniquement secondaires aux transistors, par conséquent de nombreux efforts de recherche sont consacrés au développement de dispositifs de mémoire flexibles. Les mémoires à accès aléatoire à pont conducteur (CBRAM) basées sur la création / dissolution d'un filament m
APA, Harvard, Vancouver, ISO, and other styles
10

Ly, Aliou. "Développement d’un oscillateur paramétrique optique continu intense et à faible bruit pour des applications aux communications quantiques." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS528/document.

Full text
Abstract:
La portée des communications quantiques est limitée à quelques dizaines de km en raison de l’atténuation dans les fibres. Les répéteurs quantiques (relais quantiques synchronisés par des mémoires quantiques photoniques) furent introduits afin d’accroître ces distances. Or, pour le moment, les mémoires les plus performantes fonctionnent à des longueurs d’onde n’appartenant pas à la bande C télécom. Afin de profiter de ces mémoires, l’utilisation d’interfaces quantiques (milieu non linéaire quadratique) fut proposée comme alternative. En ajoutant ainsi par somme de fréquences un photon de pompe
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Memory and power applications"

1

Os, H. W. van. The power of memory. De Prom, 1999.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Weiss, Donald H. Increasing your memory power. American Management Association, 1986.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Cliff, Kellett Michael, ed. High-intensity memory power. Sterling, 1986.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Bayne, Stephen B., and Bejoy N. Pushpakaran, eds. Power Semiconductor Technology in Pulsed Power Applications. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-80252-2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Semiconductor, National. Memory applications handbook. National Semiconductor, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Ken, Harsha, and Ober Scot 1946-, eds. PC power: Microcomputer applications. Glencoe/McGraw-Hill, 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Esposito, Anthony. Fluid power with applications. 3rd ed. Regents/Prentice Hall, 1994.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Esposito, Anthony. Fluid power with applications. 4th ed. Prentice Hall, 1997.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Esposito, Anthony. Fluid power with applications. 7th ed. Pearson Prentice Hall, 2009.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Future Transportation Technology Conference and Exposition (1987 Seattle, Wash.). Smart power: Automotive applications. Society of Automotive Engineers, 1987.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Memory and power applications"

1

Tarasov, Vasily E. "Economic models with power-law memory." In Applications in Engineering, Life and Social Sciences, Part B, edited by Dumitru Bǎleanu and António Mendes Lopes. De Gruyter, 2019. http://dx.doi.org/10.1515/9783110571929-001.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Edelman, Mark. "Dynamics of nonlinear systems with power-law memory." In Applications in Physics, Part A, edited by Vasily E. Tarasov. De Gruyter, 2019. http://dx.doi.org/10.1515/9783110571707-005.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Corcuera, José Manuel. "Power Variation Analysis of Some Integral Long-Memory Processes." In Stochastic Analysis and Applications. Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-70847-6_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Prodromakis, Themis. "Harnessing the Power of the Brain with Memory-resitors." In Circuits and Systems for Biomedical Applications. River Publishers, 2022. http://dx.doi.org/10.1201/9781003337546-3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Qiu, Yeliang, Congfeng Jiang, Tiantian Fan, et al. "Power Characterization of Memory Intensive Applications: Analysis and Implications." In Benchmarking, Measuring, and Optimizing. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32813-9_16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Choi, Hong Jun, Dong Oh Son, and Cheol Hong Kim. "Memory Contention Aware Power Management for High Performance GPUs." In Parallel and Distributed Computing, Applications and Technologies. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5907-1_23.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Cheng, Yao, Chang Xu, Daisuke Mashima, Vrizlynn L. L. Thing, and Yongdong Wu. "PowerLSTM: Power Demand Forecasting Using Long Short-Term Memory Neural Network." In Advanced Data Mining and Applications. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69179-4_51.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Yoo, Hoi Jun, and Donghyun Kim. "Embedded Memory Architecture for Low-Power Application Processor." In Integrated Circuits and Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-88497-4_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Song, Yong-Ha, and Jun-Bo Yoon. "Micro and Nanoelectromechanical Contact Switches for Logic, Memory, and Power Applications." In Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting. Springer Netherlands, 2015. http://dx.doi.org/10.1007/978-94-017-9990-4_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

El-Atab, Nazek, Ali K. Okyay, and Ammar Nayfeh. "Two-nanometer Laser Synthesized Si-Nanoparticles for Low Power Memory Applications." In 3D Stacked Chips. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-20481-9_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Memory and power applications"

1

Phan, Ha-Vu, Tan-Hung Pham, Khang B. Tran, Quoc-Thang Phan, Quoc Dung Phan, and Yuan-Kang Wu. "Modified Quantum Long-Short Term Memory with Variational Quantum Circuits for PV Power Forecasting." In 2025 IEEE Industry Applications Society Annual Meeting (IAS). IEEE, 2025. https://doi.org/10.1109/ias62731.2025.11061559.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Swami, Yashu, and T. Senthil Vadivel. "16 Bit Memory and Power Efficient Truncated Booth Multiplier For High Speed Applications/Operations." In 2025 6th International Conference on Mobile Computing and Sustainable Informatics (ICMCSI). IEEE, 2025. https://doi.org/10.1109/icmcsi64620.2025.10883607.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Dubey, Sagar, Dan Oh, Sam Khalili, et al. "Power Integrity Design of a 56Gb/s Si-Photonic Optical Link for Memory Applications." In 2025 IEEE 75th Electronic Components and Technology Conference (ECTC). IEEE, 2025. https://doi.org/10.1109/ectc51687.2025.00121.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Chen, Zhiyan, and Libo Dong. "Enhanced Dynamic Interactive Multi-View Memory Network for Utterance-Level Sentiment Recognition." In 2025 IEEE 5th International Conference on Power, Electronics and Computer Applications (ICPECA). IEEE, 2025. https://doi.org/10.1109/icpeca63937.2025.10928284.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Toka, Erkin Atay, Baris Kuseyri, and Firuzi Keyvan. "Power Factor Enhancement with Variable Flux Memory Motor for Heating, Ventilation, and Air Conditioning Applications." In 2025 IEEE International Electric Machines & Drives Conference (IEMDC). IEEE, 2025. https://doi.org/10.1109/iemdc60492.2025.11061076.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Phan, Ha-Vu, Quoc-Thang Phan, Yuan-Kang Wu, and Quoc Dung Phan. "Hybrid Long-Short Term Memory with Variational Quantum Eigensolver for Photovoltaic Power Forecasting: A Novel Approach." In 2025 IEEE Industry Applications Society Annual Meeting (IAS). IEEE, 2025. https://doi.org/10.1109/ias62731.2025.11061533.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Zhen, Hongyue, Ziming Lin, Ligang Zhao, Junbo Zhang, Baorong Zhou, and Qinxiong Huang. "Application and Challenges of In-Memory Computing in Power System Simulation." In 2024 3rd International Conference on Energy and Electrical Power Systems (ICEEPS). IEEE, 2024. http://dx.doi.org/10.1109/iceeps62542.2024.10693073.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Roizin, Yakov, Evgeny Pikhay, Vladislav Dayan, and Alexey Heiman. "High Density MTP Logic NVM for Power Management Applications." In 2009 IEEE International Memory Workshop (IMW). IEEE, 2009. http://dx.doi.org/10.1109/imw.2009.5090593.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Kouznetsov, Igor, Krishnaswamy Ramkumar, Venkatraman Prabhakar, et al. "40 nm Ultralow-Power Charge-Trap Embedded NVM Technology for IoT Applications." In 2018 IEEE International Memory Workshop (IMW). IEEE, 2018. http://dx.doi.org/10.1109/imw.2018.8388777.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Zhu, Zongwei, Xi Li, Chao Wang, and Xuehai Zhou. "Memory power optimization on different memory address mapping schemas." In 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). IEEE, 2014. http://dx.doi.org/10.1109/rtcsa.2014.6910545.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "Memory and power applications"

1

Pasupuleti, Murali Krishna. Neuromorphic Nanotech: 2D Materials for Energy-Efficient Edge Computing. National Education Services, 2025. https://doi.org/10.62311/nesx/rr325.

Full text
Abstract:
Abstract The demand for energy-efficient, real-time computing is driving the evolution of neuromorphic computing and edge AI systems. Traditional silicon-based processors struggle with power inefficiencies, memory bottlenecks, and scalability limitations, making them unsuitable for next-generation low-power AI applications. This research report explores how 2D materials, such as graphene, transition metal dichalcogenides (TMDs), black phosphorus, and MXenes, are enabling the development of neuromorphic architectures that mimic biological neural networks for high-speed, ultra-low-power computat
APA, Harvard, Vancouver, ISO, and other styles
2

Pasupuleti, Murali Krishna. Neural Computation and Learning Theory: Expressivity, Dynamics, and Biologically Inspired AI. National Education Services, 2025. https://doi.org/10.62311/nesx/rriv425.

Full text
Abstract:
Abstract: Neural computation and learning theory provide the foundational principles for understanding how artificial and biological neural networks encode, process, and learn from data. This research explores expressivity, computational dynamics, and biologically inspired AI, focusing on theoretical expressivity limits, infinite-width neural networks, recurrent and spiking neural networks, attractor models, and synaptic plasticity. The study investigates mathematical models of function approximation, kernel methods, dynamical systems, and stability properties to assess the generalization capa
APA, Harvard, Vancouver, ISO, and other styles
3

Musmanno, Joseph F., Joseph W. Manke, and Jon W. Harris. Processor-in-Memory Applications Assessment. Defense Technical Information Center, 2000. http://dx.doi.org/10.21236/ada386682.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Agarwal, Anant, and Anoop Gupta. Memory-Reference Characteristics of Multiprocessor Applications under MACH. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada207318.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Schindewolf, M., B. Bihari, J. Gyllenhaal, M. Schulz, A. Wang, and W. Karl. What Scientific Applications can Benefit from Hardware Transactional Memory? Office of Scientific and Technical Information (OSTI), 2012. http://dx.doi.org/10.2172/1044233.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Bochat, W. M. Atomic Bomb: Memory and its Power on Japanese Pacifism. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada526120.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Levy, Scott N., Patrick G. Bridges, Kurt Brian Ferreira, Aidan Patrick Thompson, and Christian Robert Trott. An examination of content similarity within the memory of HPC applications. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1088105.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Merritt, Alexander M., and Kevin Thomas Tauke Pedretti. LDRD final report : managing shared memory data distribution in hybrid HPC applications. Office of Scientific and Technical Information (OSTI), 2010. http://dx.doi.org/10.2172/1007320.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Biryukov, A., D. Dinu, D. Khovratovich, and S. Josefsson. Argon2 Memory-Hard Function for Password Hashing and Proof-of-Work Applications. RFC Editor, 2021. http://dx.doi.org/10.17487/rfc9106.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Lindemuth, I. R., R. E. Reinovsky, and C. M. Fowler. Megagauss technology and pulsed power applications. Office of Scientific and Technical Information (OSTI), 1996. http://dx.doi.org/10.2172/378770.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Memory and power applications' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography