Relevant bibliographies by topics / Memory block

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Memory block'

Author: Grafiati
Published: 4 June 2021
Last updated: 9 February 2022

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Journal articles on the topic "Memory block"

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Chae, Suk-Joo, Ronnie Mativenga, Joon-Young Paik, Muhammad Attique, and Tae-Sun Chung. "DSFTL: An Efficient FTL for Flash Memory Based Storage Systems." Electronics 9, no. 1 (January 12, 2020): 145. http://dx.doi.org/10.3390/electronics9010145.

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Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), a software called FTL (Flash Translation Layer) was presented. The function of FTL is to make flash memory device appear as a block device to its host. However, due to the erase before write features of flash memory, flash blocks need to be constantly availed through the garbage collection (GC) of invalid pages, which incurs high-priced overhead. In the previous hybrid mapping schemes, there are three problems that cause GC overhead. First, operation of partial merge causes more page copies than operation of switch merge. However, many authors just concentrate on reducing operation of full merge. Second, the availability between a data block and a log block makes the space availability of the log block lower, and it also generates a very high-priced operation of full merge. Third, the space availability of the data block is low because the data block, which has many free pages, is merged. Therefore, we propose a new FTL named DSFTL (Dynamic Setting for FTL). In this FTL, we use many SW (sequential write) log blocks to increase operation of switch merge and to decrease operation of partial merge. In addition, DSFTL dynamically handles the data blocks and log blocks to reduce the operations of erase and the high-priced operation of full merge. Additionally, our scheme prevents the data block with many free pages from being merged to increase the space availability of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) reduces the count of erase and increases the operation of switch merge. As a result, DSFTL decreases the garbage collection overhead.
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Prihozhy, A. A., and O. N. Karasik. "HETEROGENIOUS BLOCKED ALL-PAIRS SHORTEST PATHS ALGORITHM." «System analysis and applied information science», no. 3 (November 2, 2017): 68–75. http://dx.doi.org/10.21122/2309-4923-2017-3-68-75.

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The problem of finding the shortest paths between all pairs of vertices in a weighted directed graph is considered. The algorithms of Dijkstra and Floyd-Warshall, homogeneous block and parallel algorithms and other algorithms of solving this problem are known. A new heterogeneous block algorithm is proposed which considers various types of blocks and takes into account the shared hierarchical memory organization and multi-core processors for calculating each type of block. The proposed heterogeneous block computing algorithms are compared with the generally accepted homogeneous universal block calculation algorithm at theoretical and experimental levels. The main emphasis is on using the nature of the heterogeneity, the interaction of blocks during computation and the variation in block size, the size of the block matrix and the total number of blocks in order to identify the possibility of reducing the amount of computation performed during the calculation of the block, reducing the activity of the processor’s cache memory and determining the influence of the calculation time of each block type on the total execution time of the heterogeneous block algorithm. A recurrent resynchronized algorithm for calculating the diagonal block (D0) is proposed, which improves the use of the processor’s cache and reduces the number of iterations up to 3 times that are necessary to calculate the diagonal block, which implies the acceleration in calculating the diagonal block up to 60%. For more efficient work with the cache memory, variants of permutation of the basic loops k-i-j in the algorithms of calculating the blocks of the cross (C1 and C2) and the updated blocks (U3) are proposed. These permutations in combination with the proposed algorithm for calculating the diagonal block reduce the total runtime of the heterogeneous block algorithm to 13% on average against the homogeneous block algorithm.
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Lee, Myungsub. "A Block Classification Method with Monitor and Restriction in NAND Flash memory." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 209–15. http://dx.doi.org/10.17762/turcomat.v12i5.877.

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In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.
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Перминов, Н. С., Д. Ю. Таранкова, and С. А. Моисеев. "Спектрально улучшенная квантовая память на контролируемой частотной гребенке." Журнал технической физики 127, no. 8 (2019): 313. http://dx.doi.org/10.21883/os.2019.08.48048.202-18.

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We propose a scheme of a universal block of broadband quantum memory consisting of three ring microresonators forming a controllable frequency comb and interacting with each other and with a common waveguide. We find the optimal parameters of the microresonators showing the possibility of highly efficient storage of light fields on this memory block and we demonstrate the procedure for gluing several memory blocks for increasing spectral range of the composite quantum memory while maintaining high efficiency.
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Chang, Meng-Fan, Mary Jane Irwin, and Robert Michael Owens. "Power-Area Trade-Offs in Divided Word Line Memory Arrays." Journal of Circuits, Systems and Computers 07, no. 01 (February 1997): 49–67. http://dx.doi.org/10.1142/s021812669700005x.

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Since on-chip caches account for a significant portion of the power budget of modern microprocessors, low power caches are needed in microprocessors destined for portable electronic applications. A significant portion of the power consumption of caches comes from accessing the cache memory array and most of the power consumption of the memory array comes from driving the bit line pairs (i.e., the column current). Various memory array architectures have been proposed to improve the word line delay and the column current. For example, in a divided word line memory array memory cells in each row are organized into blocks. Only the memory cells which are in the activated block have their bit line pairs driven, thus both improving the speed (by decreasing the word line delay) and lowering the power consumption (by decreasing the column current). In this paper we analyze the power-area tradeoffs of divided word line memories with different size blocks. We compare the area and power consumption of 16 Kbit and 64 Kbit memory arrays with 2, 4, 8, and 16 memory cells per block. Our experiments show that a divided word line memory array can lower the power consumption by 50% to 90% over a nondivided word line memory array. However, they consume more area; the area of a divided word line memory array can be 15% to 27% larger than the area of a comparable nondivided word line array. Our experiments also showed that divided word line memory arrays with two or four memory cells in a block have better power-area product than those with more than four cells per block.
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SEO, EUISEONG, SEUNGRYOUL MAENG, DONGHYOUK LIM, and JOONWON LEE. "EXPLOITING TEMPORAL LOCALITY FOR ENERGY EFFICIENT MEMORY MANAGEMENT." Journal of Circuits, Systems and Computers 17, no. 05 (October 2008): 929–41. http://dx.doi.org/10.1142/s021812660800468x.

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Memory is becoming one of the major power consumers in computing systems. Therefore, energy efficient memory management is essential. Modern memory systems employ sleep states for energy saving. To utilize this feature, existing research activities have concentrated on increasing spatial locality to deactivate as many blocks as possible. However, they did not count the unexpected activation of memory blocks due to cache eviction of deactivated tasks. In this paper, we suggest a software-based power state management scheme for memory, which exploits temporal locality to relieve the energy loss from the unexpected activation of memory blocks from cache eviction. The suggested scheme SW-NAP makes a memory block remain deactivated during a certain tick, which has no cache miss over the block. The evaluation shows that SW-NAP is 50% better than PAVM, which is an existing software scheme, and worse than PMU, which is another approach based on the specialized hardware by 20%. We also suggest task scheduling policies that increase the effectiveness of SW-NAP and they saved up to 7% additional energy.
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Jaja, J. F., and Kwan Woo Ryu. "The block distributed memory model." IEEE Transactions on Parallel and Distributed Systems 7, no. 8 (1996): 830–40. http://dx.doi.org/10.1109/71.532114.

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Yang, Yin, Wen Yi Li, and Kai Wang. "A Read-Write Optimization Scheme for Flash Memory Storage Systems." Applied Mechanics and Materials 687-691 (November 2014): 2096–99. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2096.

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In this paper, we propose a novel and efficient read-write optimization scheme for flash memory storage systems, we have named RWF: Read-Write FTL. In the proposed scheme, we effectively connect Logical Sector Number, Logical Block Number, Logical Page Number, Physical Page Number and Physical Block Number. RWF through uniting log blocks and physical blocks, all blocks can be used for servicing update requests. The invalid blocks could be reclaimed properly and intensively, it can avoid merging log blocks with physical blocks. At last, through the simulation test on RWF and the comparison with other schemes, which demonstrate the RWF can effectively solve data storage problems, and it greatly reduces erase count of flash devices and efficiency improves the performance of flash memory storage systems.
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Edwards, Nicholas Jain, David Tonny Brain, Stephen Carinna Joly, and Mariana Karry Masucato. "Hadoop distributed file system mechanism for processing of large datasets across computers cluster using programming techniques." International research journal of management, IT and social sciences 6, no. 6 (September 7, 2019): 1–16. http://dx.doi.org/10.21744/irjmis.v6n6.739.

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In this paper, we have proved that the HDFS I/O operations performance is getting increased by integrating the set associativity in the cache design and changing the pipeline topology using fully connected digraph network topology. In read operation, since there is huge number of locations (words) at cache compared to direct mapping the chances of miss ratio is very low, hence reducing the swapping of the data between main memory and cache memory. This is increasing the memory I/O operations performance. In Write operation instead of using the sequential pipeline we need to construct the fully connected graph using the data blocks listed from the NameNode metadata. In sequential pipeline, the data is getting copied to source node in the pipeline. Source node will copy the data to next data block in the pipeline. The same copy process will continue until the last data block in the pipeline. The acknowledgment process has to follow the same process from last block to source block. The time required to transfer the data to all the data blocks in the pipeline and the acknowledgment process is almost 2n times to data copy time from one data block to another data block (if the replication factor is n).
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Chung, Tae-Sun, Dong-Joo Park, and Jongik Kim. "An Efficient Flash Translation Layer for Large Block NAND Flash Devices." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550138. http://dx.doi.org/10.1142/s0218126615501388.

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Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.
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Dissertations / Theses on the topic "Memory block"

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Zhu, Shaojuan. "Associative memory as a Bayesian building block /." Full text open access at:, 2008. http://content.ohsu.edu/u?/etd,655.

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Peters, Nicholas Rayfield. "Block structures, multi-layering and memory : composition portfolio : commentary." Thesis, Brunel University, 2010. http://bura.brunel.ac.uk/handle/2438/4603.

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This commentary accompanies a portfolio of nine compositions written between October 2006 and June 2009. This commentary traces the development of a range of compositional ideas throughout the portfolio. These revolve around the creation of multilayered textures where all the material and all subtle variations thereof are audible, leading to an investigation of rhythmical block durations and the role of memory. The context in which these ideas arose is provided through discussion of specific existing work that closely relates to the portfolio, in particular by John Cage, Morton Feldman, György Ligeti and Giacinto Scelsi.
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Chi, Hsiang. "Flash memory boot block architecture for safe firmware updates." FIU Digital Commons, 1995. http://digitalcommons.fiu.edu/etd/2160.

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The most significant risk of updating embedded system code is the possible loss of system firmware during the update process. If the firmware is lost, the system will cease to operate, which can be very costly to the end user. This thesis is concerned with exploring alternate architectures which exploit the integration of flash memory technology in order to overcome this problem. Three design models and associated software techniques will be presented. These design models are described in detail in terms of the strategies they employ in order to prevent system lockup and the loss of firmware. The most important objective, which is addressed in the third model, is to ensure that the system can continue to process interrupts during the update. In addition, a portion of this research was aimed at providing the capability to perform updates remotely, and at maximizing system code memory space and available system RAM.
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Jarque, Al V. "Recursive block-by-block integral equation solution for transient dynamic analysis with memory-type elements." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2001. http://handle.dtic.mil/100.2/ADA390953.

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Malard, Joël. "Block solvers for dense linear systems on local memory multiprocessors." Thesis, McGill University, 1992. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=39760.

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The solution of dense systems of linear equations is at the heart of numerical computations. Such systems are best solved by direct methods based on one of the LU, Cholesky or QR factorizations. Typical parallel algorithms for the LU, Cholesky and QR factorizations of dense matrices stored on a message passing multicomputer hide latency by overlapping communication with arithmetic and by restricting communications to occur along a subring of processors. We show empirically that exploiting the full connectivity of the underlying multicomputer is essential for designing communication efficient algorithms.
A specialized total exchange algorithm is presented for improving communication load balance during an LU factorization with pivoting. Threshold pivoting is proposed as a way of significantly reducing processor idle time due to row exchanges during an LU factorization with pivoting.
The columns of the Q factor computed by modified Gram-Schmidt QR factorization algorithms can be far from orthogonal. Parallelizations of the algorithm proposed by Bjorck and Paige for safely using the computed Q are also presented.
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Lianekhammy, Joann. "INVESTIGATING AGE-RELATED INHIBITORY DEFICITS IN SPATIAL WORKING MEMORY." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/402.

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Age-related inhibitory effects were investigated during spatial memory performance. In Experiment 1, 15 young (M = 20 years) and 16 old adults (M = 70 years) completed two spatial tasks (i.e., Block Suppression Test, Corsi Block Tapping Test) that differed in need for inhibitory processing. Accuracy differences within each task revealed age-related differences in spatial working memory and between task differences revealed that older adults had difficulty ignoring irrelevant items. Experiment 2 (10 young, 10 old adults) examined whether the distractibility of irrelevant items in the inhibition task (i.e. BST) accounted for the age-related inhibitory effects. Findings were largely consistent with the initial experiment indicating that inhibitory function was affected by adult aging.
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Gupta, Sandeep K. S. "Synthesizing communication-efficient distributed memory parallel programs for block recursive algorithms /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487861796820607.

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Kirschner, Johannes [Verfasser], and Marcus [Gutachter] Halik. "Block Copolymer Hybrid Dielectrics in Organic Memory Transistors / Johannes Kirschner ; Gutachter: Marcus Halik." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2017. http://d-nb.info/1152079026/34.

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Chandrakar, Shant. "Memory Architecture Template for Fast Block Matching Algorithms on Field Programmable Gate Arrays." DigitalCommons@USU, 2009. https://digitalcommons.usu.edu/etd/495.

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Fast Block Matching (FBM) algorithms for video compression are well suited for acceleration using parallel data-path architectures on Field Programmable Gate Arrays (FPGAs). However, designing an efficient on-chip memory subsystem to provide the required throughput to this parallel data-path architecture is a complex problem. This thesis presents a memory architecture template that can be parameterized for a given FBM algorithm, number of parallel Processing Elements (PEs), and block size. The template can be parameterized with well known exploration techniques to design efficient on-chip memory subsystems. The memory subsystems are derived for two existing FBM algorithms and are implemented on a Xilinx Virtex 4 family of FPGAs. Results show that the derived memory subsystem in the best case supports up to 27 more parallel PEs than the three existing subsystems and processes integer pixels in a 1080p video sequence up to a rate of 73 frames per second. The speculative execution of an FBM algorithm for the same number of PEs increases the number of frames processed per second by 49%.
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JANARTHANAN, ARUN. "LOW POWER CONTROLLER MAPPING BY DISABLING THE EMBEDDED MEMORY BLOCKS IN FPGAs." University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1178109590.

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Books on the topic "Memory block"

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Wilton, Steven J. E. Block transfers in a shared memory multiprocessor. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1993.

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Geschiere, J. P. Structured parallelization of a multi-block Navier-Stokes solver targeting distributed memory platforms. Amsterdam: National Aerospace Laboratory, 1994.

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The playful Middle Ages: Meanings of play and plays of meaning, essays in memory of Elaine C. Block. Turnhout: Brepols, 2010.

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Kidd, Parris M. Phosphatidylserine (PS): Number-one brain booster : the nutrient building block that accelerates all brain functions and counters Alzheimer's. New Canaan, Conn: Keats Pub., 1998.

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Ndongo-Bidyogo, Donato. Shadows of your black memory. Chicago: Swan Isle Press, 2007.

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Hord, Fred L. Reconstructing memory: Black literary criticism. Chicago: Third World Press, 1991.

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Embodying Black experience: Stillness, critical memory, and the Black body. Ann Arbor: University of Michigan Press, 2010.

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Black Arab as a figure of memory. Skopje: Macedonian Academy of Sciences and Arts, 2009.

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Grillo, Evelio. Black Cuban, Black American: A memoir. Houston, Tex: Arte Público Press, 2000.

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The queer limit of Black memory: Black lesbian literature and irresolution. Columbus: Ohio State University Press, 2013.

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Book chapters on the topic "Memory block"

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Chung, Tae-Sun, Dong-Joo Park, Yeonseung Ryu, and Sugwon Hong. "LSTAFF: System Software for Large Block Flash Memory." In Lecture Notes in Computer Science, 704–12. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/978-3-540-30585-9_78.

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Levin, Jed, and Patrice L. Jeppson. "Archaeology as a Building Block for Popular Memory." In Transforming Heritage Practice in the 21st Century, 197–211. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-14327-5_15.

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Canu, Joël, and Hubert Ritzdorf. "Adaptive, Block-Structured Multigrid on Local Memory Machines." In Notes on Numerical Fluid Mechanics (NNFM), 84–98. Wiesbaden: Vieweg+Teubner Verlag, 1994. http://dx.doi.org/10.1007/978-3-663-14246-1_6.

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Ahn, S. k., P. Deshmukh, and R. M. Kasi. "Exploiting Architecture and Composition of Side-Chain Liquid Crystalline Polymers for Shape Memory Applications." In Non-Conventional Functional Block Copolymers, 39–51. Washington, DC: American Chemical Society, 2011. http://dx.doi.org/10.1021/bk-2011-1066.ch004.

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Larsson, Fredrik, Paul Pettersson, and Wang Yi. "On Memory-Block Traversal Problems in Model-Checking Timed Systems." In Tools and Algorithms for the Construction and Analysis of Systems, 127–41. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-46419-0_10.

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Kwon, Jin Baek. "On Bypassing Page Cache for Block Devices on Storage Class Memory." In Lecture Notes in Electrical Engineering, 361–66. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-5041-1_59.

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Pfähler, Jörg, Gidon Ernst, Gerhard Schellhorn, Dominik Haneberg, and Wolfgang Reif. "Formal Specification of an Erase Block Management Layer for Flash Memory." In Hardware and Software: Verification and Testing, 214–29. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03077-7_15.

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Knoblauch, Andreas, and Günther Palm. "Bidirectional Associative Memory with Block Coding: A Comparison of Iterative Retrieval Methods." In Artificial Neural Networks and Machine Learning – ICANN 2019: Theoretical Neural Computation, 3–19. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30487-4_1.

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Vadnala, Praveen Kumar. "Time-Memory Trade-Offs for Side-Channel Resistant Implementations of Block Ciphers." In Topics in Cryptology – CT-RSA 2017, 115–30. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-52153-4_7.

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Karlsson, Lars, and Bo Kågström. "Efficient Reduction from Block Hessenberg Form to Hessenberg Form Using Shared Memory." In Applied Parallel and Scientific Computing, 258–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28145-7_26.

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Conference papers on the topic "Memory block"

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Blelloch, Guy E., Phillip B. Gibbons, and S. Harsha Vardhan. "Combinable memory-block transactions." In the twentieth annual symposium. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1378533.1378537.

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Kramer, Gerhard. "Networks with in-block memory." In 2012 IEEE Information Theory Workshop (ITW 2012). IEEE, 2012. http://dx.doi.org/10.1109/itw.2012.6404689.

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Aggarwal, Alok, Ashok K. Chandra, and Marc Snir. "Hierarchical memory with block transfer." In 28th Annual Symposium on Foundations of Computer Science. IEEE, 1987. http://dx.doi.org/10.1109/sfcs.1987.31.

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Yanan Cao, Long Chen, and Zhao Zhang. "Flexible memory: A novel main memory architecture with block-level memory compression." In 2015 IEEE International Conference on Networking, Architecture and Storage (NAS). IEEE, 2015. http://dx.doi.org/10.1109/nas.2015.7255237.

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Österlund, Erik, and Welf Löwe. "Block-free concurrent GC: stack scanning and copying." In ISMM '16: International Symposium on Memory Management. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2926697.2926701.

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Chen, Feng, Michael P. Mesnier, and Scott Hahn. "A protected block device for Persistent Memory." In 2014 30th Symposium on Mass Storage Systems and Technologies (MSST). IEEE, 2014. http://dx.doi.org/10.1109/msst.2014.6855541.

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Zimmermann, L., F. Boileau, L. Arnaud, and B. Desloges. "Experimetnal study of block line memory initialization." In International Magnetics Conference. IEEE, 1989. http://dx.doi.org/10.1109/intmag.1989.690379.

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Dominguez, David. "Block information and topology in memory networks." In COOPERATIVE BEHAVIOR IN NEURAL SYSTEMS: Ninth Granada Lectures. AIP, 2007. http://dx.doi.org/10.1063/1.2709592.

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Vorobyov, Kostyantyn, Julien Signoles, and Nikolai Kosmatov. "Shadow state encoding for efficient monitoring of block-level properties." In ISMM '17: International Symposium on Memory Management. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3092255.3092269.

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Yang, Renhua, Xiaoyong Xue, Yufeng Xie, and Yinyin Lin. "Adaptive Block level management for hybrid main memory." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021532.

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Reports on the topic "Memory block"

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Kim, Joohee, and Marios C. Papaefthymiou. Block-Based Multi-Period Refresh for Energy Efficient Dynamic Memory. Fort Belvoir, VA: Defense Technical Information Center, April 2002. http://dx.doi.org/10.21236/ada414244.

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Aikins, Deane. Using Propranolol to Block Memory Reconsolidation in Female Veterans with PTSD. Fort Belvoir, VA: Defense Technical Information Center, October 2013. http://dx.doi.org/10.21236/ada612332.

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Aikins, Deane. Using Propranolol to Block Memory Reconsolidation in Female Veterans with PTSD. Fort Belvoir, VA: Defense Technical Information Center, October 2010. http://dx.doi.org/10.21236/ada543119.

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Aikins, Deane. Using Propranolol to Block Memory Reconsolidation in Female Veterans with PTSD. Fort Belvoir, VA: Defense Technical Information Center, October 2012. http://dx.doi.org/10.21236/ada598741.

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Aikins, Deane. Using Propranolol to Block Memory Reconsolidation in Female Veterans with PTSD. Fort Belvoir, VA: Defense Technical Information Center, October 2011. http://dx.doi.org/10.21236/ada561958.

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Aikins, Deane. Using Propranolol to Block Memory Reconsolidation in Female Veterans with PTSD. Fort Belvoir, VA: Defense Technical Information Center, October 2014. http://dx.doi.org/10.21236/ada615056.

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Liu, Xin, Zaiwen Wen, and Yin Zhang. Limited Memory Block Krylov Subspace Optimization for Computing Dominant Singular Value Decompositions. Fort Belvoir, VA: Defense Technical Information Center, March 2012. http://dx.doi.org/10.21236/ada580501.

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Santhi, Nandakishore, and Gopinath Chennupati. Compute Node Models: Large-scale Amenable Block-Level Simulation for Memory Hierarchies and Pipelines. Office of Scientific and Technical Information (OSTI), February 2017. http://dx.doi.org/10.2172/1342832.

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Dubnicki, Cezary. The Effects of Block Size on the Performance of Coherent Caches in Shared-Memory Multiprocessors. Fort Belvoir, VA: Defense Technical Information Center, May 1993. http://dx.doi.org/10.21236/ada272838.

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Asea, Patrick K., and Michael J. Dueker. Non-Monotonic Long Memory Dynamics in Black-Market Exchange Rates. Federal Reserve Bank of St. Louis, 1995. http://dx.doi.org/10.20955/wp.1995.003.

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