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Relevant bibliographies by topics / Memory fault

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Academic literature on the topic 'Memory fault'

Author: Grafiati

Published: 3 June 2025

Last updated: 23 June 2025

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Journal articles on the topic "Memory fault"

1

Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (2022): 971. http://dx.doi.org/10.3390/mi13060971.

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

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Park, Pangun, Piergiuseppe Di Marco, Hyejeon Shin, and Junseong Bang. "Fault Detection and Diagnosis Using Combined Autoencoder and Long Short-Term Memory Network." Sensors 19, no. 21 (2019): 4612. http://dx.doi.org/10.3390/s19214612.

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Fault detection and diagnosis is one of the most critical components of preventing accidents and ensuring the system safety of industrial processes. In this paper, we propose an integrated learning approach for jointly achieving fault detection and fault diagnosis of rare events in multivariate time series data. The proposed approach combines an autoencoder to detect a rare fault event and a long short-term memory (LSTM) network to classify different types of faults. The autoencoder is trained with offline normal data, which is then used as the anomaly detection. The predicted faulty data, captured by autoencoder, are put into the LSTM network to identify the types of faults. It basically combines the strong low-dimensional nonlinear representations of the autoencoder for the rare event detection and the strong time series learning ability of LSTM for the fault diagnosis. The proposed approach is compared with a deep convolutional neural network approach for fault detection and identification on the Tennessee Eastman process. Experimental results show that the combined approach accurately detects deviations from normal behaviour and identifies the types of faults within the useful time.

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Mrozek, Ireneusz, and Vyacheslav N. Yarmolik. "Linked Coupling Faults Detection by Multirun March Tests." Applied Sciences 14, no. 6 (2024): 2501. http://dx.doi.org/10.3390/app14062501.

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This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in relation to each other. The memory march test and applied address sequence and background determine the scenario for implementing the roles of memory faulty cells. The necessary and sufficient conditions for detecting linked coupling faults are given based on a new formal model. Formally, the undetectable linked coupling faults are defined, and the conditions for their detection are formulated using multirun memory march tests. The experimental investigation confirmed the validity of the proposed formulated statements. Based on the example of a linked coupling fault, this study demonstrates the fulfillment of the necessary and sufficient conditions for its detection using a single march test. As demonstrated in this article, employing the approach proposed by the authors, a two-pass march C test, for instance, enables the attainment of 55.42% fault coverage for linked coupling faults, inclusive of undetectable faults identified by the single-pass march test.

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Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.

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This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distributed RAM mode of the memory block, the TPG based on FSM is designed to provide March C-testing patterns. Besides, the comparator-based output response analyzer (ORA) and the cascaded ORA scan chain are used to locate the faulty CLB and propagate the comparison output in every row. Finally, fault-injection experiment results verify its ability to detect and diagnose multiple faulty CLBs in faulty FPGAs.

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Swamy S., Kendaganna, Rajasree P. M., Anand M. Sharma, and Jnanaprakash J. Naik. "A Review Paper on Memory Fault Models and its Algorithms." International Journal of Electrical Engineering and Computer Science 6 (October 7, 2024): 143–51. http://dx.doi.org/10.37394/232027.2024.6.17.

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The significance of testing semiconductor memories has grown significantly in the semiconductor industry due to the increased density of modern memory chips. This paper aims to investigate and analyze different types of functional faults present in today's memory technology. These faults include stuck-at faults, transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on the importance of zero-one, checkerboard, and March pattern tests, which are widely employed to assess functional memory defects at different levels, such as the chip level, array level, and board level. Furthermore, the study provides an in-depth exploration of various test algorithms and thoroughly examines their fault coverage capabilities. Overall, this review paper provides valuable insights into the challenges posed by the dense nature of modern memory chips and offers a comprehensive analysis of functional faults in memory technology. By emphasizing the importance of testing and presenting a detailed exploration of fault detection methods and test algorithms, this study contributes to the advancement of reliable and high-performance memory devices in the electronic industry suggesting that MARCH algorithms outperform others when considering factors like fault coverage, power efficiency, area optimization, and time complexity parameters, making them the preferable choice for reliable and high-performance memory devices in the electronic industry.

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Lakshmi A, Sowjanya, and Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.

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Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while minimizing useless and forced checkpoints. Long short-term memory (LSTM) based deep learning algorithm is used in our approach to predict fault occurrences and strategically place checkpoints. The proposed method also in turn improve system reliability and performance. Experimental results demonstrate the effectiveness of proposed CIC-FTM in IoT environment by minimizing the practicable operating time for checkpointing and back propagation, compared to traditional fault-tolerance mechanisms.

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Sowjanya, Lakshmi A. Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785–96. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.

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Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while minimizing useless and forced checkpoints. Long short-term memory (LSTM) based deep learning algorithm is used in our approach to predict fault occurrences and strategically place checkpoints. The proposed method also in turn improve system reliability and performance. Experimental results demonstrate the effectiveness of proposed CIC-FTM in IoT environment by minimizing the practicable operating time for checkpointing and back propagation, compared to traditional fault-tolerance mechanisms.

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Vandris, Evstratios, and Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits." VLSI Design 4, no. 3 (1996): 217–29. http://dx.doi.org/10.1155/1996/34084.

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A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

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Lee, Jeong-Geun, Deok-Hwan Kim, and Jang Hyun Lee. "Proactive Fault Diagnosis of a Radiator: A Combination of Gaussian Mixture Model and LSTM Autoencoder." Sensors 23, no. 21 (2023): 8688. http://dx.doi.org/10.3390/s23218688.

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Radiator reliability is crucial in environments characterized by high temperatures and friction, where prompt interventions are often required to prevent system failures. This study introduces a proactive approach to radiator fault diagnosis, leveraging the integration of the Gaussian Mixture Model and Long-Short Term Memory autoencoders. Vibration signals from radiators were systematically collected through randomized durability vibration bench tests, resulting in four operating states—two normal, one unknown, and one faulty. Time-domain statistical features of these signals were extracted and subjected to Principal Component Analysis to facilitate efficient data interpretation. Subsequently, this study discusses the comparative effectiveness of the Gaussian Mixture Model and Long Short-Term Memory in fault detection. Gaussian Mixture Models are deployed for initial fault classification, leveraging their clustering capabilities, while Long-Short Term Memory autoencoders excel in capturing time-dependent sequences, facilitating advanced anomaly detection for previously unencountered faults. This alignment offers a potent and adaptable solution for radiator fault diagnosis, particularly in challenging high-temperature or high-friction environments. Consequently, the proposed methodology not only provides a robust framework for early-stage fault diagnosis but also effectively balances diagnostic capabilities during operation. Additionally, this study presents the foundation for advancing reliability life assessment in accelerated life testing, achieved through dynamic threshold adjustments using both the absolute log-likelihood distribution of the Gaussian Mixture Model and the reconstruction error distribution of the Long-Short Term Memory autoencoder model.

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Mrozek, Ireneusz. "Analysis of multibackground memory testing techniques." International Journal of Applied Mathematics and Computer Science 20, no. 1 (2010): 191–205. http://dx.doi.org/10.2478/v10006-010-0014-6.

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Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

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Dissertations / Theses on the topic "Memory fault"

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Koneru, Venkata Raja Ramchandar. "Fault Insertion and Fault Analysis of Neural Cache Memory." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1592171695469746.

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Izadi, Baback A. "Design of fault-tolerant distributed memory multiprocessors /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu148786754173319.

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Rink, Norman Alexander, and Jeronimo Castrillon. "Comprehensive Backend Support for Local Memory Fault Tolerance." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-215785.

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Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to transient faults. Applications can be protected against faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to program representations at abstraction levels higher than machine instructions are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, a large proportion of a program’s memory accesses are introduced by the compiler backend. This report presents a backend that protects these accesses against faults in the memory system. It is demonstrated that the presented backend can detect all single bit flips in memory that would be missed by an error detection scheme that operates on the LLVM intermediate representation of programs. The presented compiler backend is obtained by modifying the LLVM backend for the x86 architecture. On a subset of SPEC CINT2006 the runtime overhead incurred by the backend modifications amounts to 1.50x for the 32-bit processor architecture i386, and 1.13x for the 64-bit architecture x86_64. To achieve comprehensive detection of memory faults, the modified backend implements an adjusted calling convention that leaves library function calls transparent and intact.

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MARTIN, ROBERT ROHAN. "MULTI-LEVEL CELL FLASH MEMORY FAULT TESTING AND DIAGNOSIS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1120232606.

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Taleb, Mohammed Yacine. "Optimizing Distributed In-memory Storage Systems˸ Fault-tolerance, Performance, Energy Efficiency." Thesis, Rennes, École normale supérieure, 2018. http://www.theses.fr/2018ENSR0015/document.

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Les technologies émergentes, telles que les objets connectés et les réseaux sociaux sont en train de changer notre manière d’interagir avec autrui. De par leur large adoption, ces technologies génèrent de plus en plus de données. Alors que la gestion de larges volumes de données fut l’un des sujets majeurs de la dernière décennie, un nouveau défi est apparu récemment : comment tirer profit de données générées en temps réel. Avec la croissance des capacités de mémoires vives, plusieurs fournisseurs services, tel que Facebook, déploient des péta-octets de DRAM afin de garantir un temps d’accès rapide aux données. Néanmoins, les mémoires vives sont volatiles, et nécessitent souvent des mécanismes de tolérance aux pannes coûteux en termes de performance. Ceci crée des compromis entre la performance, la tolérance aux pannes et l’efficacité dans les systèmes de stockage basés sur les mémoires vives. Dans cette thèse, nous commençons, d’une part, par étudier ces compromis : nous identifions les facteurs principaux qui impactent la performance, l’efficacité et la tolérance aux pannes dans les systèmes de stockage en mémoire.Ensuite, nous concevons et implémentons un nouveau mécanisme de réplication basé sur l’accès à la mémoire distante (RDMA). Enfin, nous portons cette technique à un nouveau type de système de stockage : les systèmes de stockage pour streaming. Nous concevons et implémentons des mécanismes de réplication et de tolérance aux pannes efficaces et un impact minimal sur les performances sur le stockage pour streaming<br>Emerging technologies such as connected devices and social networking applications are shaping the way we live, work, and interact with each other. These technologies generate increasingly high volumes of data. Dealing with large volumes of data has been an important focus in the last decade, however, today the challenge has shifted from data volume to velocity: How to store, process, and extract value from data generated With the growing capacity of DRAM, service providers largely rely on DRAM-based storage systems to serve their workloads. Because DRAM is volatile, usually, distributed in-memory storage systems rely on expensive durability mechanisms to persist data.This creates trade-offs between performance, durability and efficiency in in-memory storage systems We first study these trade-offs by means of experimental study. We extract the main factors that impact performance and efficiency in in-memory storage systems. Then, we design and implement a new RDMA-based replication mechanism that greatly improves replication efficiency in in-memory storage systems. Finally, we leverage our techniques and apply them to stream storage systems. We design and implement high-performance replication mechanisms for stream storage, while guaranteeing linearizability and durability

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Meenakshi, Siddharthan Rathna Keerthi. "Fault Modeling and Analysis for FinFET SRAM Arrays." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1368014414.

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Butler, Bryan P. (Bryan Philip). "A fault-tolerant shared memory system architecture for a Byzantine resilient computer." Thesis, Massachusetts Institute of Technology, 1989. http://hdl.handle.net/1721.1/13360.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.<br>Includes bibliographical references (leaves 145-147).<br>by Bryan P. Butler.<br>M.S.

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Hulme, Charles A. "Testing and evaluation of the configurable fault tolerant processor (CFTP) for space-based application." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FHulme.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003.<br>Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.

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Blum, Daniel Ryan. "Hardened by design approaches for mitigating transient faults in memory-based systems." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Dissertations/Spring2007/d_blum_043007.pdf.

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Dhoke, Aditya Anil. "On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23890.

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Distributed Transactional Memory (DTM) is an emerging synchronization abstraction thatpromises to alleviate the scalability, programmability, and composability challenges of lock-based distributed synchronization. With DTM, programmers organize code that read/writeshared memory objects, both local and remote, as memory transactions. An underlying DTMframework guarantees atomicity, isolation, and consistency properties for those transactionsthrough speculative concurrency control. In DTM, restarting an aborted transaction from the beginning can degrade performance astransactional conflicts may have occurred in the later part of the transaction, wasting work.The partial abort method alleviates this difficulty by enabling a transaction to be rolled backto the point where objects in the transaction's read-set and write-set are still consistent.In this thesis, we present protocols for supporting partial aborts in QR-DTM, a fault-tolerant DTM that uses quorum protocols for distributed concurrency control in the presence offailures. We focus on two partial abort models: closed nesting, which allows transactions to be nested and inner transactions to be rolled back without rolling back outer transactions;and checkpointing, which allows the transaction state to be saved in checkpoints throughout execution and transactions to be rolled back to those checkpoints. We present protocols that support these partial abort models in QR-DTM, called QR-CN and QR-CHK. We implemented these protocols and conducted experimental studies using macro-benchmarks(e.g., distributed versions of STAMP benchmark), and micro-benchmarks (e.g., distributed data structures). Our studies reveal that QR-CN improves throughput by as much as 101% over flat nesting in specific cases, with an average improvement of 53%. We also develop QR-ACN, a framework that automatically decomposes programmer-writtentransactions into closed nested transactions, at run-time, to improve performance. The composition of a closed nested transaction depends on the contention of objects, which can change at run-time depending upon the workload at hand. Our implementation and experimental studies reveal that QR-ACN consistently outperforms flat nesting by an averageof 51% on benchmarks including TPC-C. False conflicts occur when high-level operations, even though semantically independent, traverse the same set of objects during transaction execution. Such conflicts can lead torepeated aborts, increasing transaction execution time and degrading performance, which can be significant in DTM, since transaction execution also includes network communication. ii We consider the approach of reducing validation cost for resolving false conflicts. We presentthree protocols for reducing validation cost in DTM. Our first protocol, QR-ON, incorporatesthe open nesting model into QR-DTM. Open nesting allows inner-nested transactions tocommit independently of their parent transaction, releasing objects in the transaction read-set and write-set early, minimizing aborts due to false conflicts. We then present QR-OON,in which open-nested transactions commit asynchronously so that subsequent transactionscan proceed without waiting for the commit of previous transactions. Finally, we presentan early release methodology, QR-ER, in which objects that do not affect the final state ofthe shared data are dropped from the transaction's read-set, which avoids false conflicts andreduces communication costs. Our implementation and experimental studies revealed that QR-OON outperforms QR-ON by up to 43%, and that QR-ER outperforms QR-ON and QR-OON by up to 10% on micro- and macro-benchmarks.<br>Master of Science

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Books on the topic "Memory fault"

1

Coghlan, B. Transparent stable memory. Trinity College, Department of Computer Science, 1991.

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Sas, Miryam. Fault lines: Cultural memory and Japanese surrealism. Stanford University Press, 1999.

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Coghlan, B. The case for TransparentStable memory. Trinity College, Department of Computer Science, 1991.

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Horiguchi, Masashi. Nanoscale memory repair. Springer, 2011.

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Klemm, W. R. Thank you brain, for all you remember: What you forgot was my fault. Benecton Press, 2004.

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(Firm), Knovel, ed. High performance memory testing: Design principles, fault modeling, and self-test. Kluwer Academic, 2003.

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Adams, R. Dean. High performance memory testing: Design principles, fault modeling, and self-test. Kluwer Academic, 2003.

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Hamdioui, Said. Testing static random access memories: Defects, fault models, and test patterns. Kluwer Academic, 2004.

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Butterfield, A. Memory models: A formal analysis using VDM. Trinity College, Department of Computer Science, 1992.

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Kent, Fuchs W., and United States. National Aeronautics and Space Administration., eds. Ensuring correct rollback recovery in distributed shared memory systems. National Aeronautics and Space Administration, 1995.

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Book chapters on the topic "Memory fault"

1

Joye, Marc, and Mohamed Karroumi. "Memory-Efficient Fault Countermeasures." In Smart Card Research and Advanced Applications. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-27257-8_6.

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Brodal, Gerth Stølting, Allan Grønlund Jørgensen, and Thomas Mølhave. "Fault Tolerant External Memory Algorithms." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03367-4_36.

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Berenbrink, Petra, Friedhelm Meyer auf der Heide, and Volker Stemann. "Fault-tolerant shared memory simulations." In STACS 96. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-60922-9_16.

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Njinda, C. A., C. G. Guy, and W. R. Moore. "Fault Tolerant Integrated Memory Design." In Defect and Fault Tolerance in VLSI Systems. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4615-6799-8_23.

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Balakrishnan, Shobana, Füsun Özgüner, and Baback Izadi. "Fault Tolerance in Hypercubes." In Parallel Computing on Distributed Memory Multiprocessors. Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-642-58066-6_14.

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Li, Lili, Hao Luo, He Qi, and Feiyu Wang. "Sensor Fault Diagnosis Method of Bridge Monitoring System Based on FS-LSTM." In Advances in Frontier Research on Engineering Structures. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8657-4_44.

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AbstractAn improved long-short-term memory neural network (FS-LSTM) fault diagnosis method is proposed based on the problems of damage false alarm, data of health monitoring system incorrect caused by sensor fault in bridge structure health monitoring system. The method is verified by simulating three-span continuous beams to install several sensors and considering the five failures of one sensor, the faults such as: constant, gain, bias, gain linearity bias, and noise. At first, several pieces of white noise data are randomly generated, and each piece of white noise data is applied as a ground pulsation excitation to the structure support, and the acceleration response of the structure at the sensor location is calculated. Simultaneously, each structural response record of each sensor adds white noise with the same signal-to-noise ratio to obtain the test value of each sensor; Secondly, in order to study the generality, except for the five types of faulty sensors in sequence, one sensor is randomly selected from each of the remaining spans, to verify whether there will be a situation where an intact sensor is misdiagnosed as a faulty sensor; Finally, the FS-LSTM network is constructed through the training set to predict the acceleration data, determine the sensor fault threshold, and compare the residual sequence with the fault threshold to diagnose whether the sensor is faulty. The case research of a three-span continuous beam shows that when the above-mentioned five types of faults occur in the sensor, the proposed method can correctly determine whether the sensor is faulty, and it will not be misdiagnosed, which can be used for daily bridge health monitoring. Furthermore, it provides a new method for the maintenance of the bridge health monitoring system.

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Kanellakis, Paris Christos, and Alex Allister Shvartsman. "Shared Memory Randomized Algorithms and Distributed Models and Algorithms." In Fault-Tolerant Parallel Computation. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-5210-6_6.

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Plainfossé, David, and Marc Shapiro. "Experience with a fault-tolerant garbage collector in a distributed lisp system." In Memory Management. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/bfb0017186.

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James, Jerry, and Ambuj K. Singh. "Fault tolerance bounds for memory consistency." In Distributed Algorithms. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0030685.

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Armknecht, Frederik, and Willi Meier. "Fault Attacks on Combiners with Memory." In Selected Areas in Cryptography. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11693383_3.

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Conference papers on the topic "Memory fault"

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Alag, J. C., A. C. T. Quah, D. Nagalingam, P. T. Ng, Y. K. Teoh, and Y. H. Chan. "Static Fault Isolation on Memory BIST Failure." In 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2024. http://dx.doi.org/10.1109/ipfa61654.2024.10691092.

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Benso, A., A. Bosio, S. Carlo, G. Natale, and P. Prinetto. "Memory Fault Simulator for Static-Linked Faults." In 2006 15th Asian Test Symposium. IEEE, 2006. http://dx.doi.org/10.1109/ats.2006.260989.

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Kruger, Kleber, and Fabio Iaione. "Técnicas de Tolerância a Falhas em uma Plataforma para Prototipagem Rápida Usando Microcontroladores." In XX Workshop de Testes e Tolerância a Falhas. Sociedade Brasileira de Computação - SBC, 2019. http://dx.doi.org/10.5753/wtf.2019.7715.

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This paper describes the implementation of fault tolerance techniques (based on data and processing redundancy) in programming of a rapid prototyping platform using microcontrollers. To evaluate performance of these techniques was used a fault injector software and a weather station system as a case study. Experiments simulated faults in sensor readings and faults in SRAM memory regions of the weather station. Finally, the fault-tolerant system performance is presented in comparison with non-fault-tolerant system, considering incidence of failures, processing time, memory and power consumption.

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Gueron, Shay. "Attacks on Encrypted Memory and Constructions for Memory Protection." In 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). IEEE, 2016. http://dx.doi.org/10.1109/fdtc.2016.20.

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Harutyunyan, G. "Extending fault periodicity table for testing external memory faults." In 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2016. http://dx.doi.org/10.1109/ewdts.2016.7807738.

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Yu-Tsao Hsing, Song-Guang Wu, and Cheng-Wen Wu. "RAMSES-D: DRAM fault simulator supporting weighted coupling fault." In 2007 IEEE International Workshop on Memory Technology, Design and Testing (MTDT). IEEE, 2007. http://dx.doi.org/10.1109/mtdt.2007.4547612.

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Safran, Laura, Christopher Hodge, and John Sylvestri. "Targeted Memory Test for Enhanced Diagnostic Fault Localization." In ISTFA 2017. ASM International, 2017. http://dx.doi.org/10.31399/asm.cp.istfa2017p0511.

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Abstract A customized test resource has been created on Linux based automated test system to enhance and accelerate diagnostics and fault localization on random access memory. The resource, Targeted Memory Test, allows creation of a user defined sub-array which targets a specific area of a memory array. The resource includes a customized pattern set which can then be used with the unique Advanced Characterization shmoo plot routine to fully characterize any given failure mode. The sub-array patterns and characterization data can provide a clear understanding of the failure and reduce the time needed for both fault localization and physical failure analysis.

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Fournier, Jacques J. A., and Philippe Loubet-Moundi. "Memory Address Scrambling Revealed Using Fault Attacks." In 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). IEEE, 2010. http://dx.doi.org/10.1109/fdtc.2010.13.

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Liang, Lin, Guanghua Xu, and Tao Sun. "Immune Memory Network-Based Fault Diagnosis." In 2006 6th International Conference on Intelligent Systems Design and Applications. IEEE, 2006. http://dx.doi.org/10.1109/isda.2006.173.

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Zhou, Feng. "Fault diagnosis of dynamic memory board." In International Conference on Intelligent Manufacturing, edited by Shuzi Yang, Ji Zhou, and Cheng-Gang Li. SPIE, 1995. http://dx.doi.org/10.1117/12.217514.

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Reports on the topic "Memory fault"

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Banergee, Prithviraj. A Novel System Level Approach to Fault Tolerance in Distributed Memory Multicomputers. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada284729.

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