Dissertations / Theses on the topic 'Memory fault'

Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to transient faults. Applications can be protected against faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to program representations at abstraction levels higher than machine instructions are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, a large proportion of a program’s memory accesses are introduced by the compiler backend. This report presents a backend that protects these accesses against faults in the memory system. It is demonstrated that the presented backend can detect all single bit flips in memory that would be missed by an error detection scheme that operates on the LLVM intermediate representation of programs. The presented compiler backend is obtained by modifying the LLVM backend for the x86 architecture. On a subset of SPEC CINT2006 the runtime overhead incurred by the backend modifications amounts to 1.50x for the 32-bit processor architecture i386, and 1.13x for the 64-bit architecture x86_64. To achieve comprehensive detection of memory faults, the modified backend implements an adjusted calling convention that leaves library function calls transparent and intact.

Les technologies émergentes, telles que les objets connectés et les réseaux sociaux sont en train de changer notre manière d’interagir avec autrui. De par leur large adoption, ces technologies génèrent de plus en plus de données. Alors que la gestion de larges volumes de données fut l’un des sujets majeurs de la dernière décennie, un nouveau défi est apparu récemment : comment tirer profit de données générées en temps réel. Avec la croissance des capacités de mémoires vives, plusieurs fournisseurs services, tel que Facebook, déploient des péta-octets de DRAM afin de garantir un temps d’accès rapide aux données. Néanmoins, les mémoires vives sont volatiles, et nécessitent souvent des mécanismes de tolérance aux pannes coûteux en termes de performance. Ceci crée des compromis entre la performance, la tolérance aux pannes et l’efficacité dans les systèmes de stockage basés sur les mémoires vives. Dans cette thèse, nous commençons, d’une part, par étudier ces compromis : nous identifions les facteurs principaux qui impactent la performance, l’efficacité et la tolérance aux pannes dans les systèmes de stockage en mémoire.Ensuite, nous concevons et implémentons un nouveau mécanisme de réplication basé sur l’accès à la mémoire distante (RDMA). Enfin, nous portons cette technique à un nouveau type de système de stockage : les systèmes de stockage pour streaming. Nous concevons et implémentons des mécanismes de réplication et de tolérance aux pannes efficaces et un impact minimal sur les performances sur le stockage pour streaming<br>Emerging technologies such as connected devices and social networking applications are shaping the way we live, work, and interact with each other. These technologies generate increasingly high volumes of data. Dealing with large volumes of data has been an important focus in the last decade, however, today the challenge has shifted from data volume to velocity: How to store, process, and extract value from data generated With the growing capacity of DRAM, service providers largely rely on DRAM-based storage systems to serve their workloads. Because DRAM is volatile, usually, distributed in-memory storage systems rely on expensive durability mechanisms to persist data.This creates trade-offs between performance, durability and efficiency in in-memory storage systems We first study these trade-offs by means of experimental study. We extract the main factors that impact performance and efficiency in in-memory storage systems. Then, we design and implement a new RDMA-based replication mechanism that greatly improves replication efficiency in in-memory storage systems. Finally, we leverage our techniques and apply them to stream storage systems. We design and implement high-performance replication mechanisms for stream storage, while guaranteeing linearizability and durability

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.<br>Includes bibliographical references (leaves 145-147).<br>by Bryan P. Butler.<br>M.S.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003.<br>Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.

Distributed Transactional Memory (DTM) is an emerging synchronization abstraction thatpromises to alleviate the scalability, programmability, and composability challenges of lock-based distributed synchronization. With DTM, programmers organize code that read/writeshared memory objects, both local and remote, as memory transactions. An underlying DTMframework guarantees atomicity, isolation, and consistency properties for those transactionsthrough speculative concurrency control. In DTM, restarting an aborted transaction from the beginning can degrade performance astransactional conflicts may have occurred in the later part of the transaction, wasting work.The partial abort method alleviates this difficulty by enabling a transaction to be rolled backto the point where objects in the transaction's read-set and write-set are still consistent.In this thesis, we present protocols for supporting partial aborts in QR-DTM, a fault-tolerant DTM that uses quorum protocols for distributed concurrency control in the presence offailures. We focus on two partial abort models: closed nesting, which allows transactions to be nested and inner transactions to be rolled back without rolling back outer transactions;and checkpointing, which allows the transaction state to be saved in checkpoints throughout execution and transactions to be rolled back to those checkpoints. We present protocols that support these partial abort models in QR-DTM, called QR-CN and QR-CHK. We implemented these protocols and conducted experimental studies using macro-benchmarks(e.g., distributed versions of STAMP benchmark), and micro-benchmarks (e.g., distributed data structures). Our studies reveal that QR-CN improves throughput by as much as 101% over flat nesting in specific cases, with an average improvement of 53%. We also develop QR-ACN, a framework that automatically decomposes programmer-writtentransactions into closed nested transactions, at run-time, to improve performance. The composition of a closed nested transaction depends on the contention of objects, which can change at run-time depending upon the workload at hand. Our implementation and experimental studies reveal that QR-ACN consistently outperforms flat nesting by an averageof 51% on benchmarks including TPC-C. False conflicts occur when high-level operations, even though semantically independent, traverse the same set of objects during transaction execution. Such conflicts can lead torepeated aborts, increasing transaction execution time and degrading performance, which can be significant in DTM, since transaction execution also includes network communication. ii We consider the approach of reducing validation cost for resolving false conflicts. We presentthree protocols for reducing validation cost in DTM. Our first protocol, QR-ON, incorporatesthe open nesting model into QR-DTM. Open nesting allows inner-nested transactions tocommit independently of their parent transaction, releasing objects in the transaction read-set and write-set early, minimizing aborts due to false conflicts. We then present QR-OON,in which open-nested transactions commit asynchronously so that subsequent transactionscan proceed without waiting for the commit of previous transactions. Finally, we presentan early release methodology, QR-ER, in which objects that do not affect the final state ofthe shared data are dropped from the transaction's read-set, which avoids false conflicts andreduces communication costs. Our implementation and experimental studies revealed that QR-OON outperforms QR-ON by up to 43%, and that QR-ER outperforms QR-ON and QR-OON by up to 10% on micro- and macro-benchmarks.<br>Master of Science

Actualmente, los clústeres de PCs están considerados como una alternativa eficiente a la hora de construir supercomputadores en los que miles de nodos de computación se conectan mediante una red de interconexión. La red de interconexión tiene que ser diseñada cuidadosamente, puesto que tiene una gran influencia sobre las prestaciones globales del sistema. Dos de los principales parámetros de diseño de las redes de interconexión son la topología y el encaminamiento. La topología define la interconexión de los elementos de la red entre sí, y entre éstos y los nodos de computación. Por su parte, el encaminamiento define los caminos que siguen los paquetes a través de la red. Las prestaciones han sido tradicionalmente la principal métrica a la hora de evaluar las redes de interconexión. Sin embargo, hoy en día hay que considerar dos métricas adicionales: el coste y la tolerancia a fallos. Las redes de interconexión además de escalar en prestaciones también deben hacerlo en coste. Es decir, no sólo tienen que mantener su productividad conforme aumenta el tamaño de la red, sino que tienen que hacerlo sin incrementar sobremanera su coste. Por otra parte, conforme se incrementa el número de nodos en las máquinas de tipo clúster, la red de interconexión debe crecer en concordancia. Este incremento en el número de elementos de la red de interconexión aumenta la probabilidad de aparición de fallos, y por lo tanto, la tolerancia a fallos es prácticamente obligatoria para las redes de interconexión actuales. Esta tesis se centra en la topología fat-tree, ya que es una de las topologías más comúnmente usadas en los clústeres. El objetivo de esta tesis es aprovechar sus características particulares para proporcionar tolerancia a fallos y un algoritmo de encaminamiento capaz de equilibrar la carga de la red proporcionando una buena solución de compromiso entre las prestaciones y el coste.<br>Gómez Requena, C. (2010). Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/8856<br>Palancia

Storytelling holds a significant place in peace education and dialogue work with young people in Israel/Palestine, reflecting the popularity of the dual narrative approach as a framework for understanding the conflict. The approach is predicated on the assumption that there are two competing national narratives that have collided in the same geographical space, with young people only able to come to terms with the ‘other’ narrative through a process of concession and compromise, mediated by adults. Recognising the constraints and limitations of the dual narrative approach, my thesis focuses on the lives of Israeli and Palestinian youth who inhabit a border of some kind (physical, linguistic, ethnic, or intergenerational) and analyzes how stories are transmitted across and influenced by such boundaries. Special attention is given to traumatic histories that carry a social taboo, such as the Nakba in Israeli society and the Holocaust in Palestine, and how young people may develop and express their conceptions of community, belonging, and exclusion through storytelling. The research is grounded in ethnographic fieldwork and practical storytelling workshops conducted over sixteen months in Israel/Palestine (March 2014 to July 2015), with various methods of narrative inquiry forming the basis for data analysis, notably Interpretative Phenomenological Analysis (IPA). The thesis is divided into four chapters, which are based on the dominant themes that emerged through fieldwork. ‘Language and the Hidden Landscape’ is an applied linguistic analysis of how young people living in segregated communities imagine and narrate places that are off-limits to them. ‘Violence in the Narration of Self and Other’, an examination of the violence inherent in face-to-face storytelling that is grounded in the phenomenological theory, discusses how the storytellers deal with violence through narrative, their depiction of members of the ‘other’ community’, and the more disturbing and potentially violent functions of storytelling in peace education for youth. ‘Forbidden Histories in Contested Spaces’ unpicks the shadowy interweave between Holocaust and Nakba memory, while ‘Happily Ever After?’ examines how the narrators view and construct endings – both for the conflict, and in their narratives. These themes bring together time, place, and inhabitants’ interaction with place and memory, resulting in a more complex and nuanced understanding of how young people growing up with intractable conflict use storytelling to interpret their histories and make sense of their lives in the present day, as well as the ways in which stories may interact even in a highly polarized and segregated society. In conclusion, the role of storytelling with children in conflict zones is re-evaluated, with the research suggesting that there needs to be a shift in emphasis from storytelling as a means of therapy to storytelling as a social and political act, a means of enabling young people to take a more active role in community-building, rehabilitation, and ultimately reconciliation.

With the recent technological developments in last few decades, there is a notable shift in the way business/consumer transactions are conducted. These transactions are usually triggered over the internet and transactional systems working in the background ensure that these transactions are processed. The majority of these transactions nowadays fall in Online Transaction Processing (OLTP) category, where low latency is preferred characteristic. In addition to low latency, OLTP transaction systems also require high service continuity and dependability. Replication is a common technique that makes the services dependable and therefore helps in providing reliability, availability and fault-tolerance. Deferred Update Replication (DUR) and Deferred Execution Replication (DER) represent the two well known transaction execution models for replicated transactional systems. Under DUR, a transaction is executed locally at one node before a global certification is invoked to resolve conflicts against other transactions running on remote nodes. On the other hand, DER postpones the transaction execution until the agreement on a common order of transaction requests is reached. Both DUR and DER require a distributed ordering layer, which ensures a total order of transactions even in case of faults. In today's distributed transactional systems, performance is of paramount importance. Any loss in performance, e.g., increased latency due to slow processing of client requests, may entail loss of revenue for businesses. On one hand, the DUR model is a good candidate for transaction processing in those systems in case the conflicts among transactions are rare, while it can be detrimental for high conflict workload profiles. On the other hand, the DER model is an attractive choice because of its ability to behave as independent of the characteristics of the workload, but trivial realizations of the model ultimately do not offer a good performance increase margin. Indeed transactions are executed sequentially and the total order layer can be a serious bottleneck for latency and scalability. This dissertation proposes novel solutions and system optimizations to enhance the overall performance of replicated transactional systems. The first presented result is HiperTM, a DER-based transaction replication solution that is able to alleviate the costs of the total order layer via speculative execution techniques. HiperTM exploits the time that is between the broadcast of a client request and the finalization of the order for that request to speculatively execute the request, so to achieve an overlapping between replicas coordination and transactions execution. HiperTM proposes two main components: OS-Paxos, a novel total order layer that is able to early deliver requests optimistically according to a tentative order, which is then either confirmed or rejected by a final total order; SCC, a lightweight speculative concurrency control protocol that is able to exploit the optimistic delivery of OS-Paxos and execute transactions in a speculative fashion. SCC still processes write transactions serially in order to minimize the code instrumentation overheads, but it is able to parallelize the execution of read-only transactions thanks to its built-in object multiversion scheme. The second contribution in this dissertation is X-DUR, a novel transaction replication system that addressed the high cost of local and remote aborts in case of high contention on shared objects in DUR based approaches, due to which the performance is adversely affected. Exploiting the knowledge of client's transaction locality, X-DUR incorporates the benefits of state machine approach to scale-up the distributed performance of DUR systems. As third contribution, this dissertation proposes Archie, a DER-based replicated transactional system that improves HiperTM in two aspects. First, Archie includes a highly optimized total order layer that combines optimistic-delivery and batching thus allowing the anticipation of a big amount of work before the total order is finalized. Then the concurrency control is able to process transactions speculatively and with a higher degree of parallelism, although the order of the speculative commits still follows the order defined by the optimistic delivery. Both HiperTM and Archie perform well up to a certain number of nodes in the system, beyond which their performance is impacted by limitations of single leader-based total-order layer. This motivates the design of Caesar, the forth contribution of this dissertation, which is a transactional system based on a novel multi-leader partial order protocol. Caesar enforces a partial order on the execution of transactions according to their conflicts, by letting non-conflicting transactions to proceed in parallel and without enforcing any synchronization during the execution (e.g., no locks). As the last contribution, this dissertation presents Dexter, a replication framework that exploits the commonly observed phenomenon such that not all read-only workloads require up-to-date data. It harnesses the application specific freshness and content-based constraints of read-only transactions to achieve high scalability. Dexter services the read-only requests according to the freshness guarantees specified by the application and routes the read-only workload accordingly in the system to achieve high performance and low latency. As a result, Dexter framework also alleviates the interference between read-only requests and read-write requests thereby helping to improve the performance of read-write requests execution as well.<br>Ph. D.

As services grow and receive more traffic, data resilience through replication becomes increasingly important. Modern large-scale Internet services such as Facebook, Google and Twitter serve millions of users concurrently. Replication is a vital component of distributed systems. Eventual consistency and Conflict-Free Replicated Data Types (CRDTs) are suggested as an alternative to strong consistency systems. This thesis implements and evaluates Snapple, a distributed, fault-tolerant, in-memory key-value database based on CRDTs running on the Java Virtual Machine. Snapple supports two kinds of CRDTs, an optimized implementation of the OR-Set and version vectors. Performance measurements show that the Snapple system is significantly faster than Riak, a persistent database based on CRDTs, but has a factor 5x - 2.5x lower throughput than Redis, a popular in-memory key-value database written in C. Snapple is a prototype-implementation but might be a viable alternative to Redis if the user wants the consistency guarantees CRDTs provide.<br>När internet-baserade tjänster växer och får mer trafik blir data replikering allt viktigare. Moderna storskaliga internet-baserade tjänster såsom Facebook, Google och Twitter hanterar miljoner av förfrågningar från användare samtidigt. Datareplikering är en vital komponent av distribuerade system. Eventuell synkronisering och Konfliktfria Replikerade Datatyper (CRDTs) är föreslagna som alternativ till direkt synkronisering. Denna uppsats implementerar och evaluerar Snapple, en distribuerad feltolerant nyckelvärdesdatabas i RAM-minnet baserad på CRDTs och som exekverar på Javas virtuella maskin. Snapple stödjer två sorters CRDTs, den optimerade implementationen av observera-ta-bort setet och versionsvektorer. Prestanda-mätningar visar att Snapple-systemet är mycket snabbare än Riak, en persistent databas baserad på CRDTs. Snapple visar sig ha 5x - 2.5x lägre genomströmning än Redis, en popular i-minnet nyckel-värdes databas skriven i C. Snapple är en prototyp men CRDT-stödda system kan vara ett värdigt alternativ till Redis om användaren vill ta del av synkroniseringsgarantierna som CRDTs tillhandahåller.

A distributed system is defined as a collection of autonomous computers connected by a network, and with the appropriate distributed software for the system to be seen by users as a single entity capable of providing computing facilities. Distributed systems with centralised control have a distinguished control node, called leader node. The main role of a leader node is to distribute and manage shared resources in a resource-efficient manner. A distributed system with centralised control can use stream processing networks for communication. In a stream processing system, applications typically act as continuous queries, ingesting data continuously, analyzing and correlating the data, and generating a stream of results. Fault tolerance is the ability of a system to process the information, even if it happens any failure or anomaly in the system. Fault tolerance has become an important requirement for distributed systems, due to the possibility of failure has currently risen to the increase in number of nodes and the runtime of applications in distributed system. Therefore, to resolve this problem, it is important to add fault tolerance mechanisms order to provide the internal capacity to preserve the execution of the tasks despite the occurrence of faults. If the leader on a centralised control system fails, it is necessary to elect a new leader. While leader election has received a lot of attention in message-passing systems, very few solutions have been proposed for shared memory systems, as we propose. In addition, rollback-recovery strategies are important fault tolerance mechanisms for distributed systems, since that it is based on storing information into a stable storage in failure-free state and when a failure affects a node, the system uses the information stored to recover the state of the node before the failure appears. In this thesis, we are focused on creating two fault tolerance mechanisms for distributed systems with centralised control that uses stream processing for communication. These two mechanism created are leader election and log-based rollback-recovery, implemented using LPEL. The leader election method proposed is based on an atomic Compare-And-Swap (CAS) instruction, which is directly available on many processors. Our leader election method works with idle nodes, meaning that only the non-busy nodes compete to become the new leader while the busy nodes can continue with their tasks and later update their leader reference. Furthermore, this leader election method has short completion time and low space complexity. The log-based rollback-recovery method proposed for distributed systems with stream processing networks is a novel approach that is free from domino effect and does not generate orphan messages accomplishing the always-no-orphans consistency condition. Additionally, this approach has lower overhead impact into the system compared to other approaches, and it is a mechanism that provides scalability, because it is insensitive to the number of nodes in the system.

Dissertação(mestrado) - Universidade Federal do Rio Grande, Programa de Pós-Graduação em Letras, Instituto de Letras e Artes, 2010.<br>Submitted by Cristiane Silva (cristiane_gomides@hotmail.com) on 2012-10-20T10:50:47Z No. of bitstreams: 1 sarapinho.pdf: 776948 bytes, checksum: eadb2d192bf011f9be6bfa5a2755bd0b (MD5)<br>Approved for entry into archive by Bruna Vieira(bruninha_vieira@ibest.com.br) on 2012-11-05T13:57:17Z (GMT) No. of bitstreams: 1 sarapinho.pdf: 776948 bytes, checksum: eadb2d192bf011f9be6bfa5a2755bd0b (MD5)<br>Made available in DSpace on 2012-11-05T13:57:17Z (GMT). No. of bitstreams: 1 sarapinho.pdf: 776948 bytes, checksum: eadb2d192bf011f9be6bfa5a2755bd0b (MD5) Previous issue date: 2010<br>Fault Lines (2007) de Nancy Huston apresenta um novo caminho para os estudos no campo do entrecruzamento entre a história e a ficção. As duas formas narrativas intercambiam seus modos de lidar com o tempo, mas a infância ainda não fazia parte dessas correspondências. Nas narrativas de quatro crianças de seis anos da mesma família, porém, em épocas e lugares diferenciados, adentramos a história maior sob uma perspectiva infantil. De 2004 a 1945, o tempo presente se torna passado e as linhas de falha de cada personagem se tornam evidentes. Sol, Randall, Sadie e Kristina redimensionam a história dos adultos e revelam, através da ficção, uma nova forma de olhar o tempo pretérito.<br>Fault Lines (2007) by Nancy Huston introduces a new path for studies in the field of the exchanges between history and fiction. The two narrative-forms trade with each other their perspectives of time, but childhood was not part of this deal. Through the narratives of four six year-old children from the same family, however, at different times and places, we visit major history under a child’s eyes. From 2004 to 1945, the present time walks to the past and the fault lines of each character become evident. Sol, Randall, Sadie and Kristina present a different version for the historical events and show through fiction a new way of looking at the past time.

L’objectif de cette thèse est de développer un observateur non linéaire pour un outil de diagnostic pour des systèmes non linéaires à temps continu et à mesures discrètes. Ce mémoire débute par l’étude de notions d’observabilité faisant le point sur l’observation de ces systèmes. Nous enchaînons ensuite par l’analyse d’observateurs non linéaires obtenu par optimisation, puis nous présentons les méthodes de diagnostic à l'aide d'observateurs. Un observateur à mémoire finie est ensuite synthétisé pour détecter et localiser les défauts capteurs et actionneurs d’une classe de systèmes non linéaires en présence à la fois de bruit de processus et de bruit de mesures. De plus, un observateur non linéaire est également construit sur un modèle augmenté pour estimer simultanément les états du système et les entrées inconnues. Une étude de robustesse vis à vis des divers bruits a été menée, ainsi que l'étude de la définition des défaut d'amplitude minimale pour la détection. L'utilisation de l'algorithme EWMA a également été introduit pour ses performance en détection. Le cas de multiple défauts simultanés ont été détectés et identifiés dans cette partie. À la fin de cette thèse, un observateur à mémoire finie est développé pour les systèmes non linéaires à temps variants<br>The aim of this thesis is to design a nonlinear observer as a diagnostic tool for continuous-time nonlinear systems with discrete-time measurements. We begin with the study of some observability notions concerning the considered nonlinear systems, following by the presents of three typical optimization-based nonlinear observers and observer-based diagnostic methods. Inspired by the existing approaches, a finite memory observer is then designed for a class of nonlinear systems in the presence of both process and measurement noises in order to perform fault detection and isolation of sensor and actuator faults. In the second part, a nonlinear observer based on augmented model is then designed to simultaneously estimate both system states and unknown inputs. The robustness with respect to the diverse noises is studied, as well as the study of the minimum amplitude of fault for the detection. The EWMA algorithm was also introduced and analyzed for its performance in detection. Multiple simultaneous faults are also detected and identified in this part. At the end of this thesis, a finite memory observer is designed for the nonlinear time-varying systems on the basis of the fundamental synthesis for linear time-varying systems

L’environnement radiatif spatial est un environnement sévère qui agit sur tout composants électroniques embarqués sur des engins spatiaux, y compris sous le bouclier naturel que nous procure le champ magnétique terrestre en orbite basse. Bien qu’il soit possible, en particulier à ces orbites, de se protéger efficacement contre les particules créant de la dose totale ionisante, cela pose plus de difficultés pour les particules générant des effets singuliers. Cela est d’autant plus un problème que l’utilisation des composants commerciaux (dits « COTS »), non conçus pour de telles applications, sont de plus en plus utilisés. Dans le cadre de cette thèse, les effets singuliers sur trois types de mémoires sont étudiés: SRAM, FRAM et NAND Flash. En se basant sur l’analyse des résultats de tests, les mécanismes d’erreurs induits par des particules générant des effets singuliers sont analysés. Avec pour objectif d’étudier et comparer la sensibilité de ces mémoires directement en orbite, l’expérience RES (Radiation Effect Study) a été développée et est présentée dans ce manuscrit. Cette expérience scientifique constituera la charge utile du nanosatellite de type CubeSat nommé MTCube (Memory Test CubeSat) developpé à l’Université de Montpellier en collaboration entre le Centre Spatial Universitaire Montpellier-Nîmes, et les laboratoires LIRMM et IES. Ce nanosatellite est financé par l’ESA (Agence Spatial Européenne)<br>Space radiation is a harsh environment affecting all electronic devices used on spacecraft, despite the presence of Earth’s protective magnetic field in Low Earth Orbit (LEO). Although particles inducing total ionizing dose (TID) can be effectively shielded against in LEO, particles responsible for Single Event Effects (SEEs) remain an issue for the reliability of electronics. This is particularly of concern considering the increasing use of Commercial-Off-The-Shelf (COTS) components, not designed for space applications. In the frame of this thesis, the SEE response of three commercial memory types are explored: SRAM, FRAM and NAND Flash. Based on SEE test results, the possible fault mechanisms induced by SEE particles on those devices are analysed. In order to study and compare the devices’ response with actual in-orbit measurements, the RES (Radiation Effect Study) science experiment was developed and is presented. The RES experiment will be the payload of the MTCube (Memory Test CubeSat) nanosatellite, which is being developed at the University of Montpellier as a joint project between the University Space Center (CSU Montpellier-Nîmes), as well as the LIRMM and IES laboratories. MTCube is financed by the European Space Agency (ESA)

Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications.

[EN] SRAM technology has traditionally been used to implement processor caches since it is the fastest existing RAM technology.However,one of the major drawbacks of this technology is its high energy consumption.To reduce this energy consumption modern processors mainly use two complementary techniques: i)low-power operating modes and ii)low-power memory technologies.The first technique allows the processor working at low clock frequencies and supply voltages.The main limitation of this technique is that manufacturing defects can significantly affect the reliability of SRAM cells when working these modes.The second technique brings alternative technologies such as eDRAM, which provides minimum area and power consumption.The main drawback of this memory technology is that reads are destructive and eDRAM cells work slower than SRAM ones. This thesis presents three main contributions regarding low-power caches and heterogeneous technologies: i)an study that identifies the optimal capacitance of eDRAM cells, ii)a novel cache design that tolerates the faults produced by SRAM cells in low-power modes, iii)a methodology that allows obtain the optimal operating frequency/voltage level when working with low-power modes. Regarding the first contribution,in this work SRAM and eDRAM technologies are combined to achieve a low-power fast cache that requires smaller area than conventional designs and that tolerates SRAM failures.First,this dissertation focuses on one of the main critical aspects of the design of heterogeneous caches:eDRAM cell capacitance.In this dissertation the optimal capacitance for an heterogeneous L1 data cache is identified by analyzing the compromise between performance and energy consumption.Experimental results show that an heterogeneous cache implemented with 10fF capacitors offers similar performance as a conventional SRAM cache while providing 55% energy savings and reducing by 29% the cache area. Regarding the second contribution,this thesis proposes a novel organization for a fault-tolerant heterogeneous cache.Currently,reducing the supply voltage is a mechanism widely used to reduce consumption and applies when the system workload activity decreases.However,SRAM cells cause different types of failures when the supply voltage is reduced and thus they limit the minimum operating voltage of the microprocessor. In the proposal,memory cells implemented with eDRAM technology serve as backup in case of failure of SRAM cells, because the correct operation of eDRAM cells is not affected by reduced voltages. The proposed architecture has two working modes: high-performance mode for supply voltages that do not induce SRAM cell failures, and low-power mode for those voltages that cause SRAM cell failures. In high-performance mode, the cache provides full capacity, which enables the processor to achieve its maximum performance. In low-power mode, the effective capacity of the cache is reduced because some of the eDRAM cells are dedicated to recover from SRAM failures. Experimental results show that the performance is scarcely reduced (e.g. less than 2.7% across all the studied benchmarks) with respect to an ideal SRAM cache without failures. Finally,this thesis proposes a methodology to find the optimal frequency/voltage level regarding energy consumption for the designed heterogeneous cache. For this purpose, first SRAM failure types and their probabilities are characterized.Then,the energy consumption of different frequency/voltage levels is evaluated when the system works in low-power mode.The study shows that, mainly due to the impact of SRAM failures on performance,the optimal combination of voltage and frequency from the energy point of view does not always correspond to the minimum voltage.<br>[ES] La tecnología SRAM se ha utilizado tradicionalmente para implementar las memorias cache debido a que es la tecnología de memoria RAM más rápida existente.Por contra,uno de los principales inconvenientes de esta tecnología es su elevado consumo energético.Para reducirlo los procesadores modernos suelen emplear dos técnicas complementarias:i) modos de funcionamiento de bajo consumo y ii)tecnologías de bajo consumo.La primeras técnica consiste en utilizar bajas frecuencias y voltajes de funcionamiento.La principal limitación de esta técnica es que los defectos de fabricación pueden afectar notablemente a la fiabilidad de las celdas SRAM en estos modos.La segunda técnica agrupa tecnologías alternativas como la eDRAM,que ofrece área y consumo mínimos.El inconveniente de esta tecnología es que las lecturas son destructivas y es más lenta que la SRAM. Esta tesis presenta tres contribuciones principales centradas en caches de bajo consumo y tecnologías heterogéneas: i)estudio de la capacitancia óptima de las celdas eDRAM, ii)diseño de una cache tolerante a fallos producidos en las celdas SRAM en modos de bajo consumo, iii)metodología para obtener la relación óptima entre voltaje y frecuencia en procesadores con modos de bajo consumo. Respecto a la primera contribución,en este trabajo se combinan las tecnologías SRAM y eDRAM para conseguir una memoria cache rápida, de bajo consumo, área reducida, y tolerante a los fallos inherentes a la tecnología SRAM.En primer lugar,esta disertación se centra en uno de los aspectos críticos de diseño de caches heterogéneas SRAM/eDRAM: la capacitancia de los condensadores implementados con tecnología eDRAM.En esta tesis se identifica la capacitancia óptima de una cache de datos L1 heterogénea mediante el estudio del compromiso entre prestaciones y consumo energético.Los resultados experimentales muestran que condensadores de 10fF ofrecen prestaciones similares a las de una cache SRAM convencional ahorrando un 55% de consumo y reduciendo un 29% el área ocupada por la cache. Respecto a la segunda contribución,esta tesis propone una organización de cache heterogénea tolerante a fallos.Actualmente,reducir el voltaje de alimentación es un mecanismo muy utilizado para reducir el consumo en condiciones de baja carga.Sin embargo,las celdas SRAM producen distintos tipos de fallos cuando se reduce el voltaje de alimentación y por tanto limitan el voltaje mínimo de funcionamiento del microprocesador. En la cache heterogénea propuesta,las celdas de memoria implementadas con tecnología eDRAM sirven de copia de seguridad en caso de fallo de las celdas SRAM, ya que el correcto funcionamiento de las celdas eDRAM no se ve afectado por tensiones reducidas.La arquitectura propuesta consta de dos modos de funcionamiento: high-performance mode para voltajes de alimentación que no inducen fallos en celdas implementadas en tecnología SRAM, y low-power mode para aquellos que sí lo hacen. En el modo high-performance mode,el procesador dispone de toda la capacidad de la cache.En el modo low-power mode se reduce la capacidad efectiva de la cache puesto que algunas de las celdas eDRAM se dedican a la recuperación de fallos de celdas SRAM.El estudio de prestaciones realizado muestra que éstas bajan hasta un máximo de 2.7% con respecto a una cache perfecta sin fallos. Finalmente, en esta tesis se propone una metodología para encontrar la relación óptima de voltaje/frecuencia con respecto al consumo energético sobre la cache heterogénea previamente diseñada. Para ello,primero se caracterizan los tipos de fallos SRAM y las probabilidades de fallo de los mismos.Después,se evalúa el consumo energético de diferentes combinaciones de voltaje/frecuencia cuando el sistema se encuentra en un modo de bajo consumo.El estudio muestra que la combinación óptima de voltaje y frecuencia desde el punto de vista energético no siempre corresponde al mínimo voltaje debido al imp<br>[CAT] La tecnologia SRAM s'ha utilitzat tradicionalment per a implementar les memòries cau degut a que és la tecnologia de memòria RAM més ràpida existent.Per contra, un dels principals inconvenients d'aquesta tecnologia és el seu elevat consum energètic.Per a reduir el consum els processadors moderns solen emprar dues tècniques complementàries: i)modes de funcionament de baix consum i ii)tecnologies de baix consum.La primera tècnica consisteix en utilitzar baixes freqüències i voltatges de funcionament.La principal limitació d'aquesta tècnica és que els defectes de fabricació poden afectar notablement a la fiabilitat de les cel·les SRAM en aquests modes.La segona tècnica agrupa tecnologies alternatives com la eDRAM, que ofereix àrea i consum mínims.L'inconvenient d'aquesta tecnologia és que les lectures són destructives i és més lenta que la SRAM. Aquesta tesi presenta tres contribucions principals centrades en caus de baix consum i tecnologies heterogènies: i)estudi de la capacitancia òptima de les cel·les eDRAM, ii)disseny d'una cau tolerant a fallades produïdes en les cel·les SRAM en modes de baix consum, iii)metodologia per a obtenir la relació òptima entre voltatge i freqüència en processadors amb modes de baix consum. Respecte a la primera contribució, en aquest treball es combinen les tecnologies SRAM i eDRAM per a aconseguir una memòria cau ràpida, de baix consum, àrea reduïda, i tolerant a les fallades inherents a la tecnologia SRAM.En primer lloc, aquesta dissertació se centra en un dels aspectes crítics de disseny de caus heterogènies: la capacitancia dels condensadors implementats amb tecnologia eDRAM.En aquesta dissertació s'identifica la capacitancia òptima d'una cache de dades L1 heterogènia mitjançant l'estudi del compromís entre prestacions i consum energètic.Els resultats experimentals mostren que condensadors de 10fF ofereixen prestacions similars a les d'una cau SRAM convencional estalviant un 55% de consum i reduint un 29% l'àrea ocupada per la cau. Respecte a la segona contribució, aquesta tesi proposa una organització de cau heterogènia tolerant a fallades.Actualment,reduir el voltatge d'alimentació és un mecanisme molt utilitzat per a reduir el consum en condicions de baixa càrrega.Per contra, les cel·les SRAM produeixen diferents tipus de fallades quan es redueix el voltatge d'alimentació i per tant limiten el voltatge mínim de funcionament del microprocessador. En la cau heterogènia proposta, les cel·les de memòria implementades amb tecnologia eDRAM serveixen de còpia de seguretat en cas de fallada de les cel·les SRAM, ja que el correcte funcionament de les cel·les eDRAM no es veu afectat per tensions reduïdes.L'arquitectura proposada consta de dues maneres de funcionament: high-performance mode per a voltatges d'alimentació que no indueixen fallades en cel·les implementades en tecnologia SRAM,i low-power mode per a aquells que sí ho fan.En el mode high-performance,el processador disposa de tota la capacitat de la cau.En el mode low-power es redueix la capacitat efectiva de la cau posat que algunes de les cel·les eDRAM es dediquen a la recuperació de fallades de cel·les SRAM.L'estudi de prestacions realitzat mostra que aquestes baixen fins a un màxim de 2.7% pel que fa a una cache perfecta sense fallades. Finalment,en aquesta tesi es proposa una metodologia per a trobar la relació òptima de voltatge/freqüència pel que fa al consum energètic sobre la cau heterogènia prèviament dissenyada.Per a açò,primer es caracteritzen els tipus de fallades SRAM i les probabilitats de fallada de les mateixes.Després,s'avalua el consum energètic de diferents combinacions de voltatge/freqüència quan el sistema es troba en un mode de baix consum.L'estudi mostra que la combinació òptima de voltatge i freqüència des del punt de vista energètic no sempre correspon al mínim voltatge degut a l'impacte de les fallades de SRAM en les pres<br>Lorente Garcés, VJ. (2015). Cache architectures based on heterogeneous technologies to deal with manufacturing errors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/58428<br>TESIS

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação.<br>Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.

Depuis quelques années, les mémoires non-volatiles de type Flash sont présentes dans un grand nombre de systèmes sur puce. La grande densité d'intégration et la complexité de leur procédé de fabrication rendent les mémoires Flash de plus en plus sujette aux défauts. La présence de défauts dans les mémoires est une des problématiques majeures. En effet, de tels défauts pourraient affecter le rendement, la rétention, l'endurance et donc la fiabilité des mémoires Flash. Cette thèse a porté sur l'analyse des mécanismes de défaillances, la modélisation des comportements fautifs et le développement de solution en vue d'améliorer le test des mémoires Flash. Dans ce contexte, nous avons proposé un modèle SPICE de la mémoire Flash TSTAC™ d'ATMEL. En comparaison avec l'état de l'art, le modèle SPICE proposé permet de simuler les opérations fonctionnelles de la mémoire de manière dynamique. Ce modèle a était utilisé pour effectuer des simulations d'injections de défauts réalistes pouvant affecter la matrice de la mémoire Flash TSTAC™. Ces simulations ont permis de prédire leurs comportements fautifs et de déterminer leurs modèles de fautes. D'autres types de simulations électriques effectuées à l'aide du modèle électrique ont permis de développer deux méthodes de caractérisation : la première permettant de détecter les variations d'épaisseur d'oxyde des cellules mémoires ; la deuxième méthode permet de caractériser la programmation par pulsation (pulse programming) et ainsi prédire la valeur du champ électrique durant l'écriture d'une cellule<br>In recent years, non-volatile Flash memories have been widely used on system on chip. Their high integration density and complexity of manufacturing process make the Flash memory prone to defects. The defects in the memory are one of the major issues. They could affect the performance, retention, endurance, and therefore the reliability of Flash memories. This thesis was focused on the analysis of failure mechanisms, the faulty behavior modeling and the development of solution in order to improve the testing of Flash memories. In this work, we have proposed an electrical SPICE model of an ATMEL Flash memory. Compared with the state of art, the proposed model allows to simulate the static and dynamic behavior of the memory. This model is used to perform defect injection simulations affecting the Flash memories. These simulations are able to predict faulty behavior by fault modeling. Other types of electrical simulations highlight two characterization methods. The first one is able to detect the oxide thickness variations of the memory cells; the second one allows to characterize the programming pulse and then predict the electric field value during the programming of the cell

Confiabilidade é um parâmetro de projeto importante para aplicações criticas tanto na Terra como também no espaço. Os FPGAs baseados em memoria SRAM são atrativos para implementar aplicações criticas devido a seu alto desempenho e flexibilidade. No entanto, estes FPGAs são susceptíveis aos efeitos da radiação tais como os erros transientes na memoria de configuração. Além disso, outros efeitos como o envelhecimento (aging) ou escalonamento da tensão de alimentação (voltage scaling) incrementam a sensibilidade à radiação dos FPGAs. Nossos resultados experimentais mostram que o envelhecimento e o escalonamento da tensão de alimentação podem aumentar ao menos duas vezes a susceptibilidade de FPGAs baseados em SRAM a erros transientes. Estes resultados são inovadores porque estes combinam três efeitos reais que acontecem em FPGAs baseados em SRAM. Os resultados podem guiar aos projetistas a prever os efeitos dos erros transientes durante o tempo de operação do dispositivo em diferentes níveis de tensão. A correção da memoria usando a técnica de scrubbing é um método efetivo para corrigir erros transientes em memorias SRAM, mas este método impõe custos adicionais em termos de área e consumo de energia. Neste trabalho, nos propomos uma nova técnica de scrubbing usando a redundância interna a nível de quadros chamada FLR- scrubbing. Esta técnica possui mínimo consumo de energia sem comprometer a capacidade de correção. Como estudo de caso, a técnica foi implementada em um FPGA de tamanho médio Xilinx Virtex-5, ocupando 8% dos recursos disponíveis e consumindo seis vezes menos energia que um circuito corretor tradicional chamado blind scrubber. Além, a técnica proposta reduz o tempo de reparação porque evita o uso de uma memoria externa como referencia. E como outra contribuição deste trabalho, nos apresentamos os detalhes de uma plataforma de injeção de falhas múltiplas que permite emular os erros transientes na memoria de configuração do FPGA usando reconfiguração parcial dinâmica. Resultados de campanhas de injeção são apresentados e comparados com experimentos de radiação acelerada. Finalmente, usando a plataforma de injeção de falhas proposta, nos conseguimos analisar a efetividade da técnica FLR-scrubbing. Nos também confirmamos estes resultados com experimentos de radiação acelerada.<br>Reliability is an important design constraint for critical applications at ground-level and aerospace. SRAM-based FPGAs are attractive for critical applications due to their high performance and flexibility. However, they are susceptible to radiation effects such as soft errors in the configuration memory. Furthermore, the effects of aging and voltage scaling increment the sensitivity of SRAM-based FPGAs to soft errors. Experimental results show that aging and voltage scaling can increase at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These findings are innovative because they combine three real effects that occur in SRAM-based FPGAs. Results can guide designers to predict soft error effects during the lifetime of devices operating at different power supply voltages. Memory scrubbing is an effective method to correct soft errors in SRAM memories, but it imposes an overhead in terms of silicon area and energy consumption. In this work, it is proposed a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLRscrubbing) with minimum energy consumption overhead without compromising the correction capabilities. As a case study, the FLR-scrubbing controller was implemented on a mid-size Xilinx Virtex-5 FPGA device, occupying 8% of available slices and consumes six times less energy per scrubbed frame than a classic blind scrubber. Also, the technique reduces the repair time by avoiding the use of an external golden memory for reference. As another contribution, this work presents the details of a Multiple Fault Injection Platform that emulates the configuration memory upsets of an FPGA using dynamic partial reconfiguration. Results of fault injection campaigns are presented and compared with accelerated ground-level radiation experiments. Finally, using our proposed fault injection platform it was possible to analyze the effectiveness of the FLR-scrubbing technique. Accelerated radiation tests confirmed these results.

This thesis describes design and implementation of effective memory management for multi-threaded applications. At first, the virtual memory possibilities are described, which can be found in the latest operating systems, such as Microsoft Windows and Linux. Afterwards the most frequently used algorithms for memory management are explained. Consequently, their features are used properly for a new memory manager. Final design includes particular tools for application debugging and profiling. At the end of the thesis a series of tests and evaluation of achieved results were done.

Une classe d'attaque par canal auxiliaire particulièrement efficace est celle des attaques caches, qui exploitent une différence de temps entre les mémoires caches et la mémoire principale, qui sont considérées dans cette thèse d'un point de vue cryptographique. Un des objectifs de cette thèse est alors de mieux comprendre ces attaques. D'un autre côté, l'attaque Rowhammer est une attaque par faute qui induit des perturbations dans les condensateurs des modules DRAM dans le but de créer des erreurs appelées aussi fautes qui sont aussi considérées dans cette thèse d'un point de vue cryptographique. Cette thèse explore différentes fonctionnalités micro-architecturales en relation avec les attaques temporelles utilisant les mémoires caches et des attaques par fautes proches de l'attaque Rowhammer. Par la suite, cette thèse est ensuite divisée en deux parties.La première partie porte sur les attaques temporelles utilisant les mémoires caches. Cette partie décrit aussi les fonctionnalités matérielles et logicielles devant être considérées pour effectuer des mesures de temps précis. Ces fonctionnalités ont été utilisées pour améliorer une attaque existante. Un résultat de cette thèse fournit le lien entre des techniques générales d'attaques sur les mémoires caches et l'exploitation d'une vulnérabilité en détaillant une méthode de recherche de vulnérabilités dans un fichier binaire grâce à l'analyse dynamique. Dans la seconde partie de cette thèse, les attaques par fautes proches de l'attaque Rowhammer seront étudiées. Une méthode d'analyse logicielle est proposée. Finalement, une étude et une amélioration d'une attaque connue sous le nom de fautes persistantes sont proposées. Cette thèse se concentre essentiellement sur les améliorations d'attaques existantes et sur de nouvelles approches pour effectuer des analyses d'attaques temporelles utilisant les mémoires caches et des analyses des attaques en lien avec l'attaque Rowhammer dans l'objectif de répondre à un besoin réel des industriels de protéger leurs produits de ces attaques<br>A particularly efficient attack class is the class of cache timing attacks, that exploit the difference of time between cache memories and main memory, and are considered in this thesis with a cryptographic point of view. One aim of this thesis is to understand better such attacks.In other hand, the Rowhammer attack that induces perturbations in the capacitors of the DRAM modules in order to create an error called a fault that are also considered in this thesis with a cryptographic point of view.This thesis explores different microarchitectures features before exploring cache timing attacks and fault attack with the Rowhammer attack in mind. Based on the knowledge about these features, the thesis is split in two parts.The first part is about cache timing attacks. It gathers useful hardware and software features that should be considered to perform precise timing measurements. Those considerations were used to improve an existing attack on ECDSA on a known vulnerability.One result of this thesis will fill the gap between the general techniques used for the attacks and the exploitation of a vulnerability by searching such vulnerability in a binary by using dynamic analysis.In the second part of this thesis, fault attacks closed of the Rowhammer attack are considered. Like the first part, a way to perform software analysis is given.Eventually, in the second part a result about a so called persistent fault attack is improved.This thesis mainly focuses on improving existing attacks and on new ways to perform software analysis of cache timing attacks and attacks related to the Rowhammer attack in order to fill the needs of manufacturers to protect theirs products against those attacks

This master's thesis deals with design and implementation of educational application forpaging. Goal of the application is to help students understand and practice some conceptsfrom paging. It will allow students to write parts of these concepts and see how their codework on visualization of simulation of memory system. Application will be implemented asa web application in HTML, CSS and JavaScript. Server, which will be taking care ofcompiling of user code will be a desktop application. This thesis mainly describes pagingand technologies which will be used for this thesis and application design. It also describesimplementations and testing of this work.

This Master‘s thesis is focused on theoretical study of twinning in magnetic shape memory alloys based on Ni2MnGa using ab initio calculations of electronic structure within the projector augmented wave method. In particular, the effect of increasing concentration of manganese at the expense of gallium was studied on total energy and stress profiles along different deformation paths in the (10-1)[101] shear system of non-modulated martensite. Further, this work deals with the effect of the concentration of manganese on the energy of planar fault caused by presence of partial dislocation due to motion of twin boundary. The results show that the shear modulus in studied shear system increases with the increasing concentration of manganese as well as energy barrier and deformation characteristics along shear deformation paths increases, which makes the shear more difficult in Mn-rich alloys. Increasing concentration of manganese also leads to rising the planar fault energy. All these effects can be responsible for lower mobility of twin boundaries in alloys with higher concentration of manganese.

Le rayonnement est défini comme l'émission ou la transmission d'énergie sous forme d'ondes ou de particules, qui peuvent être ionisantes ou non ionisantes. L'interaction entre le rayonnement et la matière peut générer différentes réactions, qui peuvent varier en fonction des propriétés de la particule (type, énergie cinétique, masse et charge) et de la matière ciblée (semi-conducteurs dans le cadre de cette thèse). L'exposition de composants électroniques à des environnements avec une présence significative de rayonnement peut conduire à ce type d'interaction et, par conséquent, à une variété d'effets qui peuvent affecter considérablement la fiabilité des systèmes électroniques.Lors de la conception de dispositifs et de systèmes électroniques, la prise en compte des effets des rayonnements est fondamentale pour les applications dans des environnements hostiles. Par exemple, dans les systèmes avioniques et spatiaux, ces effets sont largement étudiés pour garantir la haute fiabilité des composants et fournir les informations nécessaires pour les décisions de conception. Les préoccupations liées aux rayonnements ont commencé à être prises en compte au début de l'ère spatiale.Les rayonnements ionisants peuvent induire des effets dans différents dispositifs, et plusieurs travaux ont montré que les mémoires électroniques sont l'une des principales causes d’erreur dans les systèmes. De plus, en raison de leur nature, les mémoires ont la capacité intrinsèque de stocker la trace des fautes induites par les rayonnements, comme le Single-Bit Upset (SBU), ce qui fait de ces dispositifs le meilleur candidat pour étudier les événements singuliers.Le premier sujet introduit par la thèse est une étude sur les effets induits par les ions lourds sur une mémoire Flash de type NAND. Cette étude est basée sur plusieurs campagnes d'irradiation avec une large gamme d'énergies. Les résultats ont révélé différents mécanismes de défaillance, notamment des SBUs, des petits groupes d'erreurs, des fautes dans le registre et des fautes affectant une ou plusieurs colonnes de la mémoire. La section efficace a été calculée pour chaque type de faute, et leurs causes ont été discutées.Ensuite, une étude sur les effets de la radiation neutronique (spectres thermiques et atmosphériques) sur une DRAM auto-rafraîchissante est présentée. Des méthodes de test statique et dynamique ont été utilisées pour définir la réponse du dispositif sous faisceau neutronique. Dans ce manuscrit, les résultats expérimentaux de deux campagnes de tests sont présentés, avec l'identification de différents modèles de faute, comme les SBUs, bits collés et blocs d’erreurs. Ces fautes ont été étudiées et caractérisées avec le calcule de la section efficace, du taux d'erreurs et l’étude des bitmaps. Une analyse du temps de rétention des cellules affectées a été réalisée, montrant une différence d’efficacité entre le mécanisme d'autorafraîchissement et une véritable opération de lecture. De plus, une corrélation du mécanisme de défaillance qui génère à la fois des SBUs et des bits collés est également proposée. Finalement, les effets de réparation du recuit à haute température ont été étudiés dans des tests post irradiation.Après, ce manuscrit présente aussi une étude comparative sur les effets induits par les neutrons sur les SDRAM produites avec trois nœuds technologiques différents. Les résultats ont révélé la présence de SBUs et de bits collés dans les mémoires, montrant une sensibilité plus élevée pour la génération la plus ancienne et des résultats similaires pour les deux autres modèles étudiés.Enfin, une procédure est présentée afin d’évaluer la fiabilité des applications basées sur réseau de neurones convolutifs (CNN). Dans cette optique, cette étude propose d'utiliser des modèles de défauts réalistes extraits des tests de rayonnement comme entrée pour un émulateur logiciel qui effectue l'injection de défauts dans le système informatique dans lequel le CNN est implémenté<br>Radiation is defined as the emission or transmission of energy as waves or particles, which can be either ionizing or non-ionizing. The interaction between the radiation and the matter can generate different reactions, which may vary depending on the properties of the particle (type, kinetic energy, mass, and charge), and the target (semiconductors in this thesis scope). The exposition of electronics components to environments with a significant presence of radiation may lead to this kind of interaction and, consequently, to a variety of effects that can drastically affect the reliability of electronic systems.When designing electronic devices and systems, considering radiation effects is fundamental for applications in harsh environments. For instance, in avionics and space systems, these effects are extensively studied to ensure the high reliability of the components and provide the needed insight for design decisions. The concerns related to radiation started to be noted at the beginning of the space era.Ionizing radiation may induce effects in different types of devices, and many works have shown that memories are one of the highest contributors to soft errors in systems. Furthermore, due to their nature, memories have the intrinsic capability of storing radiation-induced fault tracks, e.g., Single-Bit Upsets (SBUs), making these devices the best candidate for studying soft errors.The first topic introduced by the thesis is a study on the heavy-ion induced effects on a Single-Level Cell NAND Flash. This study is based on several irradiation test campaigns with a wide range of heavy-ions energies. The results revealed different failure mechanisms, including Single-Event Upsets, small clusters of errors, data register upsets, and a column-wise failure mode. Cross section was calculated for each of these failure modes, and their causes were discussed.Then, a study on the effects of neutron irradiation (thermal and atmospheric-like spectra) on a self-refresh DRAM is presented. Static and dynamic test methods were used to define the response of the device under irradiation. In this manuscript, experimental results from two different test campaigns are presented, with the identification of SBUs, stuck bits, and block errors. These faults were investigated and characterized by event cross section, soft-error rates, and bitmaps evaluations. An analysis of the damaged cells' retention time was performed, showing a difference between the self-refresh mechanism and a read operation. Additionally, a correlation of the fault mechanism that generates both SBUs and stuck bits under neutron irradiation is also proposed. Furthermore, high-temperature annealing was studied in post-radiation tests.Following, this thesis presents a comparative study on the neutron-induced effects on SDRAMs produced with three different technology nodes. The results revealed the occurrence of SBUs and stuck-bits in the memories, showing higher sensitivity for the oldest generation and similar results for the other two models.Finally, a framework is presented to assess the reliability of Convolutional Neural Network (CNN) applications. In this light, this study proposes using realistic fault models retrieved from radiation tests as input for a software emulator that performs fault injection in the computing system in which the CNN is implemented

L'elaborato di tesi, argomenta il problema degli errori transitori nell'array di memoria ReRAM, in cui i driver sono colpiti da particelle energetiche. Viene messo in evidenza l'aumento di suscettibilità a questi errori, proporzionale all'aging dei driver. Sono mostrate simulazioni, in cui sono quantificati gli upset avvenuti nelle celle di memoria.

La fiabilite des systemes spatiaux est difficile a assurer lorsqu'il s'agit de prendre en compte les effets de la radiation. Plusieurs consequences sont possibles quand un circuit integre (ci) est expose a la radiation ionisante, toutefois aucune d'elles n'est particulierement desirable. Les effets commencent par une lente et implacable degradation de la performance du circuit, allant de la generation spontanee des erreurs fonctionnelles jusqu'au claquage total du circuit. En plus des effets de la radiation ionisante, il est aussi a present reconnu par la communaute internationale que les aleas (single event upsets - seus) representent une autre menace potentielle a la fiabilite des cis dans les environnements spatiaux. Ce sujet est d'importance considerable aujourd'hui, car au fur et a mesure que les technologies de cis atteignent des dimensions sousmicroniques, les effets des rayons cosmiques ont tendance a generer de plus en plus de seu sur les memoires des systemes electroniques. D'autre part, le test par courant a montre son efficacite en detectant des fautes difficilement decelables par le test logique conventionnel. Le test par courant peut donc ameliorer sensiblement la qualite et reduire le cout de production des cis cmos. Dans ce but, cette these presente une approche qui estime le courant de repos (i#d#d#q) en se basant sur des parametres de qualite comme l'immunite au bruit ainsi que la vitesse du ci. En sachant que la radiation ionisante degrade ces deux parametres des cis cmos, cette approche est ainsi tres appropriee pour ameliorer la qualite du test de fabrication du produit qui sera utilise dans des applications spatiales. Cette these presente egalement deux approches qui ont pour but la conception des systemes electroniques tolerants aux effets de la radiation. La premiere approche permet la conception de circuits tolerants aux effets de la dose totale, tandis que la deuxieme approche permet la conception de memoires cmos sram tolerantes aux aleas. Ces deux approches sont basees sur la combinaison de test par courant, realise par des capteurs de courant sur silicium, et de techniques de redondance au niveau materiel

碩士<br>東海大學<br>美術學系<br>106<br>The establishment of a home is filled with memories of loved ones and builds the most important fortress for adult students with accumulated feelings. The grandmother’s family is full of my childhood's happy hours and my childhood's curious footprints. Every corner has its own footprint. Different memories. My hometown has experienced many storms, earthquakes, and earth-rock flows. The homeland map has already been rewritten, and it has been destroyed and rebuilt. Although it lost its original appearance, the original scenery was still vivid when walking in the pastoral area. When we grew up, we followed our dreams, and the gathering time was getting less and less. The updated home still continued to talk about the family's story. When we had a sweet childhood dream, we were also confused with the fear of the wind disaster. Land has created more worries and pity. This creation will depict the appearance of the home to the heart. All the worries of the child's steps and the current situation will be analyzed like an earthquake fault, and the memory will be layered like a layer. Adhering to the homeland's heart, it has repeatedly faced the challenges of various natural disasters and cherished every time of peaceful reunion. All the feelings are conveyed through paintings to record and analyze the story of the family and the inner memory of the mood. The theme of "hometown" is to expound the research concept of the paper, consider the memories buried in the heart, add the real scene elements as the motives of creation, and confirm the representative meaning and metaphorical expression of various images in paintings.

碩士<br>國立清華大學<br>電機工程學系<br>92<br>Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded Flash memories are growing rapidly as we enter the system-on-chip (SoC) era. Conventional fault models and tests for Flash memories are usually ad hoc, and the test procedure is developed for a specific design. We propose a set of disturb fault models that are derived from the IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays. We also propose improved March-like algorithms (i.e., March-FT) for both bit-oriented and word-oriented Flash memories to cover the disturbance faults as well as conventional faults. Besides, a novel Flash memory fault simulator (called RAMSES-FT) is developed to analyze the fault coverage of the test algorithms. The fault simulator is a key component for the test pattern generation tool TAGS, which produces a test to target the fault set that the user specifies. Based on March-FT, we have designed a built-in self-test (BIST) circuit which is suitable for both the commodity Flash memory and embedded Flash core. Finally, we present the BIST designs for two industrial Flash memories, and show the area overhead that is only about 3% for a medium-sized Flash memory.

博士<br>國立清華大學<br>電機工程學系<br>95<br>With the increase in size and capacity of flash memory, long test times on complicated automatic test equipment (ATE) are now commonly seen. The test-consuming diagnosis process for ATEs results in high test cost and slow time-to-volume; thus, efficient diagnosis of flash memory has recently become a critical issue. Based on our previous work, which developed a set of disturb fault models using a systematic approach and improved March-like algorithms for both bit-oriented and word-oriented flash memory, in this work we propose cost-effective diagnostics for flash memory. The diagnosis methodology efficiently distinguishes the fault types of faulty cell from the fail bit-maps by comparing the fault signature with the fault dictionary and the fault bit-maps provide detailed diagnosis information for yield and reliability improvement. We also propose a built-in self-diagnosis (BISD) scheme that collects useful test information for off-chip diagnosis analysis and contains a unique test mode control that reduces test time and diagnostic data shift-out cycles by using a parallel shift-out mechanism. Additionally, test time is also greatly reduced by accessing the engineering test mode to do parallel programming and parallel erasing. Finally, we show a configurable diagnostics system for low-cost test and diagnosis environment. Experiments were done using industrial flash products to justify the effectiveness of our low-cost configurable diagnostics system and the efficiency using March-like test algorithm in the test flow. Furthermore, a systematic approach to minimize themass production test time by analyzing and rearranging the test items in the test flow is also presented in this work. We propose three test time reduction (TTR) techniques and implement an automatic TTR tool based on these techniques to identify redundant test items, suggest proper tests, and provide correlation between the test items. Experimental results show the TTR tool effectively reduces the test time of industrial memory mass production test flow; the results are on top of the original test flow that has been compacted by conventional way based on statistics.

碩士<br>國立清華大學<br>電機工程學系<br>91<br>Failure analysis (FA) and diagnosis of memory cores play a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on failure bitmaps and the experiences of the FA engineers is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. We propose a fault pattern oriented failure analysis methodology based on failure patterns and functional fault models of semiconductor memories. Based on the proposed approach, we developed a systematic memory failure analysis framework ---the Failure Analyzer for MEmories (FAME). FAME integrates the Memory Error Catch and Analysis (MECA) system and Memory Defect Diagnostics (MDD) system. The fault-type based diagnostics approach used by MECA can improve the efficiency of the test and diagnostic algorithms. The fault-pattern based diagnostics approach used by MDD further improves the defect identification capability. FAME also comes with a Fault/failure pattern viewer for inspecting the failure patterns and fault patterns. Our proposed approach provides an efficient way to automatically narrow down the potential causes of failures and identify suspect defects more accurately. Defect diagnostics and FA can be accelerated during the memory product and yield improvement stage. Furthermore, an experiment has been done on an industrial case, demonstrating very precise results in a much shorter time as compared with the conventional way.

碩士<br>國立臺灣大學<br>資訊工程學研究所<br>97<br>As flash memory gains its momentum in the storage market of embedded systems, existing fault detection algorithms face serious challenges due to the special characteristics of NAND flash memory and the rapid degradation of its reliability. This research proposes efficient fault detection algorithms to detect the faults of NAND flash memory in a systematic way. A sampling policy with a write parallelization strategy is also proposed to further enhance the efficiency of the fault detection algorithms. The sampling policy is later evaluated based on selected fault distribution models to show its effectiveness and efficiency on the fault detection of NAND flash memory.