To see the other types of publications on this topic, follow the link: Memory fault.
Journal articles on the topic 'Memory fault'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 journal articles for your research on the topic 'Memory fault.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.
1
Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (2022): 971. http://dx.doi.org/10.3390/mi13060971.
Full textAbstract:
Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.
2
Park, Pangun, Piergiuseppe Di Marco, Hyejeon Shin, and Junseong Bang. "Fault Detection and Diagnosis Using Combined Autoencoder and Long Short-Term Memory Network." Sensors 19, no. 21 (2019): 4612. http://dx.doi.org/10.3390/s19214612.
Full textAbstract:
Fault detection and diagnosis is one of the most critical components of preventing accidents and ensuring the system safety of industrial processes. In this paper, we propose an integrated learning approach for jointly achieving fault detection and fault diagnosis of rare events in multivariate time series data. The proposed approach combines an autoencoder to detect a rare fault event and a long short-term memory (LSTM) network to classify different types of faults. The autoencoder is trained with offline normal data, which is then used as the anomaly detection. The predicted faulty data, captured by autoencoder, are put into the LSTM network to identify the types of faults. It basically combines the strong low-dimensional nonlinear representations of the autoencoder for the rare event detection and the strong time series learning ability of LSTM for the fault diagnosis. The proposed approach is compared with a deep convolutional neural network approach for fault detection and identification on the Tennessee Eastman process. Experimental results show that the combined approach accurately detects deviations from normal behaviour and identifies the types of faults within the useful time.
3
Mrozek, Ireneusz, and Vyacheslav N. Yarmolik. "Linked Coupling Faults Detection by Multirun March Tests." Applied Sciences 14, no. 6 (2024): 2501. http://dx.doi.org/10.3390/app14062501.
Full textAbstract:
This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in relation to each other. The memory march test and applied address sequence and background determine the scenario for implementing the roles of memory faulty cells. The necessary and sufficient conditions for detecting linked coupling faults are given based on a new formal model. Formally, the undetectable linked coupling faults are defined, and the conditions for their detection are formulated using multirun memory march tests. The experimental investigation confirmed the validity of the proposed formulated statements. Based on the example of a linked coupling fault, this study demonstrates the fulfillment of the necessary and sufficient conditions for its detection using a single march test. As demonstrated in this article, employing the approach proposed by the authors, a two-pass march C test, for instance, enables the attainment of 55.42% fault coverage for linked coupling faults, inclusive of undetectable faults identified by the single-pass march test.
4
Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.
Full textAbstract:
This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distributed RAM mode of the memory block, the TPG based on FSM is designed to provide March C-testing patterns. Besides, the comparator-based output response analyzer (ORA) and the cascaded ORA scan chain are used to locate the faulty CLB and propagate the comparison output in every row. Finally, fault-injection experiment results verify its ability to detect and diagnose multiple faulty CLBs in faulty FPGAs.
5
Swamy S., Kendaganna, Rajasree P. M., Anand M. Sharma, and Jnanaprakash J. Naik. "A Review Paper on Memory Fault Models and its Algorithms." International Journal of Electrical Engineering and Computer Science 6 (October 7, 2024): 143–51. http://dx.doi.org/10.37394/232027.2024.6.17.
Full textAbstract:
The significance of testing semiconductor memories has grown significantly in the semiconductor industry due to the increased density of modern memory chips. This paper aims to investigate and analyze different types of functional faults present in today's memory technology. These faults include stuck-at faults, transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on the importance of zero-one, checkerboard, and March pattern tests, which are widely employed to assess functional memory defects at different levels, such as the chip level, array level, and board level. Furthermore, the study provides an in-depth exploration of various test algorithms and thoroughly examines their fault coverage capabilities. Overall, this review paper provides valuable insights into the challenges posed by the dense nature of modern memory chips and offers a comprehensive analysis of functional faults in memory technology. By emphasizing the importance of testing and presenting a detailed exploration of fault detection methods and test algorithms, this study contributes to the advancement of reliable and high-performance memory devices in the electronic industry suggesting that MARCH algorithms outperform others when considering factors like fault coverage, power efficiency, area optimization, and time complexity parameters, making them the preferable choice for reliable and high-performance memory devices in the electronic industry.
6
Lakshmi A, Sowjanya, and Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.
Full textAbstract:
Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while minimizing useless and forced checkpoints. Long short-term memory (LSTM) based deep learning algorithm is used in our approach to predict fault occurrences and strategically place checkpoints. The proposed method also in turn improve system reliability and performance. Experimental results demonstrate the effectiveness of proposed CIC-FTM in IoT environment by minimizing the practicable operating time for checkpointing and back propagation, compared to traditional fault-tolerance mechanisms.
7
Sowjanya, Lakshmi A. Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785–96. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.
Full textAbstract:
Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while minimizing useless and forced checkpoints. Long short-term memory (LSTM) based deep learning algorithm is used in our approach to predict fault occurrences and strategically place checkpoints. The proposed method also in turn improve system reliability and performance. Experimental results demonstrate the effectiveness of proposed CIC-FTM in IoT environment by minimizing the practicable operating time for checkpointing and back propagation, compared to traditional fault-tolerance mechanisms.
8
Vandris, Evstratios, and Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits." VLSI Design 4, no. 3 (1996): 217–29. http://dx.doi.org/10.1155/1996/34084.
Full textAbstract:
A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.
9
Lee, Jeong-Geun, Deok-Hwan Kim, and Jang Hyun Lee. "Proactive Fault Diagnosis of a Radiator: A Combination of Gaussian Mixture Model and LSTM Autoencoder." Sensors 23, no. 21 (2023): 8688. http://dx.doi.org/10.3390/s23218688.
Full textAbstract:
Radiator reliability is crucial in environments characterized by high temperatures and friction, where prompt interventions are often required to prevent system failures. This study introduces a proactive approach to radiator fault diagnosis, leveraging the integration of the Gaussian Mixture Model and Long-Short Term Memory autoencoders. Vibration signals from radiators were systematically collected through randomized durability vibration bench tests, resulting in four operating states—two normal, one unknown, and one faulty. Time-domain statistical features of these signals were extracted and subjected to Principal Component Analysis to facilitate efficient data interpretation. Subsequently, this study discusses the comparative effectiveness of the Gaussian Mixture Model and Long Short-Term Memory in fault detection. Gaussian Mixture Models are deployed for initial fault classification, leveraging their clustering capabilities, while Long-Short Term Memory autoencoders excel in capturing time-dependent sequences, facilitating advanced anomaly detection for previously unencountered faults. This alignment offers a potent and adaptable solution for radiator fault diagnosis, particularly in challenging high-temperature or high-friction environments. Consequently, the proposed methodology not only provides a robust framework for early-stage fault diagnosis but also effectively balances diagnostic capabilities during operation. Additionally, this study presents the foundation for advancing reliability life assessment in accelerated life testing, achieved through dynamic threshold adjustments using both the absolute log-likelihood distribution of the Gaussian Mixture Model and the reconstruction error distribution of the Long-Short Term Memory autoencoder model.
10
Mrozek, Ireneusz. "Analysis of multibackground memory testing techniques." International Journal of Applied Mathematics and Computer Science 20, no. 1 (2010): 191–205. http://dx.doi.org/10.2478/v10006-010-0014-6.
Full textAbstract:
Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.
11
Saied, Majd, Abbas Mishi, Clovis Francis, and Ziad Noun. "A Deep Learning Approach for Fault-Tolerant Data Fusion Applied to UAV Position and Orientation Estimation." Electronics 13, no. 16 (2024): 3342. http://dx.doi.org/10.3390/electronics13163342.
Full textAbstract:
This work introduces a novel fault-tolerance technique for data fusion in Unmanned Aerial Vehicles (UAVs), designed to address sensor faults through a deep learning-based framework. Unlike traditional methods that rely on hardware redundancy, our approach leverages Long Short-Term Memory (LSTM) networks for state estimation and a moving average (MA) algorithm for fault detection. The novelty of our technique lies in its dual strategy: utilizing LSTMs to analyze residuals and detect errors, while the MA algorithm identifies faulty sensors by monitoring variations in sensor data. This method allows for effective error correction and system recovery by replacing faulty measurements with reliable ones, eliminating the need for a fault-free prediction model. The approach has been validated through offline testing on real sensor data from a hexarotor UAV with simulated faults, demonstrating its efficacy in maintaining robust UAV operations without resorting to redundant hardware solutions.
12
Wang, Zhifu, Wei Luo, Song Xu, et al. "Electric Vehicle Lithium-Ion Battery Fault Diagnosis Based on Multi-Method Fusion of Big Data." Sustainability 15, no. 2 (2023): 1120. http://dx.doi.org/10.3390/su15021120.
Full textAbstract:
Power batteries are the core of electric vehicles, but minor faults can easily cause accidents; therefore, fault diagnosis of the batteries is very important. In order to improve the practicality of battery fault diagnosis methods, a fault diagnosis method for lithium-ion batteries in electric vehicles based on multi-method fusion of big data is proposed. Firstly, the anomalies are removed and early fault analysis is performed by t-distribution random neighborhood embedding (t-Sne) and wavelet transform denoising. Then, different features of the vehicle that have a large influence on the battery fault are identified by factor analysis , and the faulty features are extracted by a two-way long and short-term memory network method with convolutional neural network. Finally a self-learning Bayesian network is used to diagnose the battery fault. The results show that the method can improve the accuracy of fault diagnosis by about 12% when verified with data from different vehicles, and after comparing with other methods, the method not only has higher fault diagnosis accuracy, but also reduces the response time of fault diagnosis, and shows superiority compared to graded faults, which is more in line with the practical application of engineering.
13
Gmati, Badii, Amine Ben Rhouma, Houda Meddeb, and Sejir Khojet El Khil. "Diagnosis of Multiple Open-Circuit Faults in Three-Phase Induction Machine Drive Systems Based on Bidirectional Long Short-Term Memory Algorithm." World Electric Vehicle Journal 15, no. 2 (2024): 53. http://dx.doi.org/10.3390/wevj15020053.
Full textAbstract:
Availability and continuous operation under critical conditions are very important in electric machine drive systems. Such systems may suffer from several types of failures that affect the electric machine or the associated voltage source inverter. Therefore, fault diagnosis and fault tolerance are highly required. This paper presents a new robust deep learning-based approach to diagnose multiple open-circuit faults in three-phase, two-level voltage source inverters for induction-motor drive applications. The proposed approach uses fault-diagnosis variables obtained from the sigmoid transformation of the motor stator currents. The open-circuit fault-diagnosis variables are then introduced to a bidirectional long short-term memory algorithm to detect the faulty switch(es). Several simulation and experimental results are presented to show the proposed fault-diagnosis algorithm’s effectiveness and robustness.
14
Amin, Mohsin, Abbas Ramazani, Fabrice Monteiro, Camille Diou, and Abbas Dandache. "A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture." International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/962062.
Full textAbstract:
We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is to prevent data not yet validated to be sent to the main memory, and allow to fast rollback execution on faulty situations. The main memory, supposed to be fault secure in our model, only contains valid (uncorrupted) data obtained from fault-free computations. Error control coding techniques are used both in the processor core to detect errors and in the HW journal to protect the temporarily stored data from possible changes induced by transient faults. Implementation results on an FPGA of the Altera Stratix-II family show clearly the relevance of the approach, both in terms of performance/area tradeoff and fault tolerance effectiveness, even for high error rates.
15
Tao, Xinxin, Yingqing Guo, Wanli Zhao, Qifan Zhou, and Kejie Xu. "Fault detection and isolation of electromechanical actuator based on SAE-BiLSTM." Journal of Physics: Conference Series 2472, no. 1 (2023): 012031. http://dx.doi.org/10.1088/1742-6596/2472/1/012031.
Full textAbstract:
Abstract The control technology of electromechanical actuator(EMA) and its fault diagnosis is one of the key problems of multi-electric aircraft study. The method based on deep learning is used to diagnose and isolate the classic faults of EMA. The simulation model of EMA is modeling according to the working principle and control law. Four typical faults of EMA are studied,including return channel jam, spall, motor fault, and position sensor fault. Sparse Auto Encoder (SAE) algorithm can perform adaptive extraction of sensor data, which preserves dimensionality reduction and compression while preserving important features. Bidirectional Long Short Term Memory (BiLSTM) neural network is used to effectively process the time series data, which considering both past and future data during the fault diagnosis process. The established EMA model is simulated to obtain normal and faulty data sets, which are used to train the network by SAE-BiLSTM algorithm, and then the trained network is used for online fault diagnosis. After the experiment, SAE-BiLSTM algorithm can well complete the EMA fault detection and isolation.
16
Truong, Nhu, Anthony De Souza-Daw, Robert Ross, Thang Manh Hoang, and Tien Dzung Nguyen. "SELF-HEALING MEMORY HARDWARE ARCHITECTURE ON FIELD PROGRAMMABLE GATE ARRAY." ASEAN Engineering Journal 5, no. 1 (2014): 39–55. http://dx.doi.org/10.11113/aej.v5.15454.
Full textAbstract:
Hardware Fault-Tolerance is the set of techniques to remain operational after a fault by design. Programmable Logic Devices are good platforms to implement Hardware Fault-Tolerant techniques by utilizing abundant resources and facilitating self healing operations. In this paper we propose a hardware fault-tolerant architecture to duplicate components in order to replace faulty ones. The proposed architecture is markedly different from other works that mostly focuses on reconfiguring and evolving logic units rather than our evolvable memory units. The self-reparation process for a memory failure is the reallocation and synchronization of memory content. The internal flip-flops form an abundant reconfigurable resource and are reconfigured to work as newly created memory. The proposed architecture has been downloaded and tested on a real FPGA development board and has satisfied all of its pre-defined specifications.
17
Feng, Yi, Zhan Zhang, Jun Qian, De Cheng Zuo, and Xiao Zong Yang. "A Fault Injection Platform for Availability Evaluation of IA64 System." Applied Mechanics and Materials 58-60 (June 2011): 535–40. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.535.
Full textAbstract:
Availability is one of the key features for transaction processing systems. Fault injection is one of the important techniques to hasten availability tests. A fault injection platform is designed in this paper for IA64 system which is being widely used in transaction processing business. The fault injection platform is implemented using client/server mode and a series of fault injection tools are accomplished which covers CPU faults, memory faults, disk faults, IO faults, file system faults and system call boundary errors. A group of experiments on a typical IA64 server are described and performed, and the experiment results validate the effectiveness of the fault injection platform.
18
Debele, Yisak, Ha-Young Shi, Assefinew Wondosen, Tae-Wan Ku, and Beom-Soo Kang. "Deep Learning-Based Robust Actuator Fault Detection and Isolation Scheme for Highly Redundant Multirotor UAVs." Drones 7, no. 7 (2023): 437. http://dx.doi.org/10.3390/drones7070437.
Full textAbstract:
This article presents a novel approach for detecting and isolating faulty actuators in highly redundant Multirotor UAVs using cascaded Deep Neural Network (DNN) models. The proposed Fault Detection and Isolation (FDI) framework combines Long Short-Term Memory (LSTM)-based fault detection and faulty actuator locator models to achieve real-time monitoring. The study focuses on a Hexadecarotor multirotor UAV equipped with sixteen rotors. To tackle the complexity of FDI resulting from redundancy, a partitioning technique is introduced based on system dynamics. The proposed FDI scheme is composed of a region classifier model responsible for detecting faults and fault locator models that precisely determine the location of the failed actuator. Extensive training and testing of the models demonstrate high accuracy, with the regional classifier model achieving 98.97% accuracy and the fault locator model achieving 99.107% accuracy. Furthermore, the scheme was integrated into the flight control system of the UAV, before being tested via both real-time monitoring in the simulation environment and analysis of recorded real flight data. The models exhibit remarkable performance in detecting and localizing injected faults. Therefore, using DNN models and the partitioning technique, this research offers a promising method for accurately detecting and isolating faulty actuators, thereby improving the overall performance and dependability of highly redundant Multirotor UAVs in various operational scenarios.
19
G., Kumara Swamy, and Preethi M. "A Performance Degradation Tolerance Way Tagged Cache." International Journal of Trend in Scientific Research and Development 2, no. 5 (2018): 1–5. https://doi.org/10.31142/ijtsrd15729.
Full textAbstract:
For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults so that the caches can still be marketable. In processors, caches are designed as Level 1 L1 , Level 2 L2 , and the least hard disk. If the processor wants the data from to memory it checks the availability of data in upper level cache L1 and if the data is found it sends to the processor. If the data is not found in L1, it checks in lower level cache L2 and next in L3 and at the least in slow memory or hard disk. So, in this process, many functional faults may exist which leads to making the processor faulty. So, to protect the cache memory ECC and BIST are used. For a cache redesign, a PDT cache is used where functional faults are converted into performance faults. We propose a new PDT way tagged cache design which leads to increased performance. This reduces fault rate with small hardware overhead by applying BIST or ECC method. Karkagari Anjali | G. Kumara Swamy | M. Preethi "A Performance Degradation Tolerance Way Tagged Cache" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-5 , August 2018, URL: https://www.ijtsrd.com/papers/ijtsrd15729.pdf
20
Muhammad Ejaz Sandhu. "Comparison of Fault Simulation Over Custom Kernel Module Using Various Techniques." Lahore Garrison University Research Journal of Computer Science and Information Technology 5, no. 3 (2021): 73–83. http://dx.doi.org/10.54692/lgurjcsit.2021.0503220.
Full textAbstract:
To test the behavior of the Linux kernel module, device drivers and file system in a faulty situation, scientists tried to inject faults in different artificial environments. Since the rarity and unpredictability of such events are pretty high, thus the localization and detection of Linux kernel, device drivers, file system modules errors become unfathomable. ‘Artificial introduction of some random faults during normal tests’ is the only known approach to such mystifying problems. A standard method for performing such experiments is to generate synthetic faults and study the effects. Various fault injection frameworks have been analyzed over the Linux kernel to simulate such detection. The following paper highlights the comparison of different approaches and techniques used for such fault injection to test Linux kernel modules that include simulating low resource conditions and detecting memory leaks. The frameworks chosen to be used in these experiments are; Linux Text Project (LTP), KEDR, Linux Fault-Injection (LFI), and SCSI.
21
Yang, Huibao, Bangshuai Li, Xiujing Gao, Bo Xiao, and Hongwu Huang. "Enhancing Fault Detection in AUV-Integrated Navigation Systems: Analytical Models and Deep Learning Methods." Journal of Marine Science and Engineering 13, no. 7 (2025): 1198. https://doi.org/10.3390/jmse13071198.
Full textAbstract:
In complex underwater environments, the stability of navigation for autonomous underwater vehicles (AUVs) is critical for mission success. To enhance the reliability of the AUV-integrated navigation system, fault detection technology was investigated. Initially, the causes and classifications of faults within the integrated navigation system were analyzed in detail, and these faults were categorized as either abrupt or gradual, based on variations in sensor output characteristics under fault conditions. To overcome the limitations of the residual chi-square method in detecting gradual faults, a cumulative residual detection approach with error coefficient amplification was proposed. The algorithm enhances gradual fault detection by using eigenvalue analysis and constructing fault-frequency-based error amplification coefficients with non-parametric techniques. Furthermore, to improve the detection of gradual faults, artificial intelligence-based fault detection methods were also explored. Specifically, the particle swarm optimization (PSO) algorithm was employed to optimize the hyperparameters of a long short-term memory (LSTM) neural network, leading to the development of a PSO-LSTM fault detection model. In this model, the fault detection function was formulated by comparing the predictions generated by the PSO-LSTM model with those derived from the Kalman filter. The experimental results demonstrated that the fault detection function formulated by PSO-LSTM exhibited enhanced sensitivity to gradual faults and enabled the timely isolation of faulty sensors. In unfamiliar marine regions, the PSO-LSTM method demonstrates greater stability and avoids the need to recalibrate detection thresholds for each sea area—an important advantage for AUV autonomous navigation in complex environments.
22
Yarmolik, V. N., V. A. Levantsevich, D. V. Demenkovets, and I. Mrozek. "Construction and application of march tests for pattern sensitive memory faults detection." Informatics 18, no. 1 (2021): 25–42. http://dx.doi.org/10.37661/1816-0301-2021-18-1-25-42.
Full textAbstract:
The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms of march test elements the conditions for activation and fault detection of PNPSFk of storage devices. Examples of march tests with maximum fault coverage, as well as march tests with a minimum time complexity equal to 18N are given. The efficiency of a single application of tests such as MATS ++, March C− and March PS is investigated for different number of k ≤ 9 memory cells involved in PNPSFk fault. The applicability of multiple testing with variable address sequences is substantiated, when the use of random sequences of addresses is proposed. Analytical expressions are given for the fault coverage of complex PNPSFk faults depending on the multiplicity of the test. In addition, the estimates of the mean value of the multiplicity of the MATS++, March C− and March PS tests, obtained on the basis of a mathematical model describing the problem of the coupon collector, and ensuring the detection of all k2k PNPSFk faults are given. The validity of analytical estimates is experimentally shown and the high efficiency of PNPSFk fault detection is confirmed by tests of the March PS type.
23
Trivedi, Mihir, Riya Kakkar, Rajesh Gupta, et al. "Blockchain and Deep Learning-Based Fault Detection Framework for Electric Vehicles." Mathematics 10, no. 19 (2022): 3626. http://dx.doi.org/10.3390/math10193626.
Full textAbstract:
The gradual transition from a traditional transportation system to an intelligent transportation system (ITS) has paved the way to preserve green environments in metro cities. Moreover, electric vehicles (EVs) seem to be beneficial choices for traveling purposes due to their low charging costs, low energy consumption, and reduced greenhouse gas emission. However, a single failure in an EV’s intrinsic components can worsen travel experiences due to poor charging infrastructure. As a result, we propose a deep learning and blockchain-based EV fault detection framework to identify various types of faults, such as air tire pressure, temperature, and battery faults in vehicles. Furthermore, we employed a 5G wireless network with an interplanetary file system (IPFS) protocol to execute the fault detection data transactions with high scalability and reliability for EVs. Initially, we utilized a convolutional neural network (CNN) and a long-short term memory (LSTM) model to deal with air tire pressure fault, anomaly detection for temperature fault, and battery fault detection for EVs to predict the presence of faulty data, which ensure safer journeys for users. Furthermore, the incorporated IPFS and blockchain network ensure highly secure, cost-efficient, and reliable EV fault detection. Finally, the performance evaluation for EV fault detection has been simulated, considering several performance metrics, such as accuracy, loss, and the state-of-health (SoH) prediction curve for various types of identified faults. The simulation results of EV fault detection have been estimated at an accuracy of 70% for air tire pressure fault, anomaly detection of the temperature fault, and battery fault detection, with R2 scores of 0.874 and 0.9375.
24
Gantel, Laurent, Quentin Berthet, Emna Amri, Alexandre Karlov, and Andres Upegui. "Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application." Electronics 10, no. 17 (2021): 2148. http://dx.doi.org/10.3390/electronics10172148.
Full textAbstract:
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.
25
Aguilera, Carlos J. G., Cristiano P. Chenet, and Tiago R. Balen. "Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation." Journal of Integrated Circuits and Systems 11, no. 3 (2016): 185–91. http://dx.doi.org/10.29292/jics.v11i3.443.
Full textAbstract:
This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.
26
Choi, Ki-Yong, and Jung-Won Lee. "CNN-Based Fault Localization Method Using Memory-Updated Patterns for Integration Test in an HiL Environment." Applied Sciences 9, no. 14 (2019): 2799. http://dx.doi.org/10.3390/app9142799.
Full textAbstract:
Automotive electronic components are tested via hardware-in-the-loop (HiL) testing at the unit and integration test stages, according to ISO 26262. It is difficult to obtain debugging information from the HiL test because the simulator runs a black-box test automatically, depending on the scenario in the test script. At this time, debugging information can be obtained in HiL tests, using memory-updated information, without the source code or the debugging tool. However, this method does not know when the fault occurred, and it is difficult to select the starting point of debugging if the execution flow of the software is not known. In this paper, we propose a fault-localization method using a pattern in which each memory address is updated in the HiL test. Via a sequential pattern-mining algorithm in the memory-updated information of the transferred unit tests, memory-updated patterns are extracted, and the system learns using a convolutional neural network. Applying the learned pattern in the memory-updated information of the integration test can determine the fault point from the normal pattern. The point of departure from the normal pattern is highlighted as a fault-occurrence time, and updated addresses are presented as fault candidates. We applied the proposed method to an HiL test of an OSEK/VDX-based electronic control unit. Through fault-injection testing, we could find the cause of faults by checking the average memory address of 3.28%, and we could present the point of fault occurrence with an average accuracy of 80%.
27
Xie, Jialing, Weifeng Shi, and Yuqi Shi. "Research on Fault Diagnosis of Six-Phase Propulsion Motor Drive Inverter for Marine Electric Propulsion System Based on Res-BiLSTM." Machines 10, no. 9 (2022): 736. http://dx.doi.org/10.3390/machines10090736.
Full textAbstract:
To ensure the implementation of the marine electric propulsion self-healing strategy after faults, it is necessary to diagnose and accurately classify the faults. Considering the characteristics of the residual network (ResNet) and bidirectional long short-term memory (BiLSTM), the Res-BiLSTM deep learning algorithm is used to establish a fault diagnosis model to distinguish the types of electric drive faults. First, the powerful fault feature extraction ability of the residual network is used to deeply mine the fault features in the signals. Then, perform time-series learning through a bidirectional long short-term memory network, and further excavate the transient time-series features in the fault features so as to achieve the accurate classification of drive inverter faults. The effectiveness of the method is verified using noise-free fault data, and the robustness of the method is verified using data with varying degrees of noise. The results show that compared with conventional deep learning algorithms, Res-BiLSTM has the fastest and most stable training process, the diagnostic performance is improved, and the accuracy can be maintained over 95% under 25–19 dB. It has certain robustness and can be applied to marine electric propulsion systems drive inverter fault diagnosis, and its results can provide data support for the implementation of self-healing control strategies.
28
Zhang, Shuo, Emma Robinson, and Malabika Basu. "Wind Turbine Predictive Fault Diagnostics Based on a Novel Long Short-Term Memory Model." Algorithms 16, no. 12 (2023): 546. http://dx.doi.org/10.3390/a16120546.
Full textAbstract:
The operation and maintenance (O&M) issues of offshore wind turbines (WTs) are more challenging because of the harsh operational environment and hard accessibility. As sudden component failures within WTs bring about durable downtimes and significant revenue losses, condition monitoring and predictive fault diagnostic approaches must be developed to detect faults before they occur, thus preventing durable downtimes and costly unplanned maintenance. Based primarily on supervisory control and data acquisition (SCADA) data, thirty-three weighty features from operational data are extracted, and eight specific faults are categorised for fault predictions from status information. By providing a model-agnostic vector representation for time, Time2Vec (T2V), into Long Short-Term Memory (LSTM), this paper develops a novel deep-learning neural network model, T2V-LSTM, conducting multi-level fault predictions. The classification steps allow fault diagnosis from 10 to 210 min prior to faults. The results show that T2V-LSTM can successfully predict over 84.97% of faults and outperform LSTM and other counterparts in both overall and individual fault predictions due to its topmost recall scores in most multistep-ahead cases performed. Thus, the proposed T2V-LSTM can correctly diagnose more faults and upgrade the predictive performances based on vanilla LSTM in terms of accuracy, recall scores, and F-scores.
29
Yarmolik, Svetlana. "Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests." International Journal of Applied Mathematics and Computer Science 18, no. 3 (2008): 329–39. http://dx.doi.org/10.2478/v10006-008-0030-y.
Full textAbstract:
Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March TestsIt is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.
30
Mrozek, Ireneusz, and Vyacheslav Yarmolik. "Two-Run RAM March Testing with Address Decimation." Journal of Circuits, Systems and Computers 26, no. 02 (2016): 1750031. http://dx.doi.org/10.1142/s0218126617500311.
Full textAbstract:
Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator.
31
Kim, Pyung Soo. "A Design of Finite Memory Residual Generation Filter for Sensor Fault Detection." Measurement Science Review 17, no. 2 (2017): 76–82. http://dx.doi.org/10.1515/msr-2017-0010.
Full textAbstract:
Abstract In the current paper, a residual generation filter with finite memory structure is proposed for sensor fault detection. The proposed finite memory residual generation filter provides the residual by real-time filtering of fault vector using only the most recent finite measurements and inputs on the window. It is shown that the residual given by the proposed residual generation filter provides the exact fault for noisefree systems. The proposed residual generation filter is specified to the digital filter structure for the amenability to hardware implementation. Finally, to illustrate the capability of the proposed residual generation filter, extensive simulations are performed for the discretized DC motor system with two types of sensor faults, incipient soft bias-type fault and abrupt bias-type fault. In particular, according to diverse noise levels and windows lengths, meaningful simulation results are given for the abrupt bias-type fault.
32
Wang, Zhong Jie, and Yong Chun Liang. "Application of BAM Network in Fault Diagnosis of Oil-Immerseed Transformer." Applied Mechanics and Materials 325-326 (June 2013): 424–30. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.424.
Full textAbstract:
Bidirectional Associative Memory (BAM) network is presented to analysis the fault of power transformer. In order to improve the classification accuracy, the conception of combination is introduced. The fault diagnosis of power transformer is consisted of 4 BAM networks. The first BAM network is used to classify the normal and fault. The second BAM network is used to classify the heat fault and partial discharge (PD) fault. The third BAM network is used to classify MC-overheating faults in magnetic circuit and EC-overheating faults in electrical circuit. The fourth BAM network is used to classify RSI-discharge faults related to solid insulation, USI-discharge faults unrelated to solid insulation. By comparing with the RBF neural network algorithm for the same 90 input set, we conclude that the BAM network a good classifier for the fault diagnosis of power transformer.
33
Mashayekhi, V., S. Hasani Borzadaran, and M. Hoseintabar Marzebali. "Classification of Fault Severity in Induction Machine Systems Based on Temporal Convolutions and Recurrent Networks." International Transactions on Electrical Energy Systems 2022 (February 16, 2022): 1–13. http://dx.doi.org/10.1155/2022/4224356.
Full textAbstract:
Detection and severity identification of mechanical and electrical faults by means of noninvasive methods such as electrical signatures of induction machine have attracted much attention in recent years. Since operating conditions of machines and severity of faults in incipient stages influence the amplitude of fault index in the fault detection process, diagnosing fault occurrence and severity can be more complicated. In this study, an efficient method for fault detection and classification in induction machine based on deep neural networks is introduced. The introduced method applies the long short-term memory (LSTM) and fully convolutional neural networks (FCNs) in a conjoined manner. The authors use the FCN architecture for feature extraction from the time-series signal and augment it with LSTM to improve classification performance. This structure has not been previously applied for fault severity detection in induction machine systems. The authors avoid manual feature engineering and, by eliminating the preprocessing phase, directly use time series of electrical signals for fault detection and classifications. The experimental results have been carried out in different fault severities and loads. The analysis of the results and comparison with other deep and classical methods show that the faulty cases can be separated based on severity and load levels with a high accuracy (98.92%), which shows that the adopted architecture is successful in automatically extracting discriminative features from the signal.
34
Choi, Ki-Yong, and Jung-Won Lee. "Fault Localization by Comparing Memory Updates between Unit and Integration Testing of Automotive Software in an Hardware-in-the-Loop Environment." Applied Sciences 8, no. 11 (2018): 2260. http://dx.doi.org/10.3390/app8112260.
Full textAbstract:
During the inspection stage, an integration test is performed on electronic automobile parts that have passed a unit test. The faults found during this test are reported to the developer, who subsequently modifies the source code. If the tester provides the developer with memory usage information (such as functional symbol or interface signal), which works differently from normal operation in failed Hardware-in-the-Loop (HiL) testing (even when the tester has no source code), that information will be useful for debugging. In this paper, we propose a fault localization method for automotive software in an HiL environment by comparing the analysis results of updated memory between units and integration tests. Analyzing the memory usage of a normally operates unit test, makes it possible to obtain memory-updated information necessary for the operation of that particular function. By comparing this information to the memory usage when a fault occurs during an integration test, erroneously operated symbols and stored values are presented as potential root causes of the fault. We applied the proposed method to HiL testing for an OSEK/VDX-based electronic control unit (ECU). As a result of testing using fault injection, we confirmed that the fault causes can be found by checking the localized memory symbols with an average of 5.77%. In addition, when applying this methodology to a failure that occurred during a body control module (BCM) (which provides seat belt warnings) test, we could identify a suspicious symbol and find the cause of the test failure with only 8.54% of localized memory symbols.
35
Wei, Xiong, and Guo Min. "A New Nano-Design of a Fault-Tolerant Coplanar RAM with Set/Reset Ability Based on Quantum-Dots." ECS Journal of Solid State Science and Technology 11, no. 4 (2022): 041002. http://dx.doi.org/10.1149/2162-8777/ac611c.
Full textAbstract:
Quantum Dot Cellular Automata (QCA) is a recent technology that has piqued researchers’ interest because of its small size and low energy consumption. With the help of quantum dots, the QCA technology delivers a new computational foundation for constructing digital circuits. Medical imaging and quantum computing are just a few applications for quantum dots. Quantum dots are nanocrystals that transmit data at the nano-scale. Since the memory is an important digital circuit, this work proposes a fault-tolerant loop-based coplanar Random Access Memory (RAM) with set/reset capability that uses the QCA rules. The memory cell’s operation is verified both physically and through simulations with the QCADesigner program. The quantum cost of the proposed memory cell shows that it has a negligible quantum cost. The proposed QCA-based memory circuit performs well in simulations, with 96 QCA cells and the output signal generated after 0.75 clock phases. The gates and wire in this design have around 85 percent better fault-tolerant capability than the best-presented memory systems. Furthermore, this circuit can tolerate most cell omission, displacement, misalignment, and deposition faults. This structure can be used to create high-performance higher-order fault-tolerant memory structures.
36
G., Sathesh Kumar*1 &. V. Saminadan2. "A NOVAL BISR APPROACH FOR EMBEDDED MEMORY SELF REPAIR." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 5, no. 9 (2018): 267–74. https://doi.org/10.5281/zenodo.1441095.
Full textAbstract:
As the density of embedded memory increases, manufacturing yields of integrated circuits can reach unacceptable limits. Normal memory testing operations require BIST to effectively deal with problems such as limited access and "at speed" testing. Built-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. This project proposes a BIRA scheme for RAMs, which can provide the optimal repair rate using very low area cost and single test run of multiple single input change (MSIC) vectors in a pattern. Furthermore, the manifested errors are detected at the modules’ outputs using novel voting, while the latent faults are detected by comparing the internal states of the memory modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules.
37
Orsi, Robert A. "The Fault of Memory." Journal of Family History 15, no. 2 (1990): 133–47. http://dx.doi.org/10.1177/036319909001500202.
Full text
38
Poeppelman, AlanD. "4692923 Fault tolerant memory." Microelectronics Reliability 28, no. 2 (1988): 329–30. http://dx.doi.org/10.1016/0026-2714(88)90379-4.
Full text
39
Wei, Zhihui, Zhengang Liu, Zhengbo Guo, and Haidong Guo. "Research on an aeroengine bearing fault diagnosis method based on WMSST-CNN-BKA-LSSVM." Journal of Physics: Conference Series 2882, no. 1 (2024): 012038. http://dx.doi.org/10.1088/1742-6596/2882/1/012038.
Full textAbstract:
Abstract To effectively extract the fault feature from small sample datasets and improve the accuracy of the model, an aeroengine bearing fault diagnosis method is proposed in this research based on wavelet multi-synchrosqueezed transform-convolutional neural network-black-winged kite algorithm-least squares support vector machine (WMSST-CNN-BKA-LSSVM). WMSST was used to perform modal decomposition on the collected fault data to obtain the time-frequency images. The time-frequency images were input into CNN for fault data feature extraction. The results of the CNN fully connected layer were used as input to the LSSVM, and the BKA was used to optimize the key parameters of the LSSVM to classify aeroengine bearing faults. The method was verified by aeroengine bearing test data from the Harbin Institute of Technology. The research showed that the accuracy is 99.86% when the faulty test samples are 70%, and the accuracy is 93.90% when the faulty samples are 30%. The accuracy showed the applicability of this method in small sample fault diagnosis. By comparing the method with a one-dimensional convolutional neural network (1D-CNN) and the convolutional neural network - long short-term memory (CNN-LSTM), it is found that the accuracy has been dramatically improved.
40
Chu, Kenny Sau Kang, Kuewwai Chew, and Yoong Choon Chang. "Fault-Diagnosis and Fault-Recovery System of Hall Sensors in Brushless DC Motor Based on Neural Networks." Sensors 23, no. 9 (2023): 4330. http://dx.doi.org/10.3390/s23094330.
Full textAbstract:
This paper proposes a neural-network-based framework using Convolutional Neural Network and Long-Short Term Memory (CNN-LSTM) for detecting faults and recovering signals from Hall sensors in brushless DC motors. Hall sensors are critical components in determining the position and speed of motors, and faults in these sensors can disrupt their normal operation. Traditional fault-diagnosis methods, such as state-sensitive and transition-sensitive approaches, and fault-recovery methods, such as vector tracking observer, have been widely used in the industry but can be inflexible when applied to different models. The proposed fault diagnosis using the CNN-LSTM model was trained on the signal sequences of Hall sensors and can effectively distinguish between normal and faulty signals, achieving an accuracy of the fault-diagnosis system of around 99.3% for identifying the type of fault. Additionally, the proposed fault recovery using the CNN-LSTM model was trained on the signal sequences of Hall sensors and the output of the fault-detection system, achieving an efficiency of determining the position of the phase in the sequence of the Hall sensor signal at around 97%. This work has three main contributions: (1) a CNN-LSTM neural network structure is proposed to be implemented in both the fault-diagnosis and fault-recovery systems for efficient learning and feature extraction from the Hall sensor data. (2) The proposed fault-diagnosis system is equipped with a sensitive and accurate fault-diagnosis system that can achieve an accuracy exceeding 98%. (3) The proposed fault-recovery system is capable of recovering the position in the sequence states of the Hall sensors, achieving an accuracy of 95% or higher.
41
Ding, Dong, Lei Wang, Zhijie Yang, Kai Hu, and Hongjun He. "ACIMS: Analog CIM Simulator for DNN Resilience." Electronics 10, no. 6 (2021): 686. http://dx.doi.org/10.3390/electronics10060686.
Full textAbstract:
Analog Computing In Memory (ACIM) combines the advantages of both Compute In Memory (CIM) and analog computing, making it suitable for the design of energy-efficient hardware accelerators for computationally intensive DNN applications. However, their use will introduce hardware faults that decrease the accuracy of DNN. In this work, we take Sandwich-Ram as the real hardware example of ACIM and are the first to propose a fault injection and fault-aware training framework for it, named Analog Computing In Memory Simulator (ACIMS). Using this framework, we can simulate and repair the hardware faults of ACIM. The experimental results show that ACIMS can recover 91.0%, 93.7% and 89.8% of the DNN’s accuracy drop through retraining on the MNIST, SVHN and Cifar-10 datasets, respectively; moreover, their adjusted accuracy can reach 97.0%, 95.3% and 92.4%.
42
Ravichand, S., T. Madhu, and M. Sailaja. "A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage." International Journal of Emerging Research in Management and Technology 6, no. 8 (2018): 235. http://dx.doi.org/10.23956/ijermt.v6i8.145.
Full textAbstract:
In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit. This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.
43
Savir, Jacob. "BIST-Based Fault Diagnosis in the Presence of Embedded Memories." VLSI Design 12, no. 4 (2001): 487–500. http://dx.doi.org/10.1155/2001/32515.
Full textAbstract:
An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.
44
Aiman, Zakwan Jidin, Hussin Razaidi, Weng Fook Lee, and Syafiq Mispan Mohd. "A review paper on memory fault models and test algorithms." Bulletin of Electrical Engineering and Informatics 10, no. 6 (2021): 3083–93. https://doi.org/10.11591/eei.v10i6.3048.
Full textAbstract:
Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.
45
ADEYEYE, Adebimpe O., Abraham O. AMOLE, and Oluwaseun A. BAMIDO. "ANALYSIS OF RECURRENT NEURAL NETWORK AND LONG-SHORT TERM MEMORY BASED FAULT DETECTION SYSTEMS FOR MICROGRID APPLICATIONS." OAUSTECH Journal of Engineering and Intelligent Technology 1, no. 1 (2025): 1–14. https://doi.org/10.36108/ojeit/5202.10.0110.
Full textAbstract:
Microgrids are modern small-scale versions of centralized electricity systems, and due to their complexity and the significant impact of financial loss or damage in the event of a fault, the need for an effective method of fault detection is crucial. This study addressed the critical need for effective fault detection and classification to ensure timely system restoration in the vent of fault. The investigation was based on design and simulation of a microgrid model, strategically engineered to manifest fault scenarios such as varying transient faults to different types of short circuit faults. The microgrid served the dual purpose of simulating real-world challenges and generating a robust dataset for the artificial intelligence-based fault detection models. The dataset was used for training and validating the long-short term memory (LSTM) and recurrent neural network (RNN) fault detection and classification models. The microgrid simulation served as a controlled yet representative environment for fault detection model assessment. A comparative analysis of the fault detection models was carried out by evaluating their performance using metrics like as precision, recall, F1-score, and accuracy across multiple fault classes. Notably, the LSTM model demonstrated a high accuracy of 93% while the RNN model excelled in achieving perfect precision and recall scores which resulted in the model’s 100% accuracy. This study has the potential to revolve the field of microgrid fault detection and classification thereby enhancing microgrid resilience. This study finds application in sustainable microgrids design and operation consequently, promoting the realization of SDG 7 and 11.
46
Cabrera, Diego, Ruben Medina, Mariela Cerrada, René-Vinicio Sánchez, Edgar Estupiñan, and Chuan Li. "Improved Mel Frequency Cepstral Coefficients for Compressors and Pumps Fault Diagnosis with Deep Learning Models." Applied Sciences 14, no. 5 (2024): 1710. http://dx.doi.org/10.3390/app14051710.
Full textAbstract:
Compressors and pumps are machines frequently used in petroleum and chemical industries for fluid transportation through flow systems to keep industrial processes running permanently. As their failure can produce costly disruption, developing fault detection and diagnosis tools is essential for accurately detecting and diagnosing faults. This research proposes a bi-dimensional representation of the vibration signal corresponding to the Mel Frequency Cepstral Coefficients (MFCC) and their first two derivatives as features. The pseudo-periodic nature of the fault signature in rotating machines is exploited to put forward an efficient and accurate patch-wise fault classification method. This approach enables the classification of 13 combined types of faults in a multi-stage centrifugal pump and 17 faults in a reciprocating compressor. Classification is performed using the Long Short-Term Memory (LSTM) network, the bidirectional Long Short-Term Memory (BiLSTM) neural network, and the Convolutional Neural Network (CNN). Accurate classification over 99% is attained, showing that the proposed feature extraction procedure correctly classifies a large set of faults simultaneously appearing in such rotating machines.
47
Kim, Kyuchull, and Kewal K. Saluja. "HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits." VLSI Design 4, no. 3 (1996): 181–97. http://dx.doi.org/10.1155/1996/72136.
Full textAbstract:
The paper identifies the inefficiencies of the critical processes in concurrent fault simulation and proposes methods to remove such inefficiencies in a systematic manner. Also, proposed are dynamic memory usage reduction strategies for concurrent fault simulators. Through extensive step-by-step experimentation, we verified the effectiveness of the proposed methods for performance improvement and identified best memory management strategy for dynamic memory usage reduction. A simulator, HySim, based on the proposed methods is implemented and shown to outperform the existing fault simulators and achieve dramatic memory usage reduction. The HySim maintains fault lists which are subsets of that of a conventional concurrent fault simulator, which yields shorter fault list processing time and reduced dynamic memory usage. It also employs Release-and-Reconstruct method for fault list construction, where any fault list identified to be useless is released immediately. The experimental results show that Release-and-Reconstruct method is very effective in dynamic memory usage reduction.
48
Mishra , Abhishek Kumar, Anup Kumar Das, and Nagarajan Kandasamy. "Built-In Functional Testing of Analog In-Memory Accelerators for Deep Neural Networks." Electronics 11, no. 16 (2022): 2592. http://dx.doi.org/10.3390/electronics11162592.
Full textAbstract:
The paper develops a methodology for the online built-in self-testing of deep neural network (DNN) accelerators to validate the correct operation with respect to their functional specifications. The DNN of interest is realized in the hardware to perform in-memory computing using non-volatile memory cells as computational units. Assuming a functional fault model, we develop methods to generate pseudorandom and structured test patterns to detect hardware faults. We also develop a test-sequencing strategy that combines these different classes of tests to achieve high fault coverage. The testing methodology is applied to a broad class of DNNs trained to classify images from the MNIST, Fashion-MNIST, and CIFAR-10 datasets. The goal is to expose hardware faults which may lead to the incorrect classification of images. We achieve an average fault coverage of 94% for these different architectures, some of which are large and complex.
49
Parvathi, M. "Two Cell Fault Models and Parasitic RC Test Method for Embedded SRAM." International Journal of Engineering & Technology 7, no. 4.29 (2018): 235–38. http://dx.doi.org/10.14419/ijet.v7i4.29.26262.
Full textAbstract:
The existing research on two cell memory faults was not adequate to identify the current technology prone defects. The gaps in the invention of test methods and fault models in related to two-cell SRAM is lead to the development of new test techniques, that are presented in this paper. The cell size reduction in present day technologies will give effect on bit line and coupling capacitance, due to capacitive nature through coupling, each cell will get influence of its neighbouring cells, prone to the faulty behaviour. In addition, parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behaviour of SRAMs. This paper is focused on analysis of characterization of two-cell fault models using bridge or short as defect model in the electrical environment and further evaluates the necessary conditions to induce worst-case coupling effects. The proposed method guarantees detecting all two-cell faults in the presence of capacitive coupling and worst-case neighbourhood data for any possible open or short defect.Â
50
Faizan Ahmad. "Evaluating Fault Tolerance in Distributed Systems using Predictive Analytics with Gated Recurrent Unit and Long Short-Term Memory Models." Journal of Information Systems Engineering and Management 10, no. 27s (2025): 378–99. https://doi.org/10.52783/jisem.v10i27s.4421.
Full textAbstract:
Fault tolerance is crucial for ensuring reliability in distributed systems, where minor disruptions can cascade into significant failures, causing downtimes, productivity loss, and financial damage. The complexity and interdependencies of distributed systems make them particularly prone to faults. Designing robust fault-tolerant mechanisms is therefore essential to cater the reliability demands of modern systems. Predictive analytics has become a game-changing approach, transitioning from managing faults reactively to detecting and preventing them proactively. This study examines the integration of Gated Recurrent Units (GRU) and Long Short-Term Memory (LSTM), into predictive analytics frameworks to enhance fault tolerance in distributed systems. GRUs efficiently process sequential data, whereas LSTMs are particularly adept at capturing long-term dependencies, making them well-suited for analyzing historical fault patterns. The proposed approach leverages these models to identify critical failure indicators and predict faults with high accuracy. By enabling early detection and response to potential failures, the models prevent disruptions from escalating. Experimental results demonstrate that GRU and LSTM-based models significantly reduce unexpected downtimes through precise fault predictions. Real-time monitoring capabilities further enhance decision-making and preemptive fault-handling processes, ensuring system reliability and performance. This study highlights the practical application of GRU and LSTM models in advancing fault tolerance in distributed environments. By offering a data-driven solution, the research improves fault prediction accuracy, strengthens system resilience, and enhances operational efficiency, addressing key challenges in distributed system management.