Relevant bibliographies by topics / Memory faults

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Memory faults'

Author: Grafiati
Published: 4 June 2021
Last updated: 26 July 2025

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Journal articles on the topic "Memory faults"

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G., Kumara Swamy, and Preethi M. "A Performance Degradation Tolerance Way Tagged Cache." International Journal of Trend in Scientific Research and Development 2, no. 5 (2018): 1–5. https://doi.org/10.31142/ijtsrd15729.

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For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults so that the caches can still be marketable. In processors, caches are designed as Level 1 L1 , Level 2 L2 , and the least hard disk. If the processor wants the data from to memory it checks the availability of data in upper level cache L1 and if the data is found it sends t
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Mrozek, Ireneusz, and Vyacheslav N. Yarmolik. "Linked Coupling Faults Detection by Multirun March Tests." Applied Sciences 14, no. 6 (2024): 2501. http://dx.doi.org/10.3390/app14062501.

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This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in re
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Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (2022): 971. http://dx.doi.org/10.3390/mi13060971.

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yie
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Swamy S., Kendaganna, Rajasree P. M., Anand M. Sharma, and Jnanaprakash J. Naik. "A Review Paper on Memory Fault Models and its Algorithms." International Journal of Electrical Engineering and Computer Science 6 (October 7, 2024): 143–51. http://dx.doi.org/10.37394/232027.2024.6.17.

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The significance of testing semiconductor memories has grown significantly in the semiconductor industry due to the increased density of modern memory chips. This paper aims to investigate and analyze different types of functional faults present in today's memory technology. These faults include stuck-at faults, transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on the importance of zero-one, checkerboard, and March patte
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Park, Pangun, Piergiuseppe Di Marco, Hyejeon Shin, and Junseong Bang. "Fault Detection and Diagnosis Using Combined Autoencoder and Long Short-Term Memory Network." Sensors 19, no. 21 (2019): 4612. http://dx.doi.org/10.3390/s19214612.

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Fault detection and diagnosis is one of the most critical components of preventing accidents and ensuring the system safety of industrial processes. In this paper, we propose an integrated learning approach for jointly achieving fault detection and fault diagnosis of rare events in multivariate time series data. The proposed approach combines an autoencoder to detect a rare fault event and a long short-term memory (LSTM) network to classify different types of faults. The autoencoder is trained with offline normal data, which is then used as the anomaly detection. The predicted faulty data, cap
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Mrozek, Ireneusz. "Analysis of multibackground memory testing techniques." International Journal of Applied Mathematics and Computer Science 20, no. 1 (2010): 191–205. http://dx.doi.org/10.2478/v10006-010-0014-6.

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Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions whi
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Lakshmi A, Sowjanya, and Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.

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Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while mini
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Sowjanya, Lakshmi A. Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785–96. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.

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Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while mini
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Beydaghi, Pooria, Moosa Ayati, and Mohammad Reza Zakerzadeh. "Fault-tolerant control of a rotary shape memory alloy actuator using a terminal sliding mode controller." Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science 236, no. 8 (2021): 3886–901. http://dx.doi.org/10.1177/09544062211046741.

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This paper focuses on developing a Fault-tolerant control (FTC) method for a rotary Shape Memory Alloy (SMA) actuator against actuator faults. The SMA actuator uses a pair of SMA wires in the antagonistic configuration for rotating a pulley. A proposed Terminal Sliding Mode Controller (TSMC) is utilized to compensate for the effects of actuator faults and to guarantee acceptable tracking performance in the presence of faults. The developed closed-loop scheme is applied to both a simulated model of the actuator as well as a real actuator in an experimental setup and then, the performance is eva
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Feng, Yi, Zhan Zhang, Jun Qian, De Cheng Zuo, and Xiao Zong Yang. "A Fault Injection Platform for Availability Evaluation of IA64 System." Applied Mechanics and Materials 58-60 (June 2011): 535–40. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.535.

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Availability is one of the key features for transaction processing systems. Fault injection is one of the important techniques to hasten availability tests. A fault injection platform is designed in this paper for IA64 system which is being widely used in transaction processing business. The fault injection platform is implemented using client/server mode and a series of fault injection tools are accomplished which covers CPU faults, memory faults, disk faults, IO faults, file system faults and system call boundary errors. A group of experiments on a typical IA64 server are described and perfo
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Dissertations / Theses on the topic "Memory faults"

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Koneru, Venkata Raja Ramchandar. "Fault Insertion and Fault Analysis of Neural Cache Memory." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1592171695469746.

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Blum, Daniel Ryan. "Hardened by design approaches for mitigating transient faults in memory-based systems." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Dissertations/Spring2007/d_blum_043007.pdf.

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Rink, Norman Alexander, and Jeronimo Castrillon. "Comprehensive Backend Support for Local Memory Fault Tolerance." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-215785.

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Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to transient faults. Applications can be protected against faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to program representations at abstraction levels higher than machine instructions are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, a large proportion of a program’s memory accesses ar
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ARORA, VIKRAM. "AN EFFICIENT BUILT-IN SELF-DIAGNOSTIC METHOD FOR NON-TRADITIONAL FAULTS OF EMBEDDED MEMORY ARRAYS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037998809.

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Gadde, Priyanka. "A BIST Architecture for Testing LUTs in a Virtex-4 FPGA." University of Toledo / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.

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Mihalik, Whitney Mae. "Correcting Faults and Preserving Love: The Defense of Monastic Memory in Bernard of Clairvaux's Apologia and Peter the Venerable's Letter 28." University of Akron / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=akron1374487679.

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Izadi, Baback A. "Design of fault-tolerant distributed memory multiprocessors /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu148786754173319.

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MARTIN, ROBERT ROHAN. "MULTI-LEVEL CELL FLASH MEMORY FAULT TESTING AND DIAGNOSIS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1120232606.

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Taleb, Mohammed Yacine. "Optimizing Distributed In-memory Storage Systems˸ Fault-tolerance, Performance, Energy Efficiency." Thesis, Rennes, École normale supérieure, 2018. http://www.theses.fr/2018ENSR0015/document.

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Les technologies émergentes, telles que les objets connectés et les réseaux sociaux sont en train de changer notre manière d’interagir avec autrui. De par leur large adoption, ces technologies génèrent de plus en plus de données. Alors que la gestion de larges volumes de données fut l’un des sujets majeurs de la dernière décennie, un nouveau défi est apparu récemment : comment tirer profit de données générées en temps réel. Avec la croissance des capacités de mémoires vives, plusieurs fournisseurs services, tel que Facebook, déploient des péta-octets de DRAM afin de garantir un temps d’accès r
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Hulme, Charles A. "Testing and evaluation of the configurable fault tolerant processor (CFTP) for space-based application." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FHulme.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003.<br>Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.
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Books on the topic "Memory faults"

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Mrozek, Ireneusz. Multi-run Memory Tests for Pattern Sensitive Faults. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-91204-2.

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Catholic Church. Commissio Theologica Internationalis. Memory and reconciliation: The Church and the faults of the past, December 1999. Pauline Books & Media, 2000.

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Coghlan, B. Transparent stable memory. Trinity College, Department of Computer Science, 1991.

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Sas, Miryam. Fault lines: Cultural memory and Japanese surrealism. Stanford University Press, 1999.

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Coghlan, B. The case for TransparentStable memory. Trinity College, Department of Computer Science, 1991.

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Horiguchi, Masashi. Nanoscale memory repair. Springer, 2011.

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Klemm, W. R. Thank you brain, for all you remember: What you forgot was my fault. Benecton Press, 2004.

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Butterfield, A. Memory models: A formal analysis using VDM. Trinity College, Department of Computer Science, 1992.

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Hamdioui, Said. Testing static random access memories: Defects, fault models, and test patterns. Kluwer Academic, 2004.

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(Firm), Knovel, ed. High performance memory testing: Design principles, fault modeling, and self-test. Kluwer Academic, 2003.

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Book chapters on the topic "Memory faults"

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Hamdioui, Said. "Space of memory faults." In Testing Static Random Access Memories. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4757-6706-3_3.

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Mrozek, Ireneusz. "Multi-Cell Faults." In Multi-run Memory Tests for Pattern Sensitive Faults. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91204-2_3.

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Gąsieniec, Leszek, and Piotr Indyk. "Efficient parallel computing with memory faults." In Fundamentals of Computation Theory. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0036183.

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Chlebus, B. S., A. Gambin, and P. Indyk. "PRAM computations resilient to memory faults." In Algorithms — ESA '94. Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/bfb0049426.

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Mrozek, Ireneusz. "Introduction to Digital Memory." In Multi-run Memory Tests for Pattern Sensitive Faults. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91204-2_1.

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Li, Lili, Hao Luo, He Qi, and Feiyu Wang. "Sensor Fault Diagnosis Method of Bridge Monitoring System Based on FS-LSTM." In Advances in Frontier Research on Engineering Structures. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8657-4_44.

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AbstractAn improved long-short-term memory neural network (FS-LSTM) fault diagnosis method is proposed based on the problems of damage false alarm, data of health monitoring system incorrect caused by sensor fault in bridge structure health monitoring system. The method is verified by simulating three-span continuous beams to install several sensors and considering the five failures of one sensor, the faults such as: constant, gain, bias, gain linearity bias, and noise. At first, several pieces of white noise data are randomly generated, and each piece of white noise data is applied as a groun
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Brodal, Gerth Stølting, Allan Grønlund Jørgensen, Gabriel Moruz, and Thomas Mølhave. "Counting in the Presence of Memory Faults." In Algorithms and Computation. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10631-6_85.

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Ramana Kumari, K. L. V., M. Asha Rani, and N. Balaji. "Testing of Neighborhood Pattern-Sensitive Faults for Memory." In Advances in Intelligent Systems and Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1249-7_59.

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Mrozek, Ireneusz. "Basics of Functional RAM Testing." In Multi-run Memory Tests for Pattern Sensitive Faults. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91204-2_2.

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Mrozek, Ireneusz. "Controlled Random Testing." In Multi-run Memory Tests for Pattern Sensitive Faults. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91204-2_4.

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Conference papers on the topic "Memory faults"

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Zadkarami, M., K. V. Gernaey, A. A. Safavi, and P. Ramin. "Diagnosing Faults in Wastewater Systems: A Data-Driven Approach to Handle Imbalanced Big Data." In The 35th European Symposium on Computer Aided Process Engineering. PSE Press, 2025. https://doi.org/10.69997/sct.114532.

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Process monitoring is essential in industrial settings to ensure system functionality, necessitating the identification and understanding of fault causes. While a substantial body of research focuses on fault detection, fault diagnosis has received significantly less attention. Typically, faults originate either from abnormal instrument behavior, indicating the need for calibration or replacement, or from process faults, signaling a malfunction within the system. A primary objective of this study is to apply the proposed fault diagnosis methodology to a benchmark that closely mirrors real-worl
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Hahanov, Vladimir, Eugenia Litvinova, Hanna Hahanova, et al. "Vector-Logical In-Memory Simulation of Faults as Truth Table Addresses." In 2024 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2024. https://doi.org/10.1109/ewdts63723.2024.10873615.

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Baradaran, Fereshteh, Mohsen Raji, Azadeh Baradaran, Arezoo Baradaran, and Reihaneh Akbarifard. "Zero Memory Overhead Approach for Protecting Vision Transformer Parameters Against Bit-Flip Faults." In 2025 29th International Computer Conference, Computer Society of Iran (CSICC). IEEE, 2025. https://doi.org/10.1109/csicc65765.2025.10967400.

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Zin, Ahmad Ridhwan Md, Aiman Zakwan Jidin, Razaidi Hussin, and Mohd Syafiq Mispan. "Analysis of Disturb Coupling Faults Coverage by the March AZ2 algorithm in Memory BIST." In 2024 IEEE 22nd Student Conference on Research and Development (SCOReD). IEEE, 2024. https://doi.org/10.1109/scored64708.2024.10872732.

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Lee, Sang Su, Kwan Soo Kim, Dong Kyu Lee, Gyun Ha Kim, and Choon Ki Ahn. "Distributed Control Framework for UAV Resilience Against Faults and Cyber Attacks with Finite-Memory Approach." In 2024 IEEE 29th Pacific Rim International Symposium on Dependable Computing (PRDC). IEEE, 2024. https://doi.org/10.1109/prdc63035.2024.00033.

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Chen, Yu-Guang, and Ting-Yi Wu. "Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies." In 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE, 2024. http://dx.doi.org/10.1109/dft63277.2024.10753529.

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Devi, T., Sripelli Jagadish, E. Suganya, Ahmad Alkhayyat, and Mukesh Soni. "Hybrid Convolutional Neural Network with Bi-Long Short-Term Memory Method for Detection and Classification of Transmission Line Faults." In 2024 Second International Conference on Networks, Multimedia and Information Technology (NMITCON). IEEE, 2024. http://dx.doi.org/10.1109/nmitcon62075.2024.10699206.

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Benso, A., A. Bosio, S. Carlo, G. Natale, and P. Prinetto. "Memory Fault Simulator for Static-Linked Faults." In 2006 15th Asian Test Symposium. IEEE, 2006. http://dx.doi.org/10.1109/ats.2006.260989.

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Mohammad, M. G., L. Terkawi, and M. Albasman. "Phase change memory faults." In 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06). IEEE, 2006. http://dx.doi.org/10.1109/vlsid.2006.134.

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Kruger, Kleber, and Fabio Iaione. "Técnicas de Tolerância a Falhas em uma Plataforma para Prototipagem Rápida Usando Microcontroladores." In XX Workshop de Testes e Tolerância a Falhas. Sociedade Brasileira de Computação - SBC, 2019. http://dx.doi.org/10.5753/wtf.2019.7715.

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This paper describes the implementation of fault tolerance techniques (based on data and processing redundancy) in programming of a rapid prototyping platform using microcontrollers. To evaluate performance of these techniques was used a fault injector software and a weather station system as a case study. Experiments simulated faults in sensor readings and faults in SRAM memory regions of the weather station. Finally, the fault-tolerant system performance is presented in comparison with non-fault-tolerant system, considering incidence of failures, processing time, memory and power consumption
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Reports on the topic "Memory faults"

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Banergee, Prithviraj. A Novel System Level Approach to Fault Tolerance in Distributed Memory Multicomputers. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada284729.

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