Log in

Relevant bibliographies by topics / Memory faults / Journal articles

To see the other types of publications on this topic, follow the link: Memory faults.

Journal articles on the topic 'Memory faults'

Author: Grafiati

Published: 4 June 2021

Last updated: 19 June 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Memory faults.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

G., Kumara Swamy, and Preethi M. "A Performance Degradation Tolerance Way Tagged Cache." International Journal of Trend in Scientific Research and Development 2, no. 5 (2018): 1–5. https://doi.org/10.31142/ijtsrd15729.

Full text

Abstract:

For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults so that the caches can still be marketable. In processors, caches are designed as Level 1 L1 , Level 2 L2 , and the least hard disk. If the processor wants the data from to memory it checks the availability of data in upper level cache L1 and if the data is found it sends t

APA, Harvard, Vancouver, ISO, and other styles

2

Mrozek, Ireneusz, and Vyacheslav N. Yarmolik. "Linked Coupling Faults Detection by Multirun March Tests." Applied Sciences 14, no. 6 (2024): 2501. http://dx.doi.org/10.3390/app14062501.

Full text

Abstract:

This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in re

APA, Harvard, Vancouver, ISO, and other styles

3

Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (2022): 971. http://dx.doi.org/10.3390/mi13060971.

Full text

Abstract:

Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yie

APA, Harvard, Vancouver, ISO, and other styles

4

Swamy S., Kendaganna, Rajasree P. M., Anand M. Sharma, and Jnanaprakash J. Naik. "A Review Paper on Memory Fault Models and its Algorithms." International Journal of Electrical Engineering and Computer Science 6 (October 7, 2024): 143–51. http://dx.doi.org/10.37394/232027.2024.6.17.

Full text

Abstract:

The significance of testing semiconductor memories has grown significantly in the semiconductor industry due to the increased density of modern memory chips. This paper aims to investigate and analyze different types of functional faults present in today's memory technology. These faults include stuck-at faults, transition faults, coupling faults, address decoder faults, and neighborhood pattern-sensitive faults. The paper also delves into the techniques utilized to identify and detect these faults. In particular, the focus is placed on the importance of zero-one, checkerboard, and March patte

APA, Harvard, Vancouver, ISO, and other styles

5

Park, Pangun, Piergiuseppe Di Marco, Hyejeon Shin, and Junseong Bang. "Fault Detection and Diagnosis Using Combined Autoencoder and Long Short-Term Memory Network." Sensors 19, no. 21 (2019): 4612. http://dx.doi.org/10.3390/s19214612.

Full text

Abstract:

Fault detection and diagnosis is one of the most critical components of preventing accidents and ensuring the system safety of industrial processes. In this paper, we propose an integrated learning approach for jointly achieving fault detection and fault diagnosis of rare events in multivariate time series data. The proposed approach combines an autoencoder to detect a rare fault event and a long short-term memory (LSTM) network to classify different types of faults. The autoencoder is trained with offline normal data, which is then used as the anomaly detection. The predicted faulty data, cap

APA, Harvard, Vancouver, ISO, and other styles

6

Mrozek, Ireneusz. "Analysis of multibackground memory testing techniques." International Journal of Applied Mathematics and Computer Science 20, no. 1 (2010): 191–205. http://dx.doi.org/10.2478/v10006-010-0014-6.

Full text

Abstract:

Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions whi

APA, Harvard, Vancouver, ISO, and other styles

7

Lakshmi A, Sowjanya, and Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.

Full text

Abstract:

Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while mini

APA, Harvard, Vancouver, ISO, and other styles

8

Sowjanya, Lakshmi A. Vanipriya Ch. "Communication induced checkpointing based fault tolerance mechanism using deep-learning in IoT applications." Indonesian Journal of Electrical Engineering and Computer Science 37, no. 3 (2025): 1785–96. https://doi.org/10.11591/ijeecs.v37.i3.pp1785-1796.

Full text

Abstract:

Internet of things (IoT) is increasingly used in diverse environments such as healthcare, industry and agriculture. They carry a risk of adverse effects if they make decisions based on faulty information. Software faults, especially transient faults are a primary contributor to deficient decision-making. The existing fault tolerant mechanisms often suffer from checkpoint overheads as checkpoints are placed in all the nodes. This paper describes a novel communication induced checkpointing based fault tolerance mechanism (CIC-FTM) designed to efficiently recover from transient faults, while mini

APA, Harvard, Vancouver, ISO, and other styles

9

Beydaghi, Pooria, Moosa Ayati, and Mohammad Reza Zakerzadeh. "Fault-tolerant control of a rotary shape memory alloy actuator using a terminal sliding mode controller." Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science 236, no. 8 (2021): 3886–901. http://dx.doi.org/10.1177/09544062211046741.

Full text

Abstract:

This paper focuses on developing a Fault-tolerant control (FTC) method for a rotary Shape Memory Alloy (SMA) actuator against actuator faults. The SMA actuator uses a pair of SMA wires in the antagonistic configuration for rotating a pulley. A proposed Terminal Sliding Mode Controller (TSMC) is utilized to compensate for the effects of actuator faults and to guarantee acceptable tracking performance in the presence of faults. The developed closed-loop scheme is applied to both a simulated model of the actuator as well as a real actuator in an experimental setup and then, the performance is eva

APA, Harvard, Vancouver, ISO, and other styles

10

Feng, Yi, Zhan Zhang, Jun Qian, De Cheng Zuo, and Xiao Zong Yang. "A Fault Injection Platform for Availability Evaluation of IA64 System." Applied Mechanics and Materials 58-60 (June 2011): 535–40. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.535.

Full text

Abstract:

Availability is one of the key features for transaction processing systems. Fault injection is one of the important techniques to hasten availability tests. A fault injection platform is designed in this paper for IA64 system which is being widely used in transaction processing business. The fault injection platform is implemented using client/server mode and a series of fault injection tools are accomplished which covers CPU faults, memory faults, disk faults, IO faults, file system faults and system call boundary errors. A group of experiments on a typical IA64 server are described and perfo

APA, Harvard, Vancouver, ISO, and other styles

11

Yarmolik, Svetlana. "Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests." International Journal of Applied Mathematics and Computer Science 18, no. 3 (2008): 329–39. http://dx.doi.org/10.2478/v10006-008-0030-y.

Full text

Abstract:

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March TestsIt is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which h

APA, Harvard, Vancouver, ISO, and other styles

12

Saied, Majd, Abbas Mishi, Clovis Francis, and Ziad Noun. "A Deep Learning Approach for Fault-Tolerant Data Fusion Applied to UAV Position and Orientation Estimation." Electronics 13, no. 16 (2024): 3342. http://dx.doi.org/10.3390/electronics13163342.

Full text

Abstract:

This work introduces a novel fault-tolerance technique for data fusion in Unmanned Aerial Vehicles (UAVs), designed to address sensor faults through a deep learning-based framework. Unlike traditional methods that rely on hardware redundancy, our approach leverages Long Short-Term Memory (LSTM) networks for state estimation and a moving average (MA) algorithm for fault detection. The novelty of our technique lies in its dual strategy: utilizing LSTMs to analyze residuals and detect errors, while the MA algorithm identifies faulty sensors by monitoring variations in sensor data. This method all

APA, Harvard, Vancouver, ISO, and other styles

13

Muhammad Ejaz Sandhu. "Comparison of Fault Simulation Over Custom Kernel Module Using Various Techniques." Lahore Garrison University Research Journal of Computer Science and Information Technology 5, no. 3 (2021): 73–83. http://dx.doi.org/10.54692/lgurjcsit.2021.0503220.

Full text

Abstract:

To test the behavior of the Linux kernel module, device drivers and file system in a faulty situation, scientists tried to inject faults in different artificial environments. Since the rarity and unpredictability of such events are pretty high, thus the localization and detection of Linux kernel, device drivers, file system modules errors become unfathomable. ‘Artificial introduction of some random faults during normal tests’ is the only known approach to such mystifying problems. A standard method for performing such experiments is to generate synthetic faults and study the effects. Various f

APA, Harvard, Vancouver, ISO, and other styles

14

Vandris, Evstratios, and Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits." VLSI Design 4, no. 3 (1996): 217–29. http://dx.doi.org/10.1155/1996/34084.

Full text

Abstract:

A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast duri

APA, Harvard, Vancouver, ISO, and other styles

15

Yarmolik, V. N., D. V. Demenkovets, V. V. Petrovskaya, and A. A. Ivaniuk. "Formal description model and conditions for detecting linked coupling faults of the memory devices." Informatics 20, no. 4 (2023): 7–23. http://dx.doi.org/10.37661/1816-0301-2023-20-4-7-23.

Full text

Abstract:

Objectives. The aim of the work is to develop and analyze a formal model for describing complex linked coupling faults of memory devices and to formulate the necessary and sufficient conditions for their detection. The relevance of these studies lies in the fact that modern memory devices, characterized by a large amount of stored data and manufactured according to the latest technological standards, are distinguished by the manifestation of complex types of faults in them.Methods. The presented results are based on the classical theory and practice of march tests (March tests) of memory devic

APA, Harvard, Vancouver, ISO, and other styles

16

Zhang, Shuo, Emma Robinson, and Malabika Basu. "Wind Turbine Predictive Fault Diagnostics Based on a Novel Long Short-Term Memory Model." Algorithms 16, no. 12 (2023): 546. http://dx.doi.org/10.3390/a16120546.

Full text

Abstract:

The operation and maintenance (O&M) issues of offshore wind turbines (WTs) are more challenging because of the harsh operational environment and hard accessibility. As sudden component failures within WTs bring about durable downtimes and significant revenue losses, condition monitoring and predictive fault diagnostic approaches must be developed to detect faults before they occur, thus preventing durable downtimes and costly unplanned maintenance. Based primarily on supervisory control and data acquisition (SCADA) data, thirty-three weighty features from operational data are extracted, an

APA, Harvard, Vancouver, ISO, and other styles

17

Yarmolik, V. N., V. A. Levantsevich, D. V. Demenkovets, and I. Mrozek. "Construction and application of march tests for pattern sensitive memory faults detection." Informatics 18, no. 1 (2021): 25–42. http://dx.doi.org/10.37661/1816-0301-2021-18-1-25-42.

Full text

Abstract:

The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms

APA, Harvard, Vancouver, ISO, and other styles

18

Lodhi, Ehtisham, Fei-Yue Wang, Gang Xiong, et al. "A Novel Deep Stack-Based Ensemble Learning Approach for Fault Detection and Classification in Photovoltaic Arrays." Remote Sensing 15, no. 5 (2023): 1277. http://dx.doi.org/10.3390/rs15051277.

Full text

Abstract:

The widespread adoption of green energy resources worldwide, such as photovoltaic (PV) systems to generate green and renewable power, has prompted safety and reliability concerns. One of these concerns is fault diagnostics, which is needed to manage the reliability and output of PV systems. Severe PV faults make detecting faults challenging because of drastic weather circumstances. This research article presents a novel deep stack-based ensemble learning (DSEL) approach for diagnosing PV array faults. The DSEL approach compromises three deep-learning models, namely, deep neural network, long s

APA, Harvard, Vancouver, ISO, and other styles

19

Cabrera, Diego, Ruben Medina, Mariela Cerrada, René-Vinicio Sánchez, Edgar Estupiñan, and Chuan Li. "Improved Mel Frequency Cepstral Coefficients for Compressors and Pumps Fault Diagnosis with Deep Learning Models." Applied Sciences 14, no. 5 (2024): 1710. http://dx.doi.org/10.3390/app14051710.

Full text

Abstract:

Compressors and pumps are machines frequently used in petroleum and chemical industries for fluid transportation through flow systems to keep industrial processes running permanently. As their failure can produce costly disruption, developing fault detection and diagnosis tools is essential for accurately detecting and diagnosing faults. This research proposes a bi-dimensional representation of the vibration signal corresponding to the Mel Frequency Cepstral Coefficients (MFCC) and their first two derivatives as features. The pseudo-periodic nature of the fault signature in rotating machines i

APA, Harvard, Vancouver, ISO, and other styles

20

Amin, Mohsin, Abbas Ramazani, Fabrice Monteiro, Camille Diou, and Abbas Dandache. "A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture." International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/962062.

Full text

Abstract:

We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is

APA, Harvard, Vancouver, ISO, and other styles

21

Xie, Jialing, Weifeng Shi, and Yuqi Shi. "Research on Fault Diagnosis of Six-Phase Propulsion Motor Drive Inverter for Marine Electric Propulsion System Based on Res-BiLSTM." Machines 10, no. 9 (2022): 736. http://dx.doi.org/10.3390/machines10090736.

Full text

Abstract:

To ensure the implementation of the marine electric propulsion self-healing strategy after faults, it is necessary to diagnose and accurately classify the faults. Considering the characteristics of the residual network (ResNet) and bidirectional long short-term memory (BiLSTM), the Res-BiLSTM deep learning algorithm is used to establish a fault diagnosis model to distinguish the types of electric drive faults. First, the powerful fault feature extraction ability of the residual network is used to deeply mine the fault features in the signals. Then, perform time-series learning through a bidire

APA, Harvard, Vancouver, ISO, and other styles

22

Wang, Zhong Jie, and Yong Chun Liang. "Application of BAM Network in Fault Diagnosis of Oil-Immerseed Transformer." Applied Mechanics and Materials 325-326 (June 2013): 424–30. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.424.

Full text

Abstract:

Bidirectional Associative Memory (BAM) network is presented to analysis the fault of power transformer. In order to improve the classification accuracy, the conception of combination is introduced. The fault diagnosis of power transformer is consisted of 4 BAM networks. The first BAM network is used to classify the normal and fault. The second BAM network is used to classify the heat fault and partial discharge (PD) fault. The third BAM network is used to classify MC-overheating faults in magnetic circuit and EC-overheating faults in electrical circuit. The fourth BAM network is used to classi

APA, Harvard, Vancouver, ISO, and other styles

23

Ding, Dong, Lei Wang, Zhijie Yang, Kai Hu, and Hongjun He. "ACIMS: Analog CIM Simulator for DNN Resilience." Electronics 10, no. 6 (2021): 686. http://dx.doi.org/10.3390/electronics10060686.

Full text

Abstract:

Analog Computing In Memory (ACIM) combines the advantages of both Compute In Memory (CIM) and analog computing, making it suitable for the design of energy-efficient hardware accelerators for computationally intensive DNN applications. However, their use will introduce hardware faults that decrease the accuracy of DNN. In this work, we take Sandwich-Ram as the real hardware example of ACIM and are the first to propose a fault injection and fault-aware training framework for it, named Analog Computing In Memory Simulator (ACIMS). Using this framework, we can simulate and repair the hardware fau

APA, Harvard, Vancouver, ISO, and other styles

24

G., Sathesh Kumar*1 &. V. Saminadan2. "A NOVAL BISR APPROACH FOR EMBEDDED MEMORY SELF REPAIR." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 5, no. 9 (2018): 267–74. https://doi.org/10.5281/zenodo.1441095.

Full text

Abstract:

As the density of embedded memory increases, manufacturing yields of integrated circuits can reach unacceptable limits. Normal memory testing operations require BIST to effectively deal with problems such as limited access and "at speed" testing. Built-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. This project proposes a BIRA scheme for RAMs, which can provide the op

APA, Harvard, Vancouver, ISO, and other styles

25

Gantel, Laurent, Quentin Berthet, Emna Amri, Alexandre Karlov, and Andres Upegui. "Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application." Electronics 10, no. 17 (2021): 2148. http://dx.doi.org/10.3390/electronics10172148.

Full text

Abstract:

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbin

APA, Harvard, Vancouver, ISO, and other styles

26

Debele, Yisak, Ha-Young Shi, Assefinew Wondosen, Tae-Wan Ku, and Beom-Soo Kang. "Deep Learning-Based Robust Actuator Fault Detection and Isolation Scheme for Highly Redundant Multirotor UAVs." Drones 7, no. 7 (2023): 437. http://dx.doi.org/10.3390/drones7070437.

Full text

Abstract:

This article presents a novel approach for detecting and isolating faulty actuators in highly redundant Multirotor UAVs using cascaded Deep Neural Network (DNN) models. The proposed Fault Detection and Isolation (FDI) framework combines Long Short-Term Memory (LSTM)-based fault detection and faulty actuator locator models to achieve real-time monitoring. The study focuses on a Hexadecarotor multirotor UAV equipped with sixteen rotors. To tackle the complexity of FDI resulting from redundancy, a partitioning technique is introduced based on system dynamics. The proposed FDI scheme is composed o

APA, Harvard, Vancouver, ISO, and other styles

27

Alnatheer, Suleman, and Mohammed Altaf Ahmed. "Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC." Micromachines 12, no. 7 (2021): 811. http://dx.doi.org/10.3390/mi12070811.

Full text

Abstract:

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit

APA, Harvard, Vancouver, ISO, and other styles

28

Jiménez-Guarneros, Magdiel, Jonas Grande-Barreto, and Jose de Jesus Rangel-Magdaleno. "Multiclass Incremental Learning for Fault Diagnosis in Induction Motors Using Fine-Tuning with a Memory of Exemplars and Nearest Centroid Classifier." Shock and Vibration 2021 (October 27, 2021): 1–12. http://dx.doi.org/10.1155/2021/6627740.

Full text

Abstract:

Early detection of fault events through electromechanical systems operation is one of the most attractive and critical data challenges in modern industry. Although these electromechanical systems tend to experiment with typical faults, a common event is that unexpected and unknown faults can be presented during operation. However, current models for automatic detection can learn new faults at the cost of forgetting concepts previously learned. This article presents a multiclass incremental learning (MCIL) framework based on 1D convolutional neural network (CNN) for fault detection in induction

APA, Harvard, Vancouver, ISO, and other styles

29

Tao, Xinxin, Yingqing Guo, Wanli Zhao, Qifan Zhou, and Kejie Xu. "Fault detection and isolation of electromechanical actuator based on SAE-BiLSTM." Journal of Physics: Conference Series 2472, no. 1 (2023): 012031. http://dx.doi.org/10.1088/1742-6596/2472/1/012031.

Full text

Abstract:

Abstract The control technology of electromechanical actuator(EMA) and its fault diagnosis is one of the key problems of multi-electric aircraft study. The method based on deep learning is used to diagnose and isolate the classic faults of EMA. The simulation model of EMA is modeling according to the working principle and control law. Four typical faults of EMA are studied,including return channel jam, spall, motor fault, and position sensor fault. Sparse Auto Encoder (SAE) algorithm can perform adaptive extraction of sensor data, which preserves dimensionality reduction and compression while

APA, Harvard, Vancouver, ISO, and other styles

30

Yarmolik, V. N., I. M. Mrozek, V. A. Levantsevich, and D. V. Demenkovets. "Transparent memory tests with even repeating addresses for storage devices." Informatics 18, no. 3 (2021): 18–35. http://dx.doi.org/10.37661/1816-0301-2021-18-3-18-35.

Full text

Abstract:

The urgency of the problem of memory testing of modern computing systems is shown. Mathematical models describing the faulty states of storage devices and the methods used for their detection are investigated. The concept of address sequences (pA) with an even repetition of addresses is introduced, which are the basis of the basic element included in the structure of the new transparent march tests March _pA_1 and March _pA_2. Algorithms for the formation of such sequences and examples of their implementations are given. The maximum diagnostic ability of new tests is shown for the case of the

APA, Harvard, Vancouver, ISO, and other styles

31

Parvathi, M. "Two Cell Fault Models and Parasitic RC Test Method for Embedded SRAM." International Journal of Engineering & Technology 7, no. 4.29 (2018): 235–38. http://dx.doi.org/10.14419/ijet.v7i4.29.26262.

Full text

Abstract:

The existing research on two cell memory faults was not adequate to identify the current technology prone defects. The gaps in the invention of test methods and fault models in related to two-cell SRAM is lead to the development of new test techniques, that are presented in this paper. The cell size reduction in present day technologies will give effect on bit line and coupling capacitance, due to capacitive nature through coupling, each cell will get influence of its neighbouring cells, prone to the faulty behaviour. In addition, parasitic node capacitance and faulty node voltage of a defecti

APA, Harvard, Vancouver, ISO, and other styles

32

Wang, Zhifu, Wei Luo, Song Xu, et al. "Electric Vehicle Lithium-Ion Battery Fault Diagnosis Based on Multi-Method Fusion of Big Data." Sustainability 15, no. 2 (2023): 1120. http://dx.doi.org/10.3390/su15021120.

Full text

Abstract:

Power batteries are the core of electric vehicles, but minor faults can easily cause accidents; therefore, fault diagnosis of the batteries is very important. In order to improve the practicality of battery fault diagnosis methods, a fault diagnosis method for lithium-ion batteries in electric vehicles based on multi-method fusion of big data is proposed. Firstly, the anomalies are removed and early fault analysis is performed by t-distribution random neighborhood embedding (t-Sne) and wavelet transform denoising. Then, different features of the vehicle that have a large influence on the batte

APA, Harvard, Vancouver, ISO, and other styles

33

P., Ramakrishna, Vamshika T., and Swathi M. "FPGA Implementation of Memory Bists using Single Interface." International Journal of Recent Technology and Engineering (IJRTE) 9, no. 3 (2020): 55–58. https://doi.org/10.35940/ijrte.B3975.099320.

Full text

Abstract:

The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications. Therefore, probability of occurrence of fault in every single read and writes operation is increased in Memory BIST (MBIST). There were many testing approaches that were developed for efficient testing and diagnosis of fault. However, all algorithms are not strengthened enough to detect all possible faults that may be present due to fabrication errors or environmental disturbance. Keeping this in mind and taking the possibility of development of efficient

APA, Harvard, Vancouver, ISO, and other styles

34

Mrozek, Ireneusz, and Vyacheslav Yarmolik. "Two-Run RAM March Testing with Address Decimation." Journal of Circuits, Systems and Computers 26, no. 02 (2016): 1750031. http://dx.doi.org/10.1142/s0218126617500311.

Full text

Abstract:

Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access

APA, Harvard, Vancouver, ISO, and other styles

35

Trivedi, Mihir, Riya Kakkar, Rajesh Gupta, et al. "Blockchain and Deep Learning-Based Fault Detection Framework for Electric Vehicles." Mathematics 10, no. 19 (2022): 3626. http://dx.doi.org/10.3390/math10193626.

Full text

Abstract:

The gradual transition from a traditional transportation system to an intelligent transportation system (ITS) has paved the way to preserve green environments in metro cities. Moreover, electric vehicles (EVs) seem to be beneficial choices for traveling purposes due to their low charging costs, low energy consumption, and reduced greenhouse gas emission. However, a single failure in an EV’s intrinsic components can worsen travel experiences due to poor charging infrastructure. As a result, we propose a deep learning and blockchain-based EV fault detection framework to identify various types of

APA, Harvard, Vancouver, ISO, and other styles

36

Sun, Xiaochuan, Jiahui Gao, Yu Wang, Yingqi Li, and Xin Feng. "Towards Fault Tolerance of Reservoir Computing in Time Series Prediction." Information 14, no. 5 (2023): 266. http://dx.doi.org/10.3390/info14050266.

Full text

Abstract:

During the deployment of practical applications, reservoir computing (RC) is highly susceptible to radiation effects, temperature changes, and other factors. Normal reservoirs are difficult to vouch for. To solve this problem, this paper proposed a random adaptive fault tolerance mechanism for an echo state network, i.e., RAFT-ESN, to handle the crash or Byzantine faults of reservoir neurons. In our consideration, the faulty neurons were automatically detected and located based on the abnormalities of reservoir state output. The synapses connected to them were adaptively disconnected and withd

APA, Harvard, Vancouver, ISO, and other styles

37

Gharibi, Wajeb, Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova, Ivan Hahanov, and Irina Hahanova. "Vector-logic computing for faults-as-address deductive simulation." IAES International Journal of Robotics and Automation (IJRA) 12, no. 3 (2023): 274. http://dx.doi.org/10.11591/ijra.v12i3.pp274-288.

Full text

Abstract:

The aim of the research is to create logic-free vector computing, leveraging read-write transactions in memory, to solve the problems of modeling and simulation stuck-at-fault combinations for complex logic elements and digital structures. At the same time, the problem of creating smart data structures based on logical vectors, truth tables, and deductive matrices is considered to simplify algorithms for parallel stuck-at-fault simulation. Vector computing is a computational process based on read-write transactions on bits of a binary vector of functionality, where the input data and faults ar

APA, Harvard, Vancouver, ISO, and other styles

38

Wajeb, Gharibi, Hahanov Vladimir, Chumachenko Svetlana, Litvinova Eugenia, Hahanov Ivan, and Hahanova Irina. "Vector-logic computing for faults-as-address deductive simulation." IAES International Journal of Robotics and Automation (IJRA) 12, no. 3 (2023): 274–88. https://doi.org/10.11591/ijra.v12i3.pp274-288.

Full text

Abstract:

The aim of the research is to create logic-free vector computing, leveraging read-write transactions in memory, to solve the problems of modeling and simulation stuck-at-fault combinations for complex logic elements and digital structures. At the same time, the problem of creating smart data structures based on logical vectors, truth tables, and deductive matrices is considered to simplify algorithms for parallel stuck-at-fault simulation. Vector computing is a computational process based on read-write transactions on bits of a binary vector of functionality, where the input data and faults ar

APA, Harvard, Vancouver, ISO, and other styles

39

Mishra , Abhishek Kumar, Anup Kumar Das, and Nagarajan Kandasamy. "Built-In Functional Testing of Analog In-Memory Accelerators for Deep Neural Networks." Electronics 11, no. 16 (2022): 2592. http://dx.doi.org/10.3390/electronics11162592.

Full text

Abstract:

The paper develops a methodology for the online built-in self-testing of deep neural network (DNN) accelerators to validate the correct operation with respect to their functional specifications. The DNN of interest is realized in the hardware to perform in-memory computing using non-volatile memory cells as computational units. Assuming a functional fault model, we develop methods to generate pseudorandom and structured test patterns to detect hardware faults. We also develop a test-sequencing strategy that combines these different classes of tests to achieve high fault coverage. The testing m

APA, Harvard, Vancouver, ISO, and other styles

40

Meyyappan, S., and V. Alamelumangai. "Black Box Model based Self Healing Solution for Stuck at Faults in Digital Circuits." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 5 (2017): 2451. http://dx.doi.org/10.11591/ijece.v7i5.pp2451-2458.

Full text

Abstract:

<p>The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control sign

APA, Harvard, Vancouver, ISO, and other styles

41

S., Meyyappan, and Alamelumangai V. "Black Box Model based Self Healing Solution for Stuck at Faults in Digital Circuits." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 5 (2017): 2451–58. https://doi.org/10.11591/ijece.v7i5.pp2451-2458.

Full text

Abstract:

The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The i

APA, Harvard, Vancouver, ISO, and other styles

42

Azimi, Sarah, Corrado De Sio, Andrea Portaluri, et al. "Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems." Electronics 12, no. 1 (2022): 169. http://dx.doi.org/10.3390/electronics12010169.

Full text

Abstract:

The continuous scaling of electronic components has led to the development of high-performance microprocessors that are suitable even for safety-critical applications where radiation-induced errors such as Single Event Effects (SEEs) can have a significant impact on the performance and reliability of the system. This work is dedicated to investigating the reliability of systems based on programmable hardware and Real-time operating Systems (RTOS) in the presence of architectural faults induced by soft errors in the configuration memory of the programmable hardware. We performed a proton radiat

APA, Harvard, Vancouver, ISO, and other styles

43

, Dr. K Deepti, P. Aishwarya. "Design and Implementation of FSM Based MBIST using March Algorithm." International Journal for Modern Trends in Science and Technology, no. 8 (August 5, 2020): 18–21. http://dx.doi.org/10.46501/ijmtst060804.

Full text

Abstract:

The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms

APA, Harvard, Vancouver, ISO, and other styles

44

Gmati, Badii, Amine Ben Rhouma, Houda Meddeb, and Sejir Khojet El Khil. "Diagnosis of Multiple Open-Circuit Faults in Three-Phase Induction Machine Drive Systems Based on Bidirectional Long Short-Term Memory Algorithm." World Electric Vehicle Journal 15, no. 2 (2024): 53. http://dx.doi.org/10.3390/wevj15020053.

Full text

Abstract:

Availability and continuous operation under critical conditions are very important in electric machine drive systems. Such systems may suffer from several types of failures that affect the electric machine or the associated voltage source inverter. Therefore, fault diagnosis and fault tolerance are highly required. This paper presents a new robust deep learning-based approach to diagnose multiple open-circuit faults in three-phase, two-level voltage source inverters for induction-motor drive applications. The proposed approach uses fault-diagnosis variables obtained from the sigmoid transforma

APA, Harvard, Vancouver, ISO, and other styles

45

CAȘCAVAL, Petru, and Doina CAȘCAVAL. "Near-optimal March Tests for Three-Cell and Four-Cell Coupling Fault Models in Random-Access Memories." Romanian Journal of Information Science and Technology 27, no. 3-4 (2024): 323–35. http://dx.doi.org/10.59277/romjist.2024.3-4.06.

Full text

Abstract:

This research work addresses the problem of testing n×1 RAMs in which complex models of unlinked static three or four-cell coupling faults are considered. As in other works, it is assumed that only physically neighboring memory cells could be involved in a three or four-cell coupling fault. For this reason, these fault models can also be considered to be of the neighborhood pattern sensitive type. As extensions of the well-known model of all unlinked static two-cell coupling faults, the fault models we address are complex including faults sensitized by a transition write operation as well as f

APA, Harvard, Vancouver, ISO, and other styles

46

Hahanov, V., S. Chumachenko, Y. Litvinova, et al. "VECTOR-LOGICAL FAULT SIMULATION." Radio Electronics, Computer Science, Control, no. 2 (June 29, 2023): 37. http://dx.doi.org/10.15588/1607-3274-2023-2-5.

Full text

Abstract:

Context. The main idea is the creation of vector-logical in-memory computing (VLC), which uses only read-write transactions on the address memory for faults-as-addresses simulation. There is no traditional logic. VLC is free from processor commands and ALU for computing organization and is therefore focused on implementation in SoC and FPGA. A vector-logical method of deductive matrix synthesis for the transportation of input faults, which has a quadratic computational complexity, is proposed. An inmemory simulator-automata for vector-deductive faults-as-addresses simulation, which based on re

APA, Harvard, Vancouver, ISO, and other styles

47

Hahanov, Vladimir I., Svitlana V. Chumachenko, Eugenia I. Litvinova, and Volodymyr I. Obrizan. "In-Memory modelling and simulations." Informatics. Culture. Technology 1, no. 1 (2024): 178–83. http://dx.doi.org/10.15276/ict.01.2024.26.

Full text

Abstract:

A mechanism for modeling faults as addresses on smart data structures is proposed, which excludes the algorithm for modeling input test sets to obtain a test map of logical functionality. Smart data structures are represented by a logical vector and its derivatives in the form of truth tables and matrices. The test map is a matrix whose coordinates are defined by the combinations of all logical faults that are tested on the binary sets of the exhaustive test. The construction of the test map is focused on the architecture of in- memory computing based on read-write transactions, which makes th

APA, Harvard, Vancouver, ISO, and other styles

48

Li, Ge, Di Tang, and Shun Tang. "Transmission line fault diagnosis based on SENet-ResNext-LSTM." Journal of Physics: Conference Series 2835, no. 1 (2024): 012053. http://dx.doi.org/10.1088/1742-6596/2835/1/012053.

Full text

Abstract:

Abstract A proposed model for diagnosing faults in transmission lines, integrating attention mechanisms, the ResNext network, and the Long Short-Term Memory (LSTM) network addresses issues such as diminished precision, constrained adaptability, and reliance on conventional manual fault detection methods. Initially, waveforms captured from transmission line faults undergo wavelet transformation filtration. These waveforms are subsequently partitioned into two segments for feature extraction. One segment undergoes processing by the ResNext module, equipped with an attention mechanism, thereby re

APA, Harvard, Vancouver, ISO, and other styles

49

Pradyumna, S. Acharya, and D. Badiger Sujatha. "Design for Testability (DFT) for a Chip with Memory and Logic." Recent Trends in Analog Design and Digital Devices 3, no. 2 (2020): 1–10. https://doi.org/10.5281/zenodo.3898260.

Full text

Abstract:

<em>Faulty chips will reach customer if IC testing is not performed on the fabricated IC. Simple types of testing such as functional and structural testing are not feasible in case of a large circuit. So, Design for Testability (DFT) techniques are needed to be added to the block so that the testing becomes easier and faster. Memory Built in self-test (MBIST) for memory testing and scan insertion for sequential circuits are the major DFT techniques commonly used. DFT insertion is done by using the tool called Tessent shell. After the design is done, patterns are generated by using the tool whi

APA, Harvard, Vancouver, ISO, and other styles

50

Lee, Jeong-Geun, Deok-Hwan Kim, and Jang Hyun Lee. "Proactive Fault Diagnosis of a Radiator: A Combination of Gaussian Mixture Model and LSTM Autoencoder." Sensors 23, no. 21 (2023): 8688. http://dx.doi.org/10.3390/s23218688.

Full text

Abstract:

Radiator reliability is crucial in environments characterized by high temperatures and friction, where prompt interventions are often required to prevent system failures. This study introduces a proactive approach to radiator fault diagnosis, leveraging the integration of the Gaussian Mixture Model and Long-Short Term Memory autoencoders. Vibration signals from radiators were systematically collected through randomized durability vibration bench tests, resulting in four operating states—two normal, one unknown, and one faulty. Time-domain statistical features of these signals were extracted an

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!