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Journal articles on the topic 'Memory hierarchy'

Author: Grafiati

Published: 4 June 2021

Last updated: 10 March 2023

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1

Balasubramonian, R., D. H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. "A dynamically tunable memory hierarchy." IEEE Transactions on Computers 52, no. 10 (October 2003): 1243–58. http://dx.doi.org/10.1109/tc.2003.1234523.

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2

Tabak, Daniel. "Cache and Memory Hierarchy Design." ACM SIGARCH Computer Architecture News 23, no. 3 (June 1995): 28. http://dx.doi.org/10.1145/203618.564957.

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3

Bauer, Michael, John Clark, Eric Schkufza, and Alex Aiken. "Programming the memory hierarchy revisited." ACM SIGPLAN Notices 46, no. 8 (September 7, 2011): 13–24. http://dx.doi.org/10.1145/2038037.1941558.

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4

Graefe, Goetz. "Sorting in a Memory Hierarchy with Flash Memory." Datenbank-Spektrum 11, no. 2 (July 15, 2011): 83–90. http://dx.doi.org/10.1007/s13222-011-0062-6.

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5

Lopes, Alba Sandyra Bezerra, Ivan Saraiva Silva, and Luciano Volcan Agostini. "A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos." International Journal of Reconfigurable Computing 2012 (2012): 1–10. http://dx.doi.org/10.1155/2012/473725.

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The motion estimation is the most complex module in a video encoder requiring a high processing throughput and high memory bandwidth, mainly when the focus is high-definition videos. The throughput problem can be solved increasing the parallelism in the internal operations. The external memory bandwidth may be reduced using a memory hierarchy. This work presents a memory hierarchy model for a full-search motion estimation core. The proposed memory hierarchy model is based on a data reuse scheme considering the full search algorithm features. The proposed memory hierarchy expressively reduces the external memory bandwidth required for the motion estimation process, and it provides a very high data throughput for the ME core. This throughput is necessary to achieve real time when processing high-definition videos. When considering the worst bandwidth scenario, this memory hierarchy is able to reduce the external memory bandwidth in 578 times. A case study for the proposed hierarchy, using32×32search window and8×8block size, was implemented and prototyped on a Virtex 4 FPGA. The results show that it is possible to reach 38 frames per second when processing full HD frames (1920×1080pixels) using nearly 299 Mbytes per second of external memory bandwidth.

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6

Isabel, Maria. "Stress amplifies memory for social hierarchy." Frontiers in Neuroscience 1, no. 1 (November 1, 2007): 175–84. http://dx.doi.org/10.3389/neuro.01.1.1.013.2007.

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7

Qiming Hou, Xin Sun, Kun Zhou, C. Lauterbach, and D. Manocha. "Memory-Scalable GPU Spatial Hierarchy Construction." IEEE Transactions on Visualization and Computer Graphics 17, no. 4 (April 2011): 466–74. http://dx.doi.org/10.1109/tvcg.2010.88.

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8

Yotov, Kamen, Keshav Pingali, and Paul Stodghill. "Automatic measurement of memory hierarchy parameters." ACM SIGMETRICS Performance Evaluation Review 33, no. 1 (June 6, 2005): 181–92. http://dx.doi.org/10.1145/1071690.1064233.

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9

Mei, Xinxin, and Xiaowen Chu. "Dissecting GPU Memory Hierarchy Through Microbenchmarking." IEEE Transactions on Parallel and Distributed Systems 28, no. 1 (January 1, 2017): 72–86. http://dx.doi.org/10.1109/tpds.2016.2549523.

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10

DEVILLERS, OLIVIER. "THE DELAUNAY HIERARCHY." International Journal of Foundations of Computer Science 13, no. 02 (April 2002): 163–80. http://dx.doi.org/10.1142/s0129054102001035.

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We propose a new data structure to compute the Delaunay triangulation of a set of points in the plane. It combines good worst case complexity, fast behavior on real data, small memory occupation and the possibility of fully dynamic insertions and deletions. The location structure is organized into several levels. The lowest level just consists of the triangulation, then each level contains the triangulation of a small sample of the level below. Point location is done by walking in a triangulation to determine the nearest neighbor of the query at that level, then the walk restarts from the neighbor at the level below. Using a small subset (3%) to sample a level allows a small memory occupation; the walk and the use of the nearest neighbor to change levels quickly locate the query.

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11

Yao, Ying Biao, Xian Bin Zeng, and Guang Pei Zhao. "Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research." Applied Mechanics and Materials 236-237 (November 2012): 907–12. http://dx.doi.org/10.4028/www.scientific.net/amm.236-237.907.

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MIPS processor is widely used in embedded system, whose memory hierarchy has such an important effect on the performance and cost that how to design memory hierarchy rapidly is a key problem. To deal with the MIPS memory hierarchy research, we design a MIPS simulator “QtMips”. It is a GUI, Qt-based simulator for MIPS assembly language, which not only collects and analyzes real-time simulation information, but also supports fast memory configuration setting such as hierarchy setting, allocation setting, etc.

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12

Henderson, Scott, and Sidney C. Bailin. "A dynamic memory of software designs." Artificial Intelligence for Engineering Design, Analysis and Manufacturing 8, no. 2 (1994): 163–76. http://dx.doi.org/10.1017/s0890060400000743.

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AbstractThis paper describes an application of artificial intelligence to support software reuse. We begin by discussing the characteristics of software engineering that establish dynamic reorganization as a requirement for a repository of software artifacts. We then present an experimental system that uses incremental concept formation as the basis for dynamic reorganization, and the conceptual hierarchy that was generated by the system for a set of 67 artifacts. The hierarchy is compared to a hierarchy produced manually by independent investigators, and the automatic hierarchy is evaluated in terms of retrieval efficiency and retrieval reliability. The paper ends with a discussion of three projects that share similar objectives with our work.

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13

Cargnini, Luís, Lionel Torres, Raphael Brum, Sophiane Senni, and Gilles Sassatelli. "Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory." Journal of Low Power Electronics and Applications 4, no. 3 (August 28, 2014): 214–30. http://dx.doi.org/10.3390/jlpea4030214.

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14

Fraguela, B. B., R. Doallo, and E. L. Zapata. "Probabilistic miss equations: evaluating memory hierarchy performance." IEEE Transactions on Computers 52, no. 3 (March 2003): 321–36. http://dx.doi.org/10.1109/tc.2003.1183947.

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15

Zahran, Mohamed M. "On cache memory hierarchy for Chip-Multiprocessor." ACM SIGARCH Computer Architecture News 31, no. 1 (March 2003): 39–48. http://dx.doi.org/10.1145/773365.773370.

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16

Healy, Michael J., and Thomas P. Caudell. "Episodic memory: A hierarchy of spatiotemporal concepts." Neural Networks 120 (December 2019): 40–57. http://dx.doi.org/10.1016/j.neunet.2019.09.021.

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17

Alpern, B., L. Carter, E. Feig, and T. Selker. "The uniform memory hierarchy model of computation." Algorithmica 12, no. 2-3 (September 1994): 72–109. http://dx.doi.org/10.1007/bf01185206.

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18

Rahman, Naila, and Rajeev Raman. "Adapting Radix Sort to the Memory Hierarchy." ACM Journal of Experimental Algorithmics 6 (December 31, 2001): 7. http://dx.doi.org/10.1145/945394.945401.

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19

Fischaber, Scott, Roger Woods, and John McAllister. "SoC Memory Hierarchy Derivation from Dataflow Graphs." Journal of Signal Processing Systems 60, no. 3 (June 19, 2009): 345–61. http://dx.doi.org/10.1007/s11265-009-0380-1.

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20

Lioupis, D., N. Kanellopoulos, and M. Stefanidakis. "The memory hierarchy of the CHESS computer." Microprocessing and Microprogramming 38, no. 1-5 (September 1993): 99–107. http://dx.doi.org/10.1016/0165-6074(93)90132-5.

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21

Alglave, Jade. "A formal hierarchy of weak memory models." Formal Methods in System Design 41, no. 2 (June 27, 2012): 178–210. http://dx.doi.org/10.1007/s10703-012-0161-5.

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22

Kavi, Krishna, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, and Mike Ignatowski. "Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy." Journal of Systems Architecture 61, no. 10 (November 2015): 539–52. http://dx.doi.org/10.1016/j.sysarc.2015.07.009.

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23

Talaki, Ezinam Bertrand, Olivier Savry, Mathieu Bouvier Des Noes, and David Hely. "A Memory Hierarchy Protected against Side-Channel Attacks." Cryptography 6, no. 2 (April 20, 2022): 19. http://dx.doi.org/10.3390/cryptography6020019.

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In the vulnerability analysis of System on Chips, memory hierarchy is considered among the most valuable element to protect against information theft. Many first-order side-channel attacks have been reported on all its components from the main memory to the CPU registers. In this context, memory hierarchy encryption is widely used to ensure data confidentiality. Yet, this solution suffers from both memory and area overhead along with performance losses (timing delays), which is especially critical for cache memories that already occupy a large part of the spatial footprint of a processor. In this paper, we propose a secure and lightweight scheme to ensure the data confidentiality through the whole memory hierarchy. This is done by masking the data in cache memories with a lightweight mask generator that provides masks at each clock cycle without having to store them. Only 8-bit Initialization Vectors are stored for each mask value to enable further recomputation of the masks. The overall security of the masking scheme is assessed through a mutual information estimation that helped evaluate the minimum number of attack traces needed to succeed a profiling side-channel attack to 592 K traces in the attacking phase, which provides an acceptable security level in an analysis where an example of Signal to Noise Ratio of 0.02 is taken. The lightweight aspect of the generator has been confirmed by a hardware implementation that led to resource utilization of 400 LUTs.

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24

FRAGUELA, BASILIO B., RAMÓN DOALLO, and EMILIO L. ZAPATA. "MEMORY HIERARCHY PERFORMANCE PREDICTION FOR BLOCKED SPARSE ALGORITHMS." Parallel Processing Letters 09, no. 03 (September 1999): 347–60. http://dx.doi.org/10.1142/s0129626499000323.

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Nowadays the performance gap between processors and main memory makes an efficient usage of the memory hierarchy necessary for good program performance. Several techniques have been proposed for this purpose. Nevertheless most of them consider only regular access patterns, while many scientific and numerical applications give place to irregular patterns. A typical case is that of indirect accesses due to the use of compressed storage formats for sparse matrices. This paper describes an analytic approach to model both regular and irregular access patterns. The application modeled is an optimized sparse matrix-dense matrix product algorithm with several levels of blocking. Our model can be directly applied to any memory hierarchy consisting of K-way associative caches. Results are shown for several current microprocessor architectures.

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25

Palmer, M. E., B. Totty, and S. Taylor. "Ray casting on shared-memory architectures: memory-hierarchy considerations in volume rendering." IEEE Concurrency 6, no. 1 (January 1998): 20–35. http://dx.doi.org/10.1109/4434.656777.

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26

Pohl, Constantin, Kai-Uwe Sattler, and Goetz Graefe. "Joins on high-bandwidth memory: a new level in the memory hierarchy." VLDB Journal 29, no. 2-3 (July 13, 2019): 797–817. http://dx.doi.org/10.1007/s00778-019-00546-z.

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27

Muhle-Karbe, Paul S., Nicholas E. Myers, and Mark G. Stokes. "A Hierarchy of Functional States in Working Memory." Journal of Neuroscience 41, no. 20 (April 22, 2021): 4461–75. http://dx.doi.org/10.1523/jneurosci.3104-20.2021.

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28

Bahareh Safaei, K. "Exploring the Memory Hierarchy for Packet Processing Applications." International Journal on Computational Science & Applications 2, no. 3 (June 30, 2012): 11–19. http://dx.doi.org/10.5121/ijcsa.2012.2302.

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29

Fontana, R. E., and S. R. Hetzler. "Magnetic memories: Memory hierarchy and processing perspectives (invited)." Journal of Applied Physics 99, no. 8 (April 15, 2006): 08N902. http://dx.doi.org/10.1063/1.2162476.

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30

Bellens, Pieter, Josep M. Perez, Felipe Cabarcas, Alex Ramirez, Rosa M. Badia, and Jesus Labarta. "CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy." Scientific Programming 17, no. 1-2 (2009): 77–95. http://dx.doi.org/10.1155/2009/561672.

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Cell Superscalar's (CellSs) main goal is to provide a simple, flexible and easy programming approach for the Cell Broadband Engine (Cell/B.E.) that automatically exploits the inherent concurrency of the applications at a task level. The CellSs environment is based on a source-to-source compiler that translates annotated C or Fortran code and a runtime library tailored for the Cell/B.E. that takes care of the concurrent execution of the application. The first efforts for task scheduling in CellSs derived from very simple heuristics. This paper presents new scheduling techniques that have been developed for CellSs for the purpose of improving an application's performance. Additionally, the design of a new scheduling algorithm is detailed and the algorithm evaluated. The CellSs scheduler takes an extension of the memory hierarchy for Cell/B.E. into account, with a cache memory shared between the SPEs. All new scheduling practices have been evaluated showing better behavior of our system.

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31

Neungsoo Park, Bo Hong, and V. K. Prasanna. "Tiling, block data layout, and memory hierarchy performance." IEEE Transactions on Parallel and Distributed Systems 14, no. 7 (July 2003): 640–54. http://dx.doi.org/10.1109/tpds.2003.1214317.

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32

Okada, Masato. "A hierarchy of macrodynamical equations for associative memory." Neural Networks 8, no. 6 (January 1995): 833–38. http://dx.doi.org/10.1016/0893-6080(95)00001-g.

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33

Sardashti, Somayeh, Angelos Arelakis, Per Stenström, and David A. Wood. "A Primer on Compression in the Memory Hierarchy." Synthesis Lectures on Computer Architecture 10, no. 5 (December 18, 2015): 1–86. http://dx.doi.org/10.2200/s00683ed1v01y201511cac036.

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34

Wei-Fen Lin, S. K. Reinhardt, and D. Burger. "Designing a modern memory hierarchy with hardware prefetching." IEEE Transactions on Computers 50, no. 11 (2001): 1202–18. http://dx.doi.org/10.1109/12.966495.

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35

Fang, Bin, and Mihaela Sighireanu. "A refinement hierarchy for free list memory allocators." ACM SIGPLAN Notices 52, no. 9 (October 31, 2017): 104–14. http://dx.doi.org/10.1145/3156685.3092275.

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36

Xing Du, Xiaodong Zhang, and Zhichun Zhu. "Memory hierarchy considerations for cost-effective cluster computing." IEEE Transactions on Computers 49, no. 9 (2000): 915–33. http://dx.doi.org/10.1109/12.869323.

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37

Garashchenko, A. V., and L. G. Gagarina. "An Approach to the Formation of Test Sequences Based on the Graph Model of the Cache Memory Hierarchy." Proceedings of Universities. ELECTRONICS 25, no. 6 (December 2020): 548–57. http://dx.doi.org/10.24151/1561-5405-2020-25-6-548-557.

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The verification of the cache memory hierarchy in modern SoC due to the large state space requires a huge number of complex tests. This becomes the main problem for functional verification. To cover the entire state space, a graph model of the cache memory hierarchy as well as the methods of generating the formation of the test sequences based on this model have been proposed. The graph model vertices are a set of states (tags, values, etc.) of each hierarchy level, and the edges are a set of transitions between states (instructions for reading, records). The graph model, describing all states of the cache-memory hierarchy states, has been developed. Each edge in the graph is a separate check sequence. In case of the non-deterministic situations, such as the choice of a channel (port) for multichannel cache memory, it will not be possible to resolve them at the level of the graph model, since the choice of the channel depends on many factors not considered within the model framework. It has been proposed to create a separate instance of a subgraph for each channel. The described approach has revealed, in verification of the multiport cache-memory hierarchy of the developed core with the new vector architecture VLIW DSP, a few architectural and functional errors. This approach can be used to test other processor cores and their blocks

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38

Maity, Biswadip, Bryan Donyanavard, Anmol Surhonne, Amir Rahmani, Andreas Herkersdorf, and Nikil Dutt. "SEAMS." ACM Transactions on Embedded Computing Systems 20, no. 5 (July 2021): 1–26. http://dx.doi.org/10.1145/3466875.

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Memory approximation techniques are commonly limited in scope, targeting individual levels of the memory hierarchy. Existing approximation techniques for a full memory hierarchy determine optimal configurations at design-time provided a goal and application. Such policies are rigid: they cannot adapt to unknown workloads and must be redesigned for different memory configurations and technologies. We propose SEAMS: the first self-optimizing runtime manager for coordinating configurable approximation knobs across all levels of the memory hierarchy. SEAMS continuously updates and optimizes its approximation management policy throughout runtime for diverse workloads. SEAMS optimizes the approximate memory configuration to minimize energy consumption without compromising the quality threshold specified by application developers. SEAMS can (1) learn a policy at runtime to manage variable application quality of service ( QoS ) constraints, (2) automatically optimize for a target metric within those constraints, and (3) coordinate runtime decisions for interdependent knobs and subsystems. We demonstrate SEAMS’ ability to efficiently provide functions (1)–(3) on a RISC-V Linux platform with approximate memory segments in the on-chip cache and main memory. We demonstrate SEAMS’ ability to save up to 37% energy in the memory subsystem without any design-time overhead. We show SEAMS’ ability to reduce QoS violations by 75% with < 5% additional energy.

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39

Ströter, Daniel, Johannes S. Mueller-Roemer, André Stork, and Dieter W. Fellner. "OLBVH: octree linear bounding volume hierarchy for volumetric meshes." Visual Computer 36, no. 10-12 (July 6, 2020): 2327–40. http://dx.doi.org/10.1007/s00371-020-01886-6.

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Abstract We present a novel bounding volume hierarchy for GPU-accelerated direct volume rendering (DVR) as well as volumetric mesh slicing and inside-outside intersection testing. Our novel octree-based data structure is laid out linearly in memory using space filling Morton curves. As our new data structure results in tightly fitting bounding volumes, boundary markers can be associated with nodes in the hierarchy. These markers can be used to speed up all three use cases that we examine. In addition, our data structure is memory-efficient, reducing memory consumption by up to 75%. Tree depth and memory consumption can be controlled using a parameterized heuristic during construction. This allows for significantly shorter construction times compared to the state of the art. For GPU-accelerated DVR, we achieve performance gain of 8.4$$\times $$ × –13$$\times $$ × . For 3D printing, we present an efficient conservative slicing method that results in a 3$$\times $$ × –25$$\times $$ × speedup when using our data structure. Furthermore, we improve volumetric mesh intersection testing speed by 5$$\times $$ × –52$$\times $$ × .

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40

Balasa, Florin. "Compiler-directed design of memory hierarchy for embedded systems." Qatar Foundation Annual Research Forum Proceedings, no. 2013 (November 2013): ICTP 055. http://dx.doi.org/10.5339/qfarf.2013.ictp-055.

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41

Vaumourin, Gregory, Dombek Thomas, Guerre Alexandre, and Denis Barthou. "Specific read only data management for memory hierarchy optimization." ACM SIGBED Review 11, no. 4 (January 22, 2015): 55–60. http://dx.doi.org/10.1145/2724942.2724951.

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42

Lioris, Theodoros, Grigoris Dimitroulakos, and Konstantinos Masselos. "An early memory hierarchy evaluation simulator for multimedia applications." Microprocessors and Microsystems 38, no. 1 (February 2014): 31–41. http://dx.doi.org/10.1016/j.micpro.2013.10.006.

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43

SCHIFFMANN, YORAM. "On hierarchy and association in memory and on morphogenesis." Biochemical Society Transactions 18, no. 4 (August 1, 1990): 574–76. http://dx.doi.org/10.1042/bst0180574.

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44

Ma, Cong, William Tuohy, and David J. Lilja. "Impact of spintronic memory on multicore cache hierarchy design." IET Computers & Digital Techniques 11, no. 2 (January 25, 2017): 51–59. http://dx.doi.org/10.1049/iet-cdt.2015.0190.

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45

Zhang, Yan, Zhi-Feng Chen, and Yuan-Yuan Zhou. "Efficient Execution of Multiple Queries on Deep Memory Hierarchy." Journal of Computer Science and Technology 22, no. 2 (March 2007): 273–79. http://dx.doi.org/10.1007/s11390-007-9034-6.

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46

Mäkinen, Erkki. "A Hierarchy of Context-Free Derivations." Fundamenta Informaticae 14, no. 2 (February 1, 1991): 255–59. http://dx.doi.org/10.3233/fi-1991-14206.

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This note discusses a hierarchy of different kind of context-free derivations by studying the corresponding Szilard languages. Especially, we introduce the leftmost and rightmost breadth-first derivations which are the counterparts of the well-known (depth-first) leftmost and rightmost derivations. It is shown that the Szilard languages related to different derivation types can be recognized by one-state automata which differ from each others by their memory devices.

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47

Lastovetsky, Alexey, and Ravi Reddy. "Data Partitioning for Multiprocessors with Memory Heterogeneity and Memory Constraints." Scientific Programming 13, no. 2 (2005): 93–112. http://dx.doi.org/10.1155/2005/964902.

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The paper presents a performance model that can be used to optimally distribute computations over heterogeneous computers. This model is application-centric representing the speed of each computer by a function of the problem size. This way it takes into account the processor heterogeneity, the heterogeneity of memory structure, and the memory limitations at each level of memory hierarchy. A problem of optimal partitioning of ann-element set overpheterogeneous processors using this performance model is formulated, and its efficient solution of the complexity O(p3× log2n) is given.

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48

SHIN, D. G., and J. LEONE. "AM/AG MODEL: A HIERARCHICAL SOCIAL SYSTEM METAPHOR FOR DISTRIBUTED PROBLEM SOLVING." International Journal of Pattern Recognition and Artificial Intelligence 04, no. 03 (September 1990): 473–87. http://dx.doi.org/10.1142/s0218001490000289.

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This work explores a distributed problem solving (DPS) approach, namely the AM/AG (Amplification/Aggregation) model. The AM/AG model is a hierarchic social system metaphor for DPS based on Mintzberg’s model of organizations. At the core of the model are information flow mechanisms, namely, amplification and aggregation. Amplification is a process of decomposing a given task, called an agenda, into a set of subtasks with magnified degree of specificity and distributing them to multiple processing units downward in the hierarchy. Aggregation is a process of combining the results reported from multiple processing units into a unified view, called a resolution, and promoting the conclusion upward in the hierarchy. Amplification is discussed in detail. A set of generative rules is introduced. Each rule specifies a set of actions for transforming an input agenda into other forms with higher specificity. The proposed model can be used to account for the memory recall process which makes associations between vast amounts of related concepts, sorts out the combined results, and promotes the most plausible ones. An example of memory recall is used to illustrate the model.

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49

Ding, Stephanie, Christopher J. Cueva, Misha Tsodyks, and Ning Qian. "Visual perception as retrospective Bayesian decoding from high- to low-level features." Proceedings of the National Academy of Sciences 114, no. 43 (October 9, 2017): E9115—E9124. http://dx.doi.org/10.1073/pnas.1706906114.

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When a stimulus is presented, its encoding is known to progress from low- to high-level features. How these features are decoded to produce perception is less clear, and most models assume that decoding follows the same low- to high-level hierarchy of encoding. There are also theories arguing for global precedence, reversed hierarchy, or bidirectional processing, but they are descriptive without quantitative comparison with human perception. Moreover, observers often inspect different parts of a scene sequentially to form overall perception, suggesting that perceptual decoding requires working memory, yet few models consider how working-memory properties may affect decoding hierarchy. We probed decoding hierarchy by comparing absolute judgments of single orientations and relative/ordinal judgments between two sequentially presented orientations. We found that lower-level, absolute judgments failed to account for higher-level, relative/ordinal judgments. However, when ordinal judgment was used to retrospectively decode memory representations of absolute orientations, striking aspects of absolute judgments, including the correlation and forward/backward aftereffects between two reported orientations in a trial, were explained. We propose that the brain prioritizes decoding of higher-level features because they are more behaviorally relevant, and more invariant and categorical, and thus easier to specify and maintain in noisy working memory, and that more reliable higher-level decoding constrains less reliable lower-level decoding.

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50

BEDIENT, RICHARD, MICHAEL FRAME, KEITH GROSS, JENNIFER LANSKI, and BRENDAN SULLIVAN. "HIGHER BLOCK IFS 2: RELATIONS BETWEEN IFS WITH DIFFERENT LEVELS OF MEMORY." Fractals 18, no. 04 (December 2010): 399–408. http://dx.doi.org/10.1142/s0218348x10005044.

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We continue the program of Bedient et al.1 by investigating some of the ways of embedding IFS with 1-step memory into IFS with 2-step memory, and 1- and 2-step memory into IFS with 3-step memory. This reveals a hierarchy of attractors of m-step memory IFS as subsets of attractors of n-step memory IFS.

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