Academic literature on the topic 'Memory transistor'

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.

Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.

The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR). In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells. It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1

To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).

Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplified if we consider the lossless transistors or if the y21 -parameter of one transistor is alpha multiple of second ones.

This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.

Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.

SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.