Journal articles: 'Mentor Graphics'

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Глинкин, А., К. Никеев, and Б. Филиппов. "Решения Mentor, a Siemens Business. Часть 2." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 187, no. 6 (July 29, 2019): 140–48. http://dx.doi.org/10.22184/1992-4178.2019.187.6.140.148.

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M, Siva Kuma. "Delay Estimation of Different Approximate Adders using Mentor Graphics." International Journal of Advanced Trends in Computer Science and Engineering 8, no. 6 (December 15, 2019): 3584–87. http://dx.doi.org/10.30534/ijatcse/2019/141862019.

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Smith, N. "Interview with CEO of Mentor Graphics Walden C Rhines." Engineering & Technology 9, no. 5 (June 1, 2014): 68–71. http://dx.doi.org/10.1049/et.2014.0527.

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Шамин, Е. С., and Е. Л. Харченко. "АЛГОРИТМ РАСЧЕТА ОКОН ПРОЦЕССА ФОТОЛИТОГРАФИИ НА ОСНОВЕ МОДЕЛИ РЕЗИСТА С ПОСТОЯННЫМ ПОРОГОМ." NANOINDUSTRY Russia 96, no. 3s (June 15, 2020): 756–57. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.756.757.

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Данная работа посвящена описанию возможного алгоритма создания моделей резиста с постоянным порогом и расчета окон процесса на их основе. Приведенные изыскания реализованы в виде программного средства, использующего средства моделирования фотолитографии Mentor Graphics Calibre. This work is dedicated to the description of one of possible algorithms of constant threshold resist model generation used for photolithography process window calculation. This algorithm has been realized in the form of a program using Mentor Graphics Calibre modeling tools.

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Лобзов, Д., and А. Лохов. "Решения Mentor, a Siemens Business для проектирования ИС и печатных плат." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 186, no. 5 (May 12, 2019): 126–32. http://dx.doi.org/10.22184/1992-4178.2019.186.5.126.132.

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Часть 1 В статье приведены краткие сведения обо всех средствах проектирования ИС и печатных плат, выпускаемых компанией Mentor Graphics. В первой части представлены инструменты проектирования, моделирования и верификации цифровых, аналоговых и аналого-цифровых ИС.

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Фергусон, Дж., Д. Вертянов, К. Фелтон, И. Беляков, С. Евстафьев, В. Сидоренко, and Н. Горшкова. "ПРОЕКТИРОВАНИЕ КОРПУСОВ И МИКРОСБОРОК ПО ТЕХНОЛОГИИ FO WLP СРЕДСТВАМИ САПР MENTOR GRAPHICS. Часть 2." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 206, no. 5 (June 7, 2021): 126–34. http://dx.doi.org/10.22184/1992-4178.2021.206.5.126.134.

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Применение маршрута САПР Mentor Graphics дает разработчикам корпусов, микросборок FO WLP все необходимые функциональные возможности, инструменты проектирования и верификации для получения максимальной выгоды от новой технологии корпусирования.

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Hind, Michael, and Phil Pfeiffer. "Using regional conferences to mentor student development." ACM SIGPLAN Notices 31, no. 7 (July 1996): 4–7. http://dx.doi.org/10.1145/381841.381843.

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Виклунд, П., Д. Вертянов, И. Беляков, and С. Евстафьев. "ОСОБЕННОСТИ ПРОЕКТИРОВАНИЯ ГИБКИХ И ГИБКО-ЖЕСТКИХ ПЕЧАТНЫХ ПЛАТ. Часть 1." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 200, no. 9 (November 11, 2020): 148–53. http://dx.doi.org/10.22184/1992-4178.2020.200.9.148.153.

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В статье представлены особенности и проблемы, с которыми сталкиваются разработчики при проектировании гибких и гибко-жестких печатных плат, а также функциональные возможности сквозных маршрутов Mentor Graphics Xpedition и PADS Professional, в том числе анализ целостности сигналов.

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Mentor Graphics UK Ltd. "Hardware modelling library from mentor." Computer-Aided Design 17, no. 5 (June 1985): 249. http://dx.doi.org/10.1016/0010-4485(85)90104-6.

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Chandramore, Rasika M., and S. A. Patil. "Modelling, Designing and Analysis of Phase Locked Loop Using Pyxis Tool of Mentor Graphics." International Journal of Advanced Research in Computer Science and Software Engineering 7, no. 6 (June 30, 2017): 108–10. http://dx.doi.org/10.23956/ijarcsse/v7i6/0172.

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Prasada G.S, Sai Venkatramana, G. Seshikala, and S. Niranjana. "Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 6 (November 4, 2020): 864–70. http://dx.doi.org/10.2174/2352096513666200107091932.

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Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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Filipov, B. "Setting up the system of electrical constraints in PCB design process using Mentor Graphics’ PADS CAD: eight simple steps." ELECTRONICS: Science, Technology, Business, no. 5 (2018): 164–68. http://dx.doi.org/10.22184/1992-4178.2018.176.5.164.168.

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Becker, M., N. Lotze, J. Becker, M. Ortmanns, and Y. Manoli. "Implementierung eines verlustleistungsoptimierten Dezimators für kaskadierte Sigma-Delta Analog-Digital Umsetzer." Advances in Radio Science 3 (May 13, 2005): 389–93. http://dx.doi.org/10.5194/ars-3-389-2005.

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Abstract. Dieser Beitrag stellt die Implementierung eines neuartigen Ansatzes einer effizienten Dezimator-Architektur für kaskadierte Sigma-Delta Modulatoren vor. Die Rekombinationslogik kaskadierter Modulatoren und die Korrektur des Verstärkungsfehlers zeitkontinuierlicher (CT) Modulatoren werden in die erste Stufe des Dezimators integriert. Eine entsprechende Filtertopologie wird hergeleitet und auf einem Hardware-Emulator der Firma Mentor Graphics implementiert. Der Vergleich der vorgeschlagenen Struktur mit einer herkömmlichen Implementierung zeigt eine nennenswerte Verbesserung der Effizienz.

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Rai, Shireesh Kumar, Rishikesh Pandey, and Bharat Garg. "Design of Current Differencing Transconductance Amplifier using a Novel Approach of Transconductance Boosting for High Frequency Applications." Journal of Circuits, Systems and Computers 29, no. 04 (July 5, 2019): 2050065. http://dx.doi.org/10.1142/s0218126620500656.

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This paper introduces a novel approach of transconductance boosting for current differencing transconductance amplifier (CDTA). Generally, the variation in the transconductance is achieved by changing the bias current and/or by increasing the aspect ratios of differential pair MOSFETs. These techniques of transconductance variations suffer from several serious drawbacks which include higher power dissipation, limited range of transconductance gain and lower input/output swing. The proposed approach of transconductance boosting overcomes these drawbacks at certain extent and also provides a high value of transconductance gain with acceptable range of bandwidth and power dissipation. It includes two different techniques to make it more effective for transconductance boosting. In the first technique, common source amplifiers have been used between gate and source terminals of the differential pair MOSFETs whereas in the second technique the concept of partial positive feedback is utilized. Using this approach, a new structure of CDTA namely cross-coupled common source current differencing transconductance amplifier I (CCCS-CDTA I) is proposed. To further improve the transconductance gain of CCCS-CDTA I, another structure CCCS-CDTA II is also proposed, in which the differential pair MOSFETs are replaced by two networks of “n” parallel MOSFETs having same aspect ratios. The proposed CCCS-CDTAs are simulated in Mentor Graphics Eldo simulator using TSMC 0.18[Formula: see text][Formula: see text]m process parameters. To confirm the performance of CCCS-CDTA II, physical layout and post-layout simulation results have been presented using Mentor Graphics Calibre tool. The advantages of proposed CCCS-CDTAs have also been discussed by realizing KHN filters and oscillators.

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Gupta, Ashi. "Faster and Efficient Time Division Multiple Access (TDMA) System." International Journal of Advanced Research in Computer Science and Software Engineering 8, no. 3 (March 30, 2018): 11. http://dx.doi.org/10.23956/ijarcsse.v8i3.586.

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In this paper the author has developed a new design to implement the TDMA(Time division multiple access) system. It is a verilog code that is simulated on the “Mentor graphics MODEL SIM- ALTERA 10.1d(QUARTUS II 13.0) “ software. It allows several users to share the same frequency channel by dividing the signal into different time slots. It takes requests from the users, processes them and provide grants to the users one by one according to the priority set, in one clock cycle per grant better than the previous design which takes more than 2 cycles to process 1 request.

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Yaacob, Nor Samida. "Low Power Ring Oscillator Design in 130nm CMOS Technology." Journal of Engineering and Science Research 3, no. 3 (June 28, 2019): 14–18. http://dx.doi.org/10.26666/rmp.jesr.2019.3.3.

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A temperature-stable, low-power ring oscillator design for implementation in an Application-Specific Integrated Circuit (ASIC) is presented. In this work, the design uses a new arrangement of chain delay elements consisting of a current-starved inverter and a CMOS capacitor. This power consumption improvement ring oscillator design was built in the environment of 130nm CMOS process technology using Mentor Graphics environment with voltage supply 1V. The simulation results show a maximum power consumption of 1.036 nW and it shows that the presented design is applicable in low power advanced sensing systems application including biomedical, chemical, and other sensors.

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Rao, K. Prahlada, R. M. Vani, and P. V. Hunagund. "Mitigation of mutual coupling in microstrip antenna arrays." Технология и конструирование в электронной аппаратуре, no. 5-6 (2019): 16–24. http://dx.doi.org/10.15222/tkea2019.5-6.16.

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This article demonstrates the alleviation of mutual coupling of a simple and low-cost four-element microstrip array antenna by loading I-shaped slot-type electromagnetic band gap structure in the ground plane. FR-4 glass epoxy is used as dielectric substrate. Moreover, the proposed array antenna shows a better performance in terms of multi-band resonance. The antenna is resonating at four frequencies and a virtual size reduction of 78.48% is obtained. The designed array antenna possesses directional radiation properties. Mentor Graphics IE3D software is used to design and simulate the designed antennas and the measured results are obtained using vector network analyser.

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Mohd Chachuli, Siti Amaniah, Faiz Arith, and Mohammad Idzdihar Idris. "Optimization of Power and Gain in Two-Stage Op-Amp by Using Taguchis Approach." Advanced Materials Research 712-715 (June 2013): 1820–25. http://dx.doi.org/10.4028/www.scientific.net/amr.712-715.1820.

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This paper presents a method based on statistical approach which known as Taguchi method. This method is used to optimize power dissipations and gain in a two-stage op-amp. Standard L27 which uses three factors and two outputs is chosen to optimize power and gain in the circuit. Simulation of the circuit has been implemented by using Mentor Graphics DA-IC. From the simulation, the results showed that total power dissipation has decreased from 3.9643 mW to 1.0345 mW. The percentage of power reduction is 73.9%. The overall gain also has been improved from 22 dB to 45.49 dB. The percentage of increment gain in two-stage op-amp is 56%.

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Nath Nune, Veerendra, and Addanki Purna R. "Novel design of multiplexer and demultiplexer using reversible logic gates." International Journal of Engineering & Technology 7, no. 3.29 (August 24, 2018): 80. http://dx.doi.org/10.14419/ijet.v7i3.29.18466.

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Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.

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Rao, K. P., P. V. Hunagund, and R. M. Vani. "Study of Four Element Microstrip Antenna Array Using Patch Type Electromagnetic Band Gap Structure." Engineering, Technology & Applied Science Research 8, no. 5 (October 13, 2018): 3470–74. http://dx.doi.org/10.48084/etasr.2309.

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This paper describes enhancements in the performance of four element microstrip antenna array. The conventional microstrip antenna array is producing gain equal to 6.81dB. With the introduction of U shape patch type electromagnetic band gap structure, the proposed microstrip antenna array is producing an improved gain of 20.33dB. It is producing reduced mutual coupling of -31.44, -36.41 and -31.62dB respectively. The radiation characteristics of the proposed microstrip antenna array are improved with appreciable decrease in back lobe radiation and increase in forward power. It is resonating at single band at 5.53GHz, producing an overall bandwidth of 109.45%, against 4.89% of conventional microstrip antenna array. Microstrip antenna arrays are designed using Mentor Graphics IE3D software and measured results are obtained using vector network analyzer.

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Tomaszewski, Grzegorz, Piotr Jankowski-Mihułowicz, Mariusz Węglarski, and Wojciech Lichoń. "Inkjet-printed flexible RFID antenna for UHF RFID transponders." Materials Science-Poland 34, no. 4 (December 1, 2016): 760–69. http://dx.doi.org/10.1515/msp-2016-0097.

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AbstractThe results of technological investigations in the scope of inkjet-printed flexible RFID antennas dedicated to UHF transponders and also problems with the application of nanomaterials are reported in this paper. The design of the antenna electrical circuit and the parameters of the inkjet printing process were elaborated on the basis of the numerical model prepared in the Mentor Graphics HyperLynx 3D EM software. The project evaluation was performed by measuring electrical parameters of the structures printed with silver-based conductive inks. The obtained results confirm coincidence between the model and its implementation in the inkjet printing technology. Finally, the prepared antenna has been applied in an RFID transponder of UHF band and the functional tests are also reported in this paper.

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Rao, Prahlada, VANI R M, and P. V. Hunagund. "Eight Element Antenna Array With Reduced Back Lobe Radiation." Malaysian Journal of Applied Sciences 5, no. 2 (October 31, 2020): 78–89. http://dx.doi.org/10.37231/myjas.2020.5.2.200.

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The paper presents the improvement in the performance of eight element microstrip antenna array. The overall bandwidth of the proposed microstrip antenna array is equal to 85.74 % as compared to 4.98 % of the conventional antenna array. The proposed microstrip antenna array is producing good reduction in mutual coupling values at the resonant frequency of 5.53 GHz. Moreover, the radiation properties of conventional antenna array are improved with good reduction in power radiated in the undesired direction. The proposed microstrip antenna array is producing a healthy size reduction of 47.19 %. FR-4 glass epoxy substrate is used as dielectric substrate which has a dielectric constant of 4.2 and loss tangent of 0.0245. The microstrip antenna arrays are designed using Mentor Graphics IE3D software.

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Bibilo, P. N., Yu Yu Lankevich, and V. I. Romanov. "Logical minimization for combinatorial structure in FPGA." Informatics 18, no. 1 (March 29, 2021): 7–24. http://dx.doi.org/10.37661/1816-0301-2021-18-1-7-24.

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The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

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Balodi, Deepak, and Rahul Misra. "Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, no. 01 (July 25, 2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.

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The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.

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Ansal, Kalikuzhackal Abbas, and Thangavelu Shanmuganatham. "Asymmetric coplanar inverted L-strip-fed monopole antenna with modified ground for dual band application." International Journal of Microwave and Wireless Technologies 8, no. 1 (November 6, 2014): 103–8. http://dx.doi.org/10.1017/s1759078714001330.

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A compact asymmetric coplanar strip (ACS)-fed monopole antenna for dual-band application is presented. The single-layer antenna composed of inverted L-shaped exciting strip and an L-shaped lateral ground plane. The antenna resonating at two different frequencies, 2.4 and 5.8 GHz is covering the wireless local area network/radio frequency identification bands. The antenna has an overall dimension of 35 × 5.7 mm2when printed on a substrate of dielectric constant 4.4 and loss tangent 0.02. The planar design, simple feeding, and compactness make it easy for the integration of the antenna into circuit boards. Details of the antenna design, and simulated and experimental results are presented and discussed. The experimental result shows good conformity with simulated results. The simulation tool based on the method of moments (Mentor Graphics IE3D version 15.10) has been used to analyze and optimize the antenna.

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Ansal, Kalikuzhackal Abbas, and Thangavelu Shanmuganantham. "Compact ACS-fed antenna with DGS and DMS for WiMAX/WLAN applications." International Journal of Microwave and Wireless Technologies 8, no. 7 (March 30, 2015): 1095–100. http://dx.doi.org/10.1017/s1759078715000537.

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A novel compact asymmetric coplanar strip fed planar antenna with defected ground structure and defected microstrip structure for dual band application is presented. The proposed antenna is composed of defect in both ground plane and radiating strip. The antenna has an overall dimension of 21 × 15.35 × 1.6 mm3when printed on a substrate with dielectric constant of 4.4 and loss tangent of 0.02. The antenna resonating at two different frequencies of 3.5 and 5.5 GHz is coveringworldwide interoperability microwave access and wireless local area network bands. The planar design, simple feeding technique, and compactness make it easy for the integration of the antenna into the circuit board. Details of the antenna design, simulated, and experimental results are presented and discussed. Simulation tool, based on the method of moments (Mentor Graphics IE3D version 15.10) has been used to analyze and optimize the antenna.

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Kristianti, Veronica Ernita, Hamzah Afandi, Eri Prasetyo Wibowo, and Djoko Purnomo. "A 8-Bit DAC Design in AMS 0.35 μm CMOS Process for High-Speed Communication Systems." Advanced Materials Research 646 (January 2013): 178–83. http://dx.doi.org/10.4028/www.scientific.net/amr.646.178.

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DAC architecture that is designed in this research can be applied in high-speed communication systems. DAC architecture that is presented in this research is based on the R2R ladder method. The design requires three main components, namely switches, resistors, and op-amp. This method has been applied to the 8-bit DAC for high-speed communication system using AMS technology 0.35 μm CMOS process. Resistors that are used in R2R DAC is replaced by transistors, so that the size is smaller and easier layout in the manufacturing process. Mentor graphics software is used as a simulator of the design. DAC design with 8-bit resolution in this research can be applied to the speed up to 1000 Msps. In the way the design can be categorized as high-speed DAC that can be used in a communication system.

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Et.al, K. V. K. V. L. Pavan Kumar. "Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 3055–63. http://dx.doi.org/10.17762/turcomat.v12i3.1340.

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The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS

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K. Naresh, N. Gopi Krishna, R. Sri Hari, K. V. K. V. L. Pavan Kumar, V. S. V. Prabhakar,. "Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 161–69. http://dx.doi.org/10.17762/turcomat.v12i5.808.

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The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS.

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Battula, Brahmaiah, Valeti SaiLakshmi, Karpurapu Sunandha, S. Durga Sri Sravya, Putta Vijaya Lakshmi, and S. Navya Sri. "Design a Low Power and High Speed Parity Checker using Exclusive–or Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 4 (February 28, 2021): 121–25. http://dx.doi.org/10.35940/ijitee.d8522.0210421.

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In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by using the 130nm mentor graphics tool. Finally the constraints like power, area, delay and PDP gets optimized successfully with the presented technology. Also, alternatively we can replace EXOR modules with NAND modules to design parity checker.

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bin Rosly, Hasrul Nisham, Mamun bin Ibne Reaz, Noorfazila Kamal, and Fazida Hanim Hashim. "Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application." Applied Mechanics and Materials 833 (April 2016): 111–18. http://dx.doi.org/10.4028/www.scientific.net/amm.833.111.

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Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.

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Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.

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Nuthalapati, Soniya, Ranjitha P.V.Sai, Radhika Rani Kalapala, Lourdu Sasi Rekha Lingisetty, Sirisha Mekala, and Parveen Mohammad Firdosia. "Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive NOR Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (March 30, 2021): 81–86. http://dx.doi.org/10.35940/ijitee.e8659.0310521.

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This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.

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Bhargavi, K. Manju. "Design of Linear Feedback Shift Register for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3912–18. http://dx.doi.org/10.22214/ijraset.2021.37251.

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This paper presents the design & implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.

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Baran, Krzysztof, Antoni Różowicz, Henryk Wachta, Sebastian Różowicz, and Damian Mazur. "Thermal Analysis of the Factors Influencing Junction Temperature of LED Panel Sources." Energies 12, no. 20 (October 17, 2019): 3941. http://dx.doi.org/10.3390/en12203941.

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Limiting junction temperature Tj and maintaining its low value is crucial for the lifetime and reliability of semi-conductive light sources. Obtaining the lowest possible temperature of Tj is especially important in the case of LED panels, where in a short distance there are many light sources installed, between which there occurs mutual thermal coupling. The article presents results of simulation studies connected with the influence of construction and ambient factors that influence the value of junction temperature of exemplary LED panel sources. The influence of radiator’s construction, printed circuit boards, as well as the influence of ambient factors, such as ambient temperature Ta and air flow velocity v were subjected to the analysis. Numerical calculations were done in the FloEFD software of the Mentor Graphics company, which is based on computational fluid dynamics (CFD). For construction of the LED thermal panel model the optical efficiency ηo and real thermal resistance Rthj-c were determined in a laboratory for the applied light sources.

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Abbas, Ansal Kalikuzhackal, and Thangavelu Shanmuganatham. "Asymmetric Coplanar F-strip Fed Antenna for Dual Band Wireless Applications." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 1 (February 1, 2014): 31. http://dx.doi.org/10.11591/ijece.v5i1.pp31-37.

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<p>A compact planar antenna for dual band applications is presented in this paper. The proposed antenna has Dumbbell shaped defect on the ground plane and it is fed by Asymmetric coplanar strip(ACS). The antenna is printed on FR4 epoxy substrate and it has a compact size of 21× 19 × 1.6 mm<sup>3</sup>. The antenna exhibits a dual band of resonances at 3.4GHz and 5.5 GHz which is used for WiMAX/WLAN. The planar design, simple feeding techniques and compactness make it easy for the integration of the antenna into circuit boards. Details of the antenna design and simulated results are presented and discussed. Simulation tool, based on the method of moments (Mentor Graphics IE3D version 15.10) has been used to analyze and optimize the antenna. Various features such as compactness, simple con-figuration and low fabrication cost make the antenna is suitable for dual band wireless applications.</p>

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Alam, M. J., Mohammad Arif Sobhan Bhuiyan, Md Torikul Islam Badal, Mamun Bin Ibne Reaz, and Noorfazila Kamal. "Design of a low-power compact CMOS variable gain amplifier for modern RF receivers." Bulletin of Electrical Engineering and Informatics 9, no. 1 (February 1, 2020): 87–93. http://dx.doi.org/10.11591/eei.v9i1.1468.

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The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of 200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.

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Wu, Qiang, Gen Wang, and Xu Wen Li. "Design and Implementation of a High-Speed LVDS Data Acquisition System Based on Virtex-5 FPGA." Applied Mechanics and Materials 568-570 (June 2014): 193–97. http://dx.doi.org/10.4028/www.scientific.net/amm.568-570.193.

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A High-Speed LVDS Data Acquisition system is designed, with XILINX’s Virtex-5 FPGA as core processor as well as TI’s TMS320C6748 DSP for pre-processing and storing data. This system achieved a greater amount of image processing and faster image processing requirement. The system completed the dual LVDS image data acquisition according to the demand. The resolution of the image data is 320x257. Each image transmission frame rate of not less than 150 / sec. large amount of data throughout the system as well as real-time demanding is a big challenge for designer. The designer uses simulation tools from Mentor Graphics Hyperlynx to complete the stack and impedance calculation and signal quality simulation to ensure that the system is stable and reliable. This system also has better scalability and more reliable storage method than past designs. Recently, the system has completed testing verification and results show that this design is feasible and reliable.

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Rahiman, P. F. Khaleelur, and V. S. Jayanthi. "Low Power Adder Based Auditory Filter Architecture." Scientific World Journal 2014 (2014): 1–6. http://dx.doi.org/10.1155/2014/709149.

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Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

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Alkhadragy, Rania. "Are you a mentor? A qualitative study: imago-graphic students’ mirror views." Advances in Social Sciences Research Journal 8, no. 3 (April 8, 2021): 652–61. http://dx.doi.org/10.14738/assrj.83.9931.

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Objectives: Mentoring is widely acknowledged for providing support, fostering students’ learning and self-development. This study was conducted at the Faculty of Medicine, Suez Canal University with the following objectives, exploring students’ perception of their mentors, analysing expected roles and essential skills for mentors. Methodology: A qualitative study was conducted. A focus group was planned in the first mentorship session, a sample of 30 year 1 and 2 students divided into 2 focus groups (n=15 students per a focus group). Focus group started with an imaginary students’ drawing of the mentor followed by further analysis and discussion. Results: Data displayed in a graphical format, and then further discussed to have more details. Three main themes had emerged: perception of mentors, role of the mentor and expectations from mentors. Perception was then analysed into positive, where the ease of communication was mostly discussed, and negative perception where the fear of humiliation was one of the common students’ fears. For mentors’ roles, guidance for portfolio submission was the highest frequency (45%) then came the role of academic and personal support (30%). Conclusion: Mentorship experience is a rich process of interaction and communication between mentors and mentees. Mentors should receive appropriate training to be well prepared for their roles. This study provides practical insights into essential skills mentors should have for an effective mentorship experience. Keywords: mentorship, info-graphic, mentors, qualitative, focus group

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Paradhasaradhi, Damarla, Kollu Jaya Lakshmi, Yadavalli Harika, Busa Ravi Teja Sai, and Golla Jayanth Krishna. "Comparative analysis of SRAM cell with leakage power reduction approaches." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 863. http://dx.doi.org/10.14419/ijet.v7i2.7.11083.

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In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

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B., Nadimulla, and Aruna Mastani, S. "Adjustable PRPG for Low Power Test Patterns." International Journal of Recent Technology and Engineering 9, no. 6 (March 30, 2021): 195–201. http://dx.doi.org/10.35940/ijrte.f5500.039621.

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As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C

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Meghana, Madabhushi Sai. "Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 20, 2021): 1956–63. http://dx.doi.org/10.22214/ijraset.2021.35286.

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In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have their specifications of energy consumption, delay, power delay product. To simulate the performance of the proposed designs, we use mentor graphics, tanner tool. The simulation yields a 45-nm CMOS innovation model that focuses on the proposed plans having best speed and power other than the plan of any full adder. The proposed Full Adders has 2-28% increment in consumption of energy and power delay product compared to other design schematics. The proposed hybrid full adders are investigated with voltage 1.8V, speed ,size of transistors, area, power consumption and delay.

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Marek, Jan, Jiri Hospodka, and Ondrej Subrt. "Complex model description and main capacitor sizing for the cross-coupled charge pump synthesis process." Journal of Electrical Engineering 69, no. 5 (September 1, 2018): 337–44. http://dx.doi.org/10.2478/jee-2018-0049.

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Abstract This paper presents a dynamic part of the pump stage model of the cross-coupled charge pump. The complex model has been used for both the estimation of the N-stage pump properties in a wide range of the input parameters and derivation of equations for synthesis process, as the main capacitor sizing, which is also mentioned in the article. Dynamic part of the model (pump stage capacitances) is determined from Ward’s capacitance piece-wise model through the BSIM MOSFET model equations. Main capacitor and load capacitor sizing are based on the time response characteristics fulfilling the system behavior in time. Guideline on the MOS transistor sizing as the nonlinear main pump capacitor and specification of the diode transistor for the design process are also clarified. The characteristics of the proposed circuit have been verified in the professional design environment Mentor graphics and analysis algorithm based on the state-space description of the inner complex model was programmed in Maple SW. The main benefit is to offer the alternative way of the charge pump synthesis by using the complex model and symbolic description of all formulae to find the required pump parameters without long-time simulation process.

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Singh, Kunwar, Satish Chandra Tiwari, and Maneesha Gupta. "A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product." Scientific World Journal 2014 (2014): 1–14. http://dx.doi.org/10.1155/2014/453675.

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The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

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Kassa, Sankit, Neeraj Misra, and Rajendra Nagaria. "Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing." Facta universitatis - series: Electronics and Energetics 34, no. 2 (2021): 259–80. http://dx.doi.org/10.2298/fuee2102259k.

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Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

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Pietrikova, Alena, Tomas Girasek, Peter Lukacs, Tilo Welker, and Jens Müller. "Simulation of cooling efficiency via miniaturised channels in multilayer LTCC for power electronics." Journal of Electrical Engineering 68, no. 2 (March 28, 2017): 132–37. http://dx.doi.org/10.1515/jee-2017-0018.

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Abstract The aim of this paper is detailed investigation of thermal resistance, flow analysis and distribution of coolant as well as thermal distribution inside multilayer LTCC substrates with embedded channels for power electronic devices by simulation software. For this reason four various structures of internal channels in the multilayer LTCC substrates were designed and simulated. The impact of the volume flow, structures of channels, and power loss of chip was simulated, calculated and analyzed by using the simulation software Mentor Graphics FloEFDTM. The structure, size and location of channels have the significant impact on thermal resistance, pressure of coolant as well as the effectivity of cooling power components (chips) that can be placed on the top of LTCC substrate. The main contribution of this paper is thermal analyze, optimization and impact of 4 various cooling channels embedded in LTCC multilayer structure. Paper investigate, the effect of volume flow in cooling channels for achieving the least thermal resistance of LTCC substrate that is loaded by power thermal chips. Paper shows on the impact of the first chips thermal load on the second chip as well as. This possible new technology could ensure in the case of practical realization effective cooling and increasing reliability of high power modules.

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B. Jadhav, Sachin, Jayamala K. Patil, and Ramesh T. Patil. "Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 1 (March 1, 2013): 15. http://dx.doi.org/10.11591/ijres.v2.i1.pp15-20.

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This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

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Jyothula, Sudhakar. "Low power aware pulse triggered flip flops using modified clock gating approaches." World Journal of Engineering 15, no. 6 (December 3, 2018): 792–803. http://dx.doi.org/10.1108/wje-09-2017-0309.

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PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

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Golota, Taras I., and Sotirios G. Ziavras. "A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers." VLSI Design 12, no. 1 (January 1, 2001): 25–52. http://dx.doi.org/10.1155/2001/50167.

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Existing message-passing parallel computers employ routers designed for a specific interconnection network and deal with fixed data channel width. There are disadvantages to this approach, because the system design and development times are significant and these routers do not permit run time network reconfiguration. Changes in the topology of the network may be required for better performance or faulttolerance. In this paper, we introduce a class of high-performance universal (statically and dynamically adaptable) programmable routers (UPRs) for message-passing parallel computers. The universality of these routers is based on their capability to adapt at run and/or static times according to the characteristics of the systems and/or applications. More specifically, the number of bidirectional data channels, the channel size and the I/O port mappings (for the implementation of a particular topology) can change dynamically and statically. Our research focuses on system-level specification issues of the UPRs, their VLSI design and their simulation to estimate their performance. Our simulation of data transfers via UPR routers employs VHDL code in the Mentor Graphics environment. The results show that the performance of the routers depends mostly on their current configuration. Details of the simulation and synthesis are presented.

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Journal articles on the topic 'Mentor Graphics'

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