Relevant bibliographies by topics / Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

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Journal articles on the topic "Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary"

1

John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.
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Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.
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Peng, J. W., N. Singh, G. Q. Lo, M. Bosman, C. M. Ng, and S. J. Lee. "Germanium Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal–Oxide–Semiconductor-Compatible Process." IEEE Transactions on Electron Devices 58, no. 1 (January 2011): 74–79. http://dx.doi.org/10.1109/ted.2010.2088125.

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4

Tao, Meng, Robert W. Wallace, C. Rinn Cleavelin, and Rick L. Wise. "The Chalkboard: Silicon Complementary Metal-Oxide-Semiconductor Field-Effect Transistor." Electrochemical Society Interface 14, no. 2 (June 1, 2005): 26–27. http://dx.doi.org/10.1149/2.f03052if.

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Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

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This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.
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Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.
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Bennett, Brian R., Mario G. Ancona, and J. Brad Boos. "Compound Semiconductors for Low-Power p-Channel Field-Effect Transistors." MRS Bulletin 34, no. 7 (July 2009): 530–36. http://dx.doi.org/10.1557/mrs2009.141.

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AbstractResearch in n-channel field-effect transistors based upon III–V compound semiconductors has been very productive over the last 30 years, with successful applications in a variety of high-speed analog circuits. For digital applications, complementary circuits are desirable to minimize static power consumption. Hence, p-channel transistors are also needed. Unfortunately, hole mobilities are generally much lower than electron mobilities for III–V compounds. This article reviews the recent work to enhance hole mobilities in antimonide-based quantum wells. Epitaxial heterostructures have been grown with the channel material in 1–2% compressive strain. The strain modifies the valence band structure, resulting in hole mobilities as high as 1500 cm2/Vs. The next steps toward an ultra-low-power complementary metal oxide semiconductor technology will include development of a compatible insulator technology and integration of n- and p-channel transistors.
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Liang, Hsiao-Bin, Yi-Hsun Tsou, Yo-Sheng Lin, and Chi-Chen Chen. "Uniformly Distributed Wideband Metal–Oxide–Semiconductor Field-Effect Transistor Model for Complementary Metal–Oxide–Semiconductor Radio-Frequency Integrated Cirsuits Applications." Japanese Journal of Applied Physics 47, no. 2 (February 15, 2008): 807–13. http://dx.doi.org/10.1143/jjap.47.807.

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Lee, Kitae, Sihyun Kim, Daewoong Kwon, and Byung-Gook Park. "Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation." Applied Sciences 10, no. 14 (July 20, 2020): 4977. http://dx.doi.org/10.3390/app10144977.

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Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.
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Tsai, Yu-Yang, Chun-Yu Kuo, Bo-Chang Li, Po-Wen Chiu, and Klaus Y. J. Hsu. "A Graphene/Polycrystalline Silicon Photodiode and Its Integration in a Photodiode–Oxide–Semiconductor Field Effect Transistor." Micromachines 11, no. 6 (June 17, 2020): 596. http://dx.doi.org/10.3390/mi11060596.

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In recent years, the characteristics of the graphene/crystalline silicon junction have been frequently discussed in the literature, but study of the graphene/polycrystalline silicon junction and its potential applications is hardly found. The present work reports the observation of the electrical and optoelectronic characteristics of a graphene/polycrystalline silicon junction and explores one possible usage of the junction. The current–voltage curve of the junction was measured to show the typical exponential behavior that can be seen in a forward biased diode, and the photovoltage of the junction showed a logarithmic dependence on light intensity. A new phototransistor named the “photodiode–oxide–semiconductor field effect transistor (PDOSFET)” was further proposed and verified in this work. In the PDOSFET, a graphene/polycrystalline silicon photodiode was directly merged on top of the gate oxide of a conventional metal–oxide–semiconductor field effect transistor (MOSFET). The magnitude of the channel current of this phototransistor showed a logarithmic dependence on the illumination level. It is shown in this work that the PDOSFET facilitates a better pixel design in a complementary metal–oxide–semiconductor (CMOS) image sensor, especially beneficial for high dynamic range (HDR) image detection.
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Dissertations / Theses on the topic "Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary"

1

Khan, Shamsul Arefin. "Deep sub-micron MOS transistor design and manufacturing sensitivity analysis /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Wu, Kehuey. "Strain effects on the valence band of silicon piezoresistance in p-type silicon and mobility enhancement in strained silicon pMOSFET /." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0008390.

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Vega, Reinaldo A. "Schottky field effect transistors and Schottky CMOS circuitry /." Online version of thesis, 2006. http://hdl.handle.net/1850/5179.

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Wu, Xu Sheng. "Three dimensional multi-gates devices and circuits fabrication, characterization, and modeling /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20WUX.

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Modzelewski, Kenneth Paul. "DC parameter extraction technique for independent double gate MOSFETs a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=11&did=1759989211&SrchMode=1&sid=1&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1250600320&clientId=28564.

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Liu, Kou-chen. "Si1-xGex/Si vertical MOSFETs and sidewall strained Si devices : design and fabrication /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.
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Liu, Haitao. "Novel 3-D CMOS and BiCMOS devices for high-density and high-speed ICs /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LIU.

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Wang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.
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Books on the topic "Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary"

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Saijets, Jan. MOSFET RF characterization using bulk and SOI CMOS technologies. [Espoo, Finland]: VTT Technical Research Centre of Finland, 2007.

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Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. New York: IEEE Press, 2005.

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1960-, Li Harry W., and Boyce David E. 1940-, eds. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1997.

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Baker, R. Jacob. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1998.

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Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. Piscataway, NJ: IEEE Press, 2008.

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Foty, D. MOSFET modeling with SPICE: Principles and practice. Upper Saddle River, NJ: Prentice Hall PTR, 1997.

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1960-, Li Harry W., Boyce David E. 1940-, and Institute of Electrical and Electronics Engineers, eds. CMOS circuit design, layout, and simulation. New Delhi: Prentice-Hall of India, 2004.

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CMOS: Circuit design, layout, and simulation. 3rd ed. Piscataway, NJ: IEEE Press, 2010.

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El-Khatib, Ziad. Distributed CMOS bidirectional amplifiers: Broadbanding and linearization techniques. New York: Springer, 2012.

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Hossein, Sarbishaei, and Sachdev Manoj, eds. ESD protection device and circuit design for advanced CMOS technologies. [Dordrecht]: Springer, 2008.

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Book chapters on the topic "Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary"

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Bala, Shashi, Mamta Khosla, and Raj Kumar. "CNTFET-Based Memory Design." In Advances in Computer and Electrical Engineering, 16–36. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1393-4.ch002.

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As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.
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Kurinec, S. K. "Complementary Metal Oxide Semiconductor Field Effect Transistors." In Encyclopedia of Materials: Science and Technology, 1343–50. Elsevier, 2001. http://dx.doi.org/10.1016/b0-08-043152-6/00251-5.

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Kumar, Sunil, and Balwinder Raj. "Simulations and Modeling of TFET for Low Power Design." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 640–67. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8823-0.ch021.

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In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).
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Takagi, S. "Silicon–germanium (SiGe)-based field effect transistors (FET) and complementary metal oxide semiconductor (CMOS) technologies." In Silicon–Germanium (SiGe) Nanostructures, 499–527. Elsevier, 2011. http://dx.doi.org/10.1533/9780857091420.4.499.

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Conference papers on the topic "Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary"

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Yining, Liu, Wang Renze, Yang Yapeng, Zhang Jiangang, Wang Ning, Feng Zongyang, Jia Linsheng, and Liang Boning. "The Choice of MOSFET Manufacturing Technique Used in Emergency Response Robot." In 2020 International Conference on Nuclear Engineering collocated with the ASME 2020 Power Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/icone2020-16222.

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Abstract For the aim of helping the development of robots used in Radiological Emergency Planning and Preparedness, the Total Ionizing Dose (TID) effects on the threshold voltage shift (ΔVth) of different kinds of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with different geometry and different scaling technology was compared. The different gate width and length dependent between bulk Complementary Metal-Oxide-Semiconductor Transistor (CMOS) process and nanowire (NW) MOSFET as well as higher and lower technology node is noticed. The reason of this difference is explained from the aspects of Radiation Induced Narrow channel effect (RINCE) and Radiation Induced Short channel effect (RISCE). It is found that some studies in recent years have corrected the influence of negative bias temperature instability (NBTI) when considering radiation effects. The TID effects on ΔVth of several kinds of new devices such as MOSFETs with new layout geometry as well as Ge-channel and GaN channel MOSFETs are described which can be investigated more deeply.
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Rai, Raghaw, James Conner, Sharon Murphy, and Swaminathan Subramanian. "Challenges in Evaluating Thickness, Phase, and Strain in Semiconductor Devices Using High Resolution Transmission Electron Microscopy." In ISTFA 2006. ASM International, 2006. http://dx.doi.org/10.31399/asm.cp.istfa2006p0343.

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Abstract The aggressive scaling of metal oxide semiconductor field effect transistor (MOSFET) device features, including gate dielectrics, silicides, and strained Si channels, presents unique metrology and characterization challenges to control electrical properties such as reliability and leakage current. This paper describes challenges faced in measuring the thickness of thin gate oxides and interfacial layers found in high-K gate dielectrics, determining Ni silicide phase in devices, and characterizing strain in MOSFETs with SiGe stressors. From case studies, it has been observed that thin layers (gate oxide, high-K film thickness, and interfacial layer) can be measured using high-resolution transmission electron microscopy (HRTEM) with good accuracy but there are some challenges in the form of sample thickness, damage-free samples, and precise sectioning of the sample for site-specific specimens. Complementary information based on HRTEM, annular dark field, and image simulation should be used to check the accuracy of thin gate dielectric measurements.
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Niu, Baohua, Martin von Haartman, Patrick Pardy, and Mitch Sacks. "Differential Polarization Imaging and Probing [DPIP]: Seeing and Probing the “Invisible”." In ISTFA 2012. ASM International, 2012. http://dx.doi.org/10.31399/asm.cp.istfa2012p0190.

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Abstract A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.
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Perkins, John F., Richard H. Hopkins, Charles D. Brandt, Anant K. Agarwal, Suresh Seshadri, and Richard R. Siergiej. "SiC High Temperature Electronics for Next Generation Aircraft Controls Systems." In ASME 1996 International Gas Turbine and Aeroengine Congress and Exhibition. American Society of Mechanical Engineers, 1996. http://dx.doi.org/10.1115/96-gt-106.

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Several organizations, including Westinghouse, CREE, and ATM, as well as researchers in Japan and Europe, are working to develop SiC power devices for reliable, high power and high temperature environments in military, industrial, utility, and automotive applications. Other organizations, such as NASA Lewis and several universities, are also doing important basic work on basic SiC technology development. It has been recognized for two decades that the superior properties of SiC lead to range of devices with higher power, greater temperature tolerance, and significantly more radiation hardness than silicon or GaAs. This combination of superior thermal and electrical properties results in SiC devices that can operate at up to ten times the power density of Si devices for a given volume. Recent research has focused on the development of vertical metal oxide semiconductor field effect transistor (VMOSFET) power device technology, and complementary high speed, temperature-tolerant rectifier-diodes for power applications. We are also evaluating applications for field control thyristors (FCT) and MOS turn-off thyristors (MTO). The technical issues to be resolved for these devices are also common to other power device structures. The present paper reviews the relative benefits of various power devices structures, with emphasis on how the special properties of SiC enhance the desirability of specific device configurations as compared to the Si-based versions of these devices. Progress in SiC material quality and recent power device research will be reviewed, and the potential for SiC-based devices to operate at much higher temperatures than Si-based devices, or with enhanced reliability at higher temperatures will be stressed. We have already demonstrated 1000V breakdown, current densities of 1 kA/cm2, and measurements up to 400°C in small diodes. The extension of this work will enable the implementation of highly distributed aircraft power control systems, as well as actuator and signal conditioning electronics for next generation engine sensors, by permitting electronic circuits, sensors and smart actuators to be mounted on or at the engine.
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