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1
Khan, Shamsul Arefin. "Deep sub-micron MOS transistor design and manufacturing sensitivity analysis /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Wu, Kehuey. "Strain effects on the valence band of silicon piezoresistance in p-type silicon and mobility enhancement in strained silicon pMOSFET /." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0008390.
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3
Vega, Reinaldo A. "Schottky field effect transistors and Schottky CMOS circuitry /." Online version of thesis, 2006. http://hdl.handle.net/1850/5179.
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Wu, Xu Sheng. "Three dimensional multi-gates devices and circuits fabrication, characterization, and modeling /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20WUX.
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Modzelewski, Kenneth Paul. "DC parameter extraction technique for independent double gate MOSFETs a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=11&did=1759989211&SrchMode=1&sid=1&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1250600320&clientId=28564.
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Liu, Kou-chen. "Si1-xGex/Si vertical MOSFETs and sidewall strained Si devices : design and fabrication /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.
9
Liu, Haitao. "Novel 3-D CMOS and BiCMOS devices for high-density and high-speed ICs /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LIU.
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Wang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.
11
Tse, Koon-Yiu. "High-K gate oxides and metal gate materials for future complementary metal-oxide-semiconductor field-effect transistors." Thesis, University of Cambridge, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611979.
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Jouvet, Nicolas. "Intégration hybride de transistors à un électron sur un noeud technologique CMOS." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00863770.
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Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.
13
Pelloquin, Sylvain. "LaAlO3 amorphe déposé par épitaxie par jets moléculaires sur silicium comme alternative pour la grille high-κ des transistors CMOS." Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00694351.
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Depuis l'invention du transistor MOS à effet de champ dans les années 60, l'exploitation de cette brique élémentaire a permis une évolution exponentielle du domaine de la microélectronique, avec une course effrénée vers la miniaturisation des dispositifs électroniques CMOS. Dans ce contexte, l'introduction des oxydes "high-κ" (notamment HfO2) a permis de franchir la barrière sub-nanométrique de l'EOT (Equivalent Oxide Thickness) pour l'oxyde de grille. Les travaux actuels concernent notamment la recherche de matériaux "high-κ" et de procédés qui permettraient d'avoir une interface abrupte, thermodynamiquement stable avec le silicium, pouvant conduire à des EOTs de l'ordre de 5Å. L'objectif de cette thèse, était d'explorer le potentiel de l'oxyde LaAlO3 amorphe déposé sur silicium par des techniques d'Épitaxie par Jets Moléculaires, en combinant des études sur les propriétés physico-chimiques et électriques de ce système. Le travail de thèse a d'abord consisté à définir des procédures d'élaboration sur Si de couches très minces (≈4nm), robustes et reproductibles, afin de fiabiliser les mesures électriques, puis à optimiser la qualité électrique des hétérostructures en ajustant les paramètres de dépôt à partir de corrélations entre résultats électriques et propriétés physico-chimiques (densité, stœchiométrie, environnement chimique...) et enfin à valider un procédé d'intégration du matériau dans la réalisation de MOSFET. La stabilité et la reproductibilité des mesures ont été atteintes grâce à une préparation de surface du substrat adaptée et grâce à l'introduction d'oxygène atomique pendant le dépôt de LaAlO3, permettant ainsi une homogénéisation des couches et une réduction des courants de fuite. Après optimisation des paramètres de dépôt, les meilleures structures présentent des EOTs de 8-9Å, une constante diélectrique de 16 et des courants de fuite de l'ordre de 10-2A/cm². Les caractérisations physico-chimiques fines des couches par XPS ont révélé des inhomogénéités de composition qui peuvent expliquer que le κ mesuré soit inférieur aux valeurs de LaAlO3 cristallin (20-25). Bien que les interfaces LAO/Si soient abruptes après le dépôt et que LaAlO3 soit thermodynamiquement stable vis-à-vis du silicium, le système LAO amorphe /Si s'est révélé instable pour des recuits post-dépôt effectués à des températures supérieures à 700°C. Un procédé de fabrication de MOSFETs aux dimensions relâchées a été défini pour tester les filières high-κ. Les premières étapes du procédé ont été validées pour LaAlO3.
14
Phillips, Stanley David. "Single event effects and radiation hardening methodologies in SiGe HBTs for extreme environment applications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45854.
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Field-effect transistor technologies have been critical building blocks for
satellite systems since their introduction into the microelectronics industry. The
extremely high cost of launching payloads into orbit necessitates systems to have
small form factor, ultra low-power consumption, and reliable lifetime operation,
while satisfying the performance requirements of a given application. Silicon-based
complementary metal-oxide-semiconductors (Si CMOS) have traditionally been able to
adequately meet these demands when coupled with radiation hardening techniques that
have been developed over years of invested research. However, as customer demands
increase, pushing the limits of system throughput, noise, and speed, alternative
technologies must be employed. Silicon-germanium BiCMOS platforms have been
identfied as a technology candidate for meeting the performance criteria of these
pioneering satellite systems and deep space applications, contingent on their ability to
be hardened to radiation-induced damage. Given that SiGe technology is a relative new-
comer to terrestrial and extra-terrestrial applications in radiation-rich environments,
the same wealth of knowledge of time-tested radiation hardening methodologies has
not been established as it has for Si CMOS. Although SiGe BiCMOS technology has
been experimentally proven to be inherently tolerant to total-ionizing dose damage
mechanism, the single event susceptibility of this technology remains a primary concern.
The objective of this research is to characterize the physical mechanisms that drive the
origination of ion-induced transient terminal currents in SiGe HBTs that subsequently
lead to a wide range of possible single event phenomena. Building upon this learning,
a variety of device-level hardening methodologies are explored and tested for efficacy.
15
Ma, Wei. "Linearity Analysis of Single and Double-Gate Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor." Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1103138153.
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Turner, Gary Chandler. "Zinc Oxide MESFET Transistors." Thesis, University of Canterbury. Electrical and Computer Engineering, 2009. http://hdl.handle.net/10092/3439.
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Zinc oxide is a familiar ingredient in common household items including sunscreen and medicines. It
is, however, also a semiconductor material. As such, it is possible to use zinc oxide (ZnO) to make
semiconductor devices such as diodes and transistors. Being transparent to visible light in its
crystalline form means that it has the potential to be the starting material for so-called 'transparent
electronics', where the entire device is transparent. Transparent transistors have the potential to
improve the performance of the electronics currently used in LCD display screens.
Most common semiconductor devices require the material to be selectively doped with specific
impurities that can make the material into one of two electronically distinct types – p- or n-type.
Unfortunately, making reliable p-type ZnO has been elusive to date, despite considerable efforts
worldwide. This lack of p-type material has hindered development of transistors based on this
material.
One alternative is a Schottky junction, which can be used as the active element in a type of transistor
known as a metal-semiconductor field effect transistor, MESFET. Schottky junctions are traditionally
made from noble metal layers deposited onto semiconductors. Recent work at the Canterbury
University has shown that partially oxidised metals may in fact be a better choice, at least to zinc
oxide.
This thesis describes the development of a fabrication process for metal-semiconductor field effect
transistors using a silver oxide gate on epitaxially grown zinc oxide single crystals. Devices were
successfully produced and electrically characterised. The measurements show that the technology has
significant potential.
17
Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.
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The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace the CMOS logic. Post-CMOS devices are envisaged on the idea of using state variables other than the electron charge to store and manipulate information. In the first component of the thesis, a comprehensive analysis of the performance and the energy dissipation of novel logic based on various state variables is conducted, and it is demonstrated that the interconnects will continue to be a major challenge even for post-CMOS logic.
The second component of the thesis is focused on the analysis of the interconnection aspects of spin-based logic. This research goal is accomplished through the development of physically-based models of spin-transport parameters for various metallic, semiconducting, and graphene nanoribbon interconnects by incorporating the impact of size effects for narrow cross-sectional dimensions of all-spin logic devices. Due to the generic nature of the models, they can be used in the analysis of spin-based devices to study their functionality and performance more accurately. The compact nature of the models allows them to be easily embedded into the developing CAD tools for spintronic logic. These models then provide the foundation for (i) analyzing the spin injection and transport efficiency in an all-spin logic circuit with various interconnect materials, and (ii) estimating the repeater-insertion requirements in all-spin logic, and (iii) estimating the maximum circuit size for all-spin logic. The research is crucial in pinpointing the implications of the physical limits of novel interconnects at the material, device, circuit, and architecture levels.
18
Phillips, Stanley D. "Developing radiation hardening by design." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29640.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Cressler, John; Committee Member: Citrin, David; Committee Member: Shen, Shyh-Chiang. Part of the SMARTech Electronic Thesis and Dissertation Collection.
19
Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment.
Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques.
These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented
in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic
architecture.
20
Diestelhorst, Ryan M. "Silicon-germanium BiCMOS device and circuit design for extreme environment applications." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28180.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Cressler, John; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephen.
21
Venkataraman, Sunitha. "Systematic Analysis of the Small-Signal and Broadband Noise Performance of Highly Scaled Silicon-Based Field-Effect Transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16232.
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The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory.
This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-signal AC, and broadband noise performance of 0.18 um and 130 nm Si-CMOS devices operating at cryogenic temperatures is presented. The room temperature RF noise model is extended to model the high-frequency noise performance of scaled MOSFETs at temperatures down to 77 K and 10 K. Significant performance enhancement at cryogenic temperatures is demonstrated, indicating the suitability of scaled CMOS technologies for low temperature electronics. The hot-carrier reliability of MOSFETs at cryogenic temperatures is investigated and the worst-case gate voltage stress condition is determined. The degradation due to hot-carrier-induced interface-state creation is identified as the dominant degradation mechanism at room temperature down to 77 K. The effect of high-energy proton radiation on the DC, AC, and RF noise performance of 130 nm CMOS devices is studied. The performance degradation is investigated up to an equivalent total dose of 1 Mrad, which represents the worst case condition for many earth-orbiting and planetary missions.
The geometric scaling of MOSFETs has been augmented by the introduction of novel FET designs, such as the Si/SiGe MODFETs. A comprehensive characterization and modeling of the small-signal and high-frequency noise performance of highly scaled Si/SiGe n-MODFETs is presented. The effect of gate shot noise is incorporated in the broadband noise model. SiGe MODFETs offer the potential for high-speed and low-voltage operation at high frequencies and hence are attractive devices for future RF and mixed-signal applications.
This work advances the state-of-the-art in the understanding and analysis of the RF performance of highly scaled Si-CMOS devices as well as emerging technologies, such as Si/SiGe MODFETs. The key contribution of this dissertation is to provide a robust framework for the systematic characterization, analysis and modeling of the small-signal and RF noise performance of scaled Si-MOSFETs and Si/SiGe MODFETs both for mainstream and extreme-environment applications.
22
Lourenco, Nelson Estacio. "An assessment of silicon-germanium BiCMOS technologies for extreme environment applications." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45959.
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This thesis evaluates the suitability of silicon-germanium technology for electronic systems intended for extreme environments, such as ambient temperatures outside of military specification (-55 degC to 125 degC) range and intense exposures to ionizing radiation. Silicon-germanium devices and circuits were characterized at cryogenic and high-temperatures (up to 300 degC) and exposed to ionizing radiation, providing empirical evidence that silicon-germanium is an excellent platform for terrestrial and space-based electronic applications.
23
Wilcox, Edward. "Silicon-germanium devices and circuits for cryogenic and high-radiation space environments." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33850.
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This work represents several years' research into the field of radiation hardening by design. The unique characteristics of a SiGe HBT, described in Chapter 1, make it ideally suitable for use in extreme environment applications.
Chapter 2 describes the total ionizing dose effects experienced by a SiGe HBT, particularly those experienced on an Earth-orbital or lunar-surface mission. In addition, the effects of total dose are evaluated on passive devices.
As opposed to the TID-hardness of SiGe transistors, a clear vulnerability to single-event effects does exist. This field is divided into three chapters. First, the very nature of single-event transients present in SiGe HBTs is explored in Chapter 3 using a heavy-ion microbeam with both bulk and SOI platforms [31]. Then, in Chapter 4, a new device-level SEU-hardening technique is presented along with circuit-design techniques necessarily for its implementation. In Chapter 5, the circuit-level radiation-hardening techniques necessarily to mitigate the effects shown in Chapter 3 are developed and tested [32].
Finally, in Chapter 6, the performance of the SiGe HBT in a cryogenic testing environment is characterized to understand how the widely-varying temperatures of outer space may affect device performance.
Ultimately, the built-in performance, TID-tolerance, and now-developing SEU-hardness of the SiGe HBT make a compelling case for extreme environment electronics. The low-cost, high-yield, and maturity of Si manufacturing combine with modern bandgap engineering and modern CMOS to produce a high-quality, high-performance BiCMOS platform suitable for space-borne systems.
24
Ahmed, Adnan. "Study of Low-Temperature Effects in Silicon-Germanium Heterojunction Bipolar Transistor Technology." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7227.
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This thesis investigates the effects of low temperatures on Silicon Germanium (SiGe) Hterojunction Bipolar Transistors (HBT) BiCMOS technology. A comprehensive set of dc measurements were taken on first, second, third and fourth generation IBM SiGe technology over a range of temperatures (room temperature to 43K for first generation, and room temperature to 15K for the rest). This work is unique in the sense that this sort of comprehensive study of dc characteristics on four SiGe HBT technology generations over a wide range of temperatures has never been done before to the best of the authors knowledge.
25
Thomas, Dylan Buxton. "Silicon-germanium devices and circuits for high temperature applications." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33949.
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Using bandgap engineering, silicon-germanium (SiGe) BiCMOS technology effectively combines III-V transistor performance with the cost and integration advantages associated with CMOS manufacturing. The suitability of SiGe technology for cryogenic and radiation-intense environments is well known, yet SiGe has been generally overlooked for applications involving extreme high temperature operation. This work is an investigation into the potential capabilities of SiGe technology for operation up to 300°C, including the development of packaging and testing procedures to enable the necessary measurements. At the device level, SiGe heterojunction bipolar transistors (HBTs), field-effect transistors (FETs), and resistors are verified to maintain acceptable functionality across the temperature range, laying the foundation for high temperature circuit design. This work also includes the characterization of existing bandgap references circuits, redesign for high temperature operation, validation, and further optimization recommendations. In addition, the performance of temperature sensor, operational amplifier, and output buffer circuits under extreme high temperature conditions is presented. To the author's knowledge, this work represents the first demonstration of functional circuits from a SiGe technology platform in ambient temperatures up to 300°C; furthermore, the optimized bandgap reference presented in this work is believed to show the best performance recorded across a 500°C range in a bulk-silicon technology platform.
26
Cui, Xian. "Efficient radio frequency power amplifiers for wireless communications." Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1195652135.
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"Matching properties and applications of compatible lateral bipolar transistors (CLBTs)." 2001. http://library.cuhk.edu.hk/record=b5895864.
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Hiu Yung Wong.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves 104-111).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgments --- p.iii
List of Figures --- p.ix
List of Tables --- p.xiii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation and Objectives --- p.1
Chapter 1.2 --- Contributions --- p.3
Chapter 1.3 --- Organization of the Thesis --- p.4
Chapter 2 --- Devices and Fabrication Processes --- p.5
Chapter 2.1 --- Introduction --- p.5
Chapter 2.2 --- BJTs --- p.6
Chapter 2.2.1 --- Structure and Modeling of BJTs --- p.6
Chapter 2.2.2 --- Standard BJT Process and BJT Characteristics --- p.7
Chapter 2.3 --- MOSFETs and Complementary MOS (CMOS) --- p.8
Chapter 2.3.1 --- Structure and Modeling of MOSFETs --- p.8
Chapter 2.3.2 --- Standard n-well CMOS Process and MOSFETs Charac- teristics --- p.11
Chapter 2.4 --- BiCMOS Technology --- p.13
Chapter 2.5 --- Summary --- p.14
Chapter 3 --- Matching Properties --- p.15
Chapter 3.1 --- Introduction --- p.15
Chapter 3.2 --- Importance of Matched Devices in IC Design --- p.15
Chapter 3.2.1 --- What is Matching? --- p.15
Chapter 3.2.2 --- Low-power Systems --- p.16
Chapter 3.2.3 --- Device Size Downward Scaling --- p.16
Chapter 3.2.4 --- Analog Circuits and Analog Computing --- p.17
Chapter 3.3 --- Measurement of Mismatch --- p.18
Chapter 3.3.1 --- Definitions and Statistics of Mismatch --- p.18
Chapter 3.3.2 --- Types of Mismatches --- p.20
Chapter 3.3.3 --- Matching Properties of MOSFETs --- p.23
Chapter 3.3.4 --- Matching Properties of BJTs and CLBTs --- p.27
Chapter 3.4 --- Summary --- p.30
Chapter 4 --- CMOS Compatible Lateral Bipolar Transistors (CLBTs) --- p.31
Chapter 4.1 --- Introduction --- p.31
Chapter 4.2 --- Structure and Operation --- p.32
Chapter 4.3 --- DC Model of CLBTs --- p.34
Chapter 4.4 --- Residual Gate Effect in Accumulation --- p.35
Chapter 4.5 --- Main Characteristics of CLBTs --- p.37
Chapter 4.5.1 --- Low Early Voltage --- p.37
Chapter 4.5.2 --- Low Lateral Current Gain at High Current Levels --- p.38
Chapter 4.5.3 --- Other Issues --- p.39
Chapter 4.6 --- Enhanced CLBTs with Cascode Circuit --- p.40
Chapter 4.7 --- Applications --- p.41
Chapter 4.8 --- Design and Layout of CLBTs --- p.42
Chapter 4.9 --- Experimental Results of Single pnp CLBT； nMOSFET and pMOSFET --- p.44
Chapter 4.9.1 --- CLBT Gains --- p.46
Chapter 4.9.2 --- Gate Voltage Required for Pure Bipolar Action --- p.47
Chapter 4.9.3 --- I ´ؤ V and Other Characteristics of Bare pnp CLBTs --- p.49
Chapter 4.9.4 --- Transfer Characteristics of a Cascoded pnp CLBT --- p.50
Chapter 4.9.5 --- Transfer Characteristics of an nMOSFET --- p.51
Chapter 4.9.6 --- Transfer Characteristics of Cascoded and Bare CLBTs Operating as pMOSFETs --- p.52
Chapter 4.10 --- Summary --- p.53
Chapter 5 --- Experiments on Matching Properties --- p.54
Chapter 5.1 --- Introduction --- p.54
Chapter 5.2 --- Objectives --- p.55
Chapter 5.3 --- Technology --- p.57
Chapter 5.4 --- Design of Testing Arrays --- p.57
Chapter 5.4.1 --- nMOSFET Array --- p.57
Chapter 5.4.2 --- pnp CLBT Array --- p.59
Chapter 5.5 --- Design of Input and Output Pads (I/O Pads) --- p.62
Chapter 5.6 --- Shift Register --- p.62
Chapter 5.7 --- Experimental Equipment --- p.63
Chapter 5.8 --- Experimental Setup for Matching Properties Measurements --- p.65
Chapter 5.8.1 --- Setup for Measuring the Mismatches of the Devices --- p.65
Chapter 5.8.2 --- Testing Procedures --- p.68
Chapter 5.8.3 --- Data Analysis --- p.68
Chapter 5.9 --- Matching Properties --- p.69
Chapter 5.9.1 --- Matching Properties of nMOSFETs --- p.69
Chapter 5.9.2 --- Matching Properties of CLBTs --- p.71
Chapter 5.9.3 --- Matching Properties of pMOSFETs --- p.73
Chapter 5.9.4 --- "Comments on the Matching Properties of CLBT, nMOSFET, and pMOSFET" --- p.76
Chapter 5.9.5 --- "Mismatch in CLBT, nMOSFET, and pMOSFET Cur- rent Mirrors" --- p.77
Chapter 5.10 --- Summary --- p.79
Chapter 6 --- Conclusion --- p.80
Chapter A --- Floating Gate Technology --- p.82
Chapter A.1 --- Floating Gate --- p.82
Chapter A.2 --- Tunnelling --- p.83
Chapter A.3 --- Hot Electron Effect --- p.85
Chapter A.4 --- Summary --- p.86
Chapter B --- A Trimmable Transconductance Amplifier --- p.87
Chapter B.1 --- Introduction --- p.87
Chapter B.2 --- Trimmable Transconductance Amplifier using Floating Gate Com- patible Lateral Bipolar Transistors (FG-CLBTs) --- p.87
Chapter B.2.1 --- Residual Gate Effect and Collector Current Modulation --- p.89
Chapter B.2.2 --- Floating Gate CLBTs --- p.92
Chapter B.2.3 --- Electron Tunnelling --- p.93
Chapter B.2.4 --- Hot Electron Injection --- p.94
Chapter B.2.5 --- Experimental Results of the OTA --- p.94
Chapter B.2.6 --- Experimental Results of the FGOTA --- p.96
Chapter B.3 --- Summary --- p.97
Chapter C --- AMI-ABN 1.5μm n-well Process Parameters (First Batch) --- p.98
Chapter D --- AMI-ABN 1.5μm n-well Process Parameters (Second Batch) --- p.101
Bibliography --- p.104
28
Rhee, Se Jong. "Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: physics, reliability, and process development." Thesis, 2005. http://hdl.handle.net/2152/2287.
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Qiu, Xiangping. "MOSFET-only predictive track and hold circuit." Thesis, 1997. http://hdl.handle.net/1957/34941.
Full textAbstract:
High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp
predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process.Graduation date: 1997
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Warren, Steven Benjamin. "CMOS Integration of Single-Molecule Field-Effect Transistors." Thesis, 2016. https://doi.org/10.7916/D8K937R9.
Full textAbstract:
Point functionalized carbon nanotubes have recently demonstrated the ability to serve as single-molecule biosensors. Operating as single-molecule Field-Effect Transistors (smFET), the sensors have been used to explore activity ranging in scope from DNA hybridization kinetics to DNA polymerase functionality. High signal levels and an all-electronic label-free transduction mechanism make the smFET an attractive candidate for next-generation medical diagnostics platforms and high-bandwidth basic science research studies. In this work, carbon nanotubes are integrated onto a custom designed CMOS chip. Integration enables arraying many devices for measurement, providing the requisite scale-up for any commercial application of smFETs. Integration also provides substantial benefits towards achieving high bandwidths through the reduction of electrical parasitics. In a first exploitation of these high-bandwidth measurement capabilities, integrated devices are electrically characterized over a 1-MHz bandwidth. Functionalization through electrochemical oxidation of the devices is observed with microsecond temporal resolution, revealing complex reaction pathways with resolvable scattering signatures. High rate random telegraph noise (RTN) is observed in certain oxidized devices, further illustrating the temporal resolution of the integrated sensing platform.
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Wen, Huang-Chun. "Systematic evaluation of metal gate electrode effective work function and its influence on device performance in CMOS devices." Thesis, 2006. http://hdl.handle.net/2152/3511.
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Zhou, Jianjun J. "CMOS low noise amplifier design utilizing monolithic transformers." Thesis, 1998. http://hdl.handle.net/1957/33529.
Full textAbstract:
Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low
cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA
is the inaccurate high-frequency noise model of the MOSFET implemented in circuit
simulators such as SPICE. Silicon-based monolithic inductors are another bottleneck in RF
CMOS design due to their poor quality factor.
In this thesis, a CMOS implementation of a fully-integrated differential LNA is
presented. A small-signal noise circuit model that includes the two most important noise
sources of the MOSFET at radio frequencies, channel thermal noise and induced gate
current noise, is developed for CMOS LNA analysis and simulation. Various CMOS LNA
architectures are investigated. The optimization techniques and design guidelines and
procedures for an LC tuned CMOS LNA are also described.
Analysis and modeling of silicon-based monolithic inductors and transformers are
presented and it is shown that in fully-differential applications, a monolithic transformer
occupies less die area and achieves a higher quality factor compared to two independent
inductors with the same total effective inductance. It is also shown that monolithic
transformers improve the common-mode rejection of the differential circuits.Graduation date: 1999
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Ok, Injo 1974. "A study on electrical and material characteristics of hafnium oxide with silicon interface passivation on III-V substrate for future scaled CMOS technology." Thesis, 2008. http://hdl.handle.net/2152/3974.
Full textAbstract:
The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO₂ gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO₂ (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x10¹⁰ eV⁻¹cm⁻²), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO₂ film. HfO₂ based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility.text
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Ajayan, K. R. "Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology." Thesis, 2014. http://etd.iisc.ernet.in/2005/3516.
Full textAbstract:
Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work
In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty.
In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range.
In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model
In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.
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Fan, Xiaofeng 1978. "Quantum corrected full-band semiclassical Monte Carlo simulation research of charge transport in Si, stressed-Si, and SiGe MOSFETs." Thesis, 2006. http://hdl.handle.net/2152/3451.
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Zaman, Rownak Jyoti. "A comprehensive study of 3D nano structures characteristics and novel devices." 2008. http://hdl.handle.net/2152/15350.
Full textAbstract:
Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques.text
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Yoo, Byungwook 1975. "New platforms for electronic devices: n-channel organic field-effect transistors, complementary circuits, and nanowire transistors." Thesis, 2007. http://hdl.handle.net/2152/3165.
Full textAbstract:
This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain.text
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Thejas, *. "Exploration of Displacement Detection Mechanisms in MEMS Sensors." Thesis, 2015. http://etd.iisc.ernet.in/handle/2005/2760.
Full textAbstract:
MEMS Sensors are widely used for sensing inertial displacements. The displacements arising out of acceleration /Coriolis effect are typically in the range of 1 nm-1 m. This work investigates the realization of high resolution MEMS inertial sensors using novel displacement sensing mechanisms.
Capacitance sensing ASIC is developed as part of conventional electronics interface with MEMS sensor under the conventional CMOS-MEMS integration strategy. The capacitance sense ASIC based on Continuous Time Voltage scheme with coherent and non-coherent demodulation is prototyped on AMS 0.35 m technology. The ASIC was tested to sense C = 3.125 fF over a base of 2 pF using on-chip built-in test capacitors. Dynamic performance of this ASIC was validated by interfacing with a DaCM MEMS accelerometer. 200milli-g of acceleration (equivalent to a C = 2.8 fF) over an input frequency of 20Hz is measurable using the developed ASIC. The observed sensitivity is 90mV/g. The ASIC has several programmable features such as variation in trim capacitance (3.125 fF-12.5 pF), bandwidth selection (500 Hz-20 kHz) and variable gain options (2-100).
Capacitance detection, a dominant sensing principle in MEMs sensors, experiences inherent limitation due to the role of parasitics when the displacements of interest are below 5 nm range. The capacitive equivalence ( C) for the range of displacements of the order of 5 nm and below would vary in the range atto-to-zepto farad. Hence there is a need to explore alternative sensing schemes which preferably yield higher sensitivity (than those offered by the conventional integration schemes) and are based on the principle of built-in transduction to help overcome the influence of parasitics on sensitivity.
In this regard, 3 non-conventional architectures are explored which fall under the direct integration classification namely:
(a) Sub-threshold based sensing
(b) Fringe field based sensing and
(c) Tunneling current based sensing.
a) In Sub-threshold based sensing, FET with a suspended gate is used for displacement sensing. The FET is biased in the sub-threshold region of operation. The exponential modulation of drain current for a change in displacement of 1 nm is evaluated using TCAD, and the in uence of initial air-gap variation on the sensitivity factor ( ID=ID) is brought out.
For 1% change in air gap displacement (i.e., TGap/TGap, the gap variation resulting due to the inertial force / mass loading) nearly 1050% change in drain current( ID=ID) is observed (considering initial air gaps of the order 100 nm). This validates the high sensitivity offered by the device in this regime of operation. A comparison of sensitivity estimate using the capacitive equivalence model and TCAD simulated model for different initial air-gaps in a FD-SOI FET is brought out. The influence of FDSOI FET device parameters on sensitivity, namely the variation of TSi, TBox, NA and TGap are explored.
CMOS compatibility and fabrication feasibility of this architecture was looked into by resorting to the post processing approach used for validating the sub-threshold bias concept. The IMD layers of the Bulk FETs fabricated through AMS 0.35 technology were etched using BHF and IPA mixture to result in a free standing metal (Al) layers acting as the suspended gate. The performance estimate is carried out considering specific Equivalent Gap Thickness (EGT) of 573 nm and 235 nm, to help overcome the role of coupled electrostatics in influencing the sensitivity metric. The sensitivity observed by biasing this post processed bulk FET in sub-threshold is 114% ( ID=ID change) for a 59% ( d/d change). The equivalent C in this case is 370 aF.
b) In Fringe eld based sensing approach, a JunctionLess FET (JLFET) is used as a depletion mode device and an out-of-plane gate displacement would help modulate the device pinch-o voltage due to fringe field coupling. The resulting change in the gate fringe field due to this displacement modulates the drain current of the JunctionLess FET. The displacement induced fringe field change (relative to the FET channel) brings about a distinct shift in the ID-VG characteristics of the JLFET. For displacement
d = 2 nm, the JLFET with a channel doping of ND = 8X1018cm 3 and a bias point of VG = -47.7 V, 98% enhancement in sensitivity is observed in 3D TCAD simulations. The equivalent C in this case is 29 zF. The role of ground-planes in the device operation is explored.
c) In the tunneling current based sensing approach, the beams fabricated using the SOI-MUMPS process are FIB milled so as to create very ne air gaps of the order of nearly 85 nm. Under high electric fields of the order > 8 MV/cm, the lateral displacement based tunneling sensor offers enhanced change in sensitivity for an induced external force at a fixed DC bias. When integrated as an array with varying electrode overlap, this technique can track displacements over a wide range. With the initial beam overlap as 1.2 m, for a lateral displacement of 1.2 m, a 100% change in sensitivity ( ID=ID) is observed. The effect of fringe field can be completely neglected here unlike its capacitive beam equivalent.