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Journal articles on the topic 'Metal oxide semiconductor field-effect transistor Metal oxide semiconductors, Complementary'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 February 2022

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1

John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.

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2

Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

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3

Peng, J. W., N. Singh, G. Q. Lo, M. Bosman, C. M. Ng, and S. J. Lee. "Germanium Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal–Oxide–Semiconductor-Compatible Process." IEEE Transactions on Electron Devices 58, no. 1 (January 2011): 74–79. http://dx.doi.org/10.1109/ted.2010.2088125.

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4

Tao, Meng, Robert W. Wallace, C. Rinn Cleavelin, and Rick L. Wise. "The Chalkboard: Silicon Complementary Metal-Oxide-Semiconductor Field-Effect Transistor." Electrochemical Society Interface 14, no. 2 (June 1, 2005): 26–27. http://dx.doi.org/10.1149/2.f03052if.

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5

Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

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This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

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6

Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.

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7

Bennett, Brian R., Mario G. Ancona, and J. Brad Boos. "Compound Semiconductors for Low-Power p-Channel Field-Effect Transistors." MRS Bulletin 34, no. 7 (July 2009): 530–36. http://dx.doi.org/10.1557/mrs2009.141.

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AbstractResearch in n-channel field-effect transistors based upon III–V compound semiconductors has been very productive over the last 30 years, with successful applications in a variety of high-speed analog circuits. For digital applications, complementary circuits are desirable to minimize static power consumption. Hence, p-channel transistors are also needed. Unfortunately, hole mobilities are generally much lower than electron mobilities for III–V compounds. This article reviews the recent work to enhance hole mobilities in antimonide-based quantum wells. Epitaxial heterostructures have been grown with the channel material in 1–2% compressive strain. The strain modifies the valence band structure, resulting in hole mobilities as high as 1500 cm2/Vs. The next steps toward an ultra-low-power complementary metal oxide semiconductor technology will include development of a compatible insulator technology and integration of n- and p-channel transistors.

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8

Liang, Hsiao-Bin, Yi-Hsun Tsou, Yo-Sheng Lin, and Chi-Chen Chen. "Uniformly Distributed Wideband Metal–Oxide–Semiconductor Field-Effect Transistor Model for Complementary Metal–Oxide–Semiconductor Radio-Frequency Integrated Cirsuits Applications." Japanese Journal of Applied Physics 47, no. 2 (February 15, 2008): 807–13. http://dx.doi.org/10.1143/jjap.47.807.

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9

Lee, Kitae, Sihyun Kim, Daewoong Kwon, and Byung-Gook Park. "Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation." Applied Sciences 10, no. 14 (July 20, 2020): 4977. http://dx.doi.org/10.3390/app10144977.

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Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.

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10

Tsai, Yu-Yang, Chun-Yu Kuo, Bo-Chang Li, Po-Wen Chiu, and Klaus Y. J. Hsu. "A Graphene/Polycrystalline Silicon Photodiode and Its Integration in a Photodiode–Oxide–Semiconductor Field Effect Transistor." Micromachines 11, no. 6 (June 17, 2020): 596. http://dx.doi.org/10.3390/mi11060596.

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In recent years, the characteristics of the graphene/crystalline silicon junction have been frequently discussed in the literature, but study of the graphene/polycrystalline silicon junction and its potential applications is hardly found. The present work reports the observation of the electrical and optoelectronic characteristics of a graphene/polycrystalline silicon junction and explores one possible usage of the junction. The current–voltage curve of the junction was measured to show the typical exponential behavior that can be seen in a forward biased diode, and the photovoltage of the junction showed a logarithmic dependence on light intensity. A new phototransistor named the “photodiode–oxide–semiconductor field effect transistor (PDOSFET)” was further proposed and verified in this work. In the PDOSFET, a graphene/polycrystalline silicon photodiode was directly merged on top of the gate oxide of a conventional metal–oxide–semiconductor field effect transistor (MOSFET). The magnitude of the channel current of this phototransistor showed a logarithmic dependence on the illumination level. It is shown in this work that the PDOSFET facilitates a better pixel design in a complementary metal–oxide–semiconductor (CMOS) image sensor, especially beneficial for high dynamic range (HDR) image detection.

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11

Lee, Te Liang, Ming Tsang Tsai, Ya Chin King, and Chrong Jung Lin. "A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process." Japanese Journal of Applied Physics 52, no. 4S (April 1, 2013): 04CC16. http://dx.doi.org/10.7567/jjap.52.04cc16.

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12

Toumazou, Christofer, Tan Sri Lim Kok Thay, and Pantelis Georgiou. "A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130112. http://dx.doi.org/10.1098/rsta.2013.0112.

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Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

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13

KUMAR, K. KEERTI, and N. BHEEMA RAO. "POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450109. http://dx.doi.org/10.1142/s0218126614501096.

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In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

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14

Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.

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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.

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15

Han, Joon-Kyu, Jungyeop Oh, Gyeong-Jun Yun, Dongeun Yoo, Myung-Su Kim, Ji-Man Yu, Sung-Yool Choi, and Yang-Kyu Choi. "Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware." Science Advances 7, no. 32 (August 2021): eabg8836. http://dx.doi.org/10.1126/sciadv.abg8836.

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Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

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16

Zhang, Yannan, Ke Han, and and Jiawei Li. "A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator." Micromachines 11, no. 2 (February 21, 2020): 223. http://dx.doi.org/10.3390/mi11020223.

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Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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17

Aoki, Hitoshi, and Akira Matsuzawa. "n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Modeling in Forward Body Bias Condition for Low Voltage Complementary Metal–Oxide–Semiconductor Circuits Design." Japanese Journal of Applied Physics 51 (March 21, 2012): 044301. http://dx.doi.org/10.1143/jjap.51.044301.

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18

Aoki, Hitoshi, and Akira Matsuzawa. "n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Modeling in Forward Body Bias Condition for Low Voltage Complementary Metal–Oxide–Semiconductor Circuits Design." Japanese Journal of Applied Physics 51, no. 4R (April 1, 2012): 044301. http://dx.doi.org/10.7567/jjap.51.044301.

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19

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (May 20, 2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nanodimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

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20

Rangel, Ricardo Cardoso, Katia R. A. Sasaki, Leonardo Shimizu Yojo, and João Antonio Martino. "Fabrication and Electrical Characterization of Ultra-Thin Body and BOX (UTBB) Back Enhanced SOI (BESOI) pMOSFET." Journal of Integrated Circuits and Systems 15, no. 1 (May 26, 2020): 1–6. http://dx.doi.org/10.29292/jics.v15i1.107.

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This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

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21

Yeh, Wen-Kuan, and Shuo-Mao Chen. "Efficient Suppression of Substrate Noise Coupling in Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor Technology." Japanese Journal of Applied Physics 43, no. 4B (April 27, 2004): 1695–98. http://dx.doi.org/10.1143/jjap.43.1695.

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22

Mendiratta, Namrata, Suman Lata Tripathi, Sanjeevikumar Padmanaban, and Eklas Hossain. "Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications." Applied Sciences 10, no. 7 (April 5, 2020): 2499. http://dx.doi.org/10.3390/app10072499.

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The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.

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23

Shimizu, Masahiro, Takashi Kuroi, Masahide Inuishi, Hideaki Arima, Haruhiko Abe, and Chihiro Hamaguchi. "Subquarter-micrometer Dual Gate Complementary Metal Oxide Semiconductor Field Effect Transistor with Ultrathin Gate Oxide of 2 nm." Japanese Journal of Applied Physics 37, Part 1, No. 11 (November 15, 1998): 5926–31. http://dx.doi.org/10.1143/jjap.37.5926.

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24

Seo, Sang-Ho, Sung-Ho Lee, Mi-Young Do, Jang-Kyoo Shin, and Pyung Choi. "Highly and Variably Sensitive Complementary Metal Oxide Semiconductor Active Pixel Sensor Using P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector with Transfer Gate." Japanese Journal of Applied Physics 45, no. 4B (April 25, 2006): 3470–74. http://dx.doi.org/10.1143/jjap.45.3470.

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25

Ohtou, Tetsu, Toshiharu Nagumo, and Toshiro Hiramoto. "Variable Body Effect Factor Fully Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor for Ultra Low-Power Variable-Threshold-Voltage Complementary Metal Oxide Semiconductor Applications." Japanese Journal of Applied Physics 43, no. 6A (June 9, 2004): 3311–14. http://dx.doi.org/10.1143/jjap.43.3311.

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Akiyama, T., U. Staufer, N. F. de Rooij, D. Lange, C. Hagleitner, O. Brand, H. Baltes, A. Tonin, and H. R. Hidber. "Integrated atomic force microscopy array probe with metal–oxide–semiconductor field effect transistor stress sensor, thermal bimorph actuator, and on-chip complementary metal–oxide–semiconductor electronics." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 18, no. 6 (2000): 2669. http://dx.doi.org/10.1116/1.1327299.

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27

Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

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Daus, Alwin, Songyi Han, Stefan Knobelspies, Giuseppe Cantarella, and Gerhard Tröster. "Ge2Sb2Te5 p-Type Thin-Film Transistors on Flexible Plastic Foil." Materials 11, no. 9 (September 9, 2018): 1672. http://dx.doi.org/10.3390/ma11091672.

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In this work, we show the performance improvement of p-type thin-film transistors (TFTs) with Ge 2 Sb 2 Te 5 (GST) semiconductor layers on flexible polyimide substrates, achieved by downscaling of the GST thickness. Prior works on GST TFTs have typically shown poor current modulation capabilities with ON/OFF ratios ≤20 and non-saturating output characteristics. By reducing the GST thickness to 5 nm, we achieve ON/OFF ratios up to ≈300 and a channel pinch-off leading to drain current saturation. We compare the GST TFTs in their amorphous (as deposited) state and in their crystalline (annealed at 200 °C) state. The highest effective field-effect mobility of 6.7 cm 2 /Vs is achieved for 10-nm-thick crystalline GST TFTs, which have an ON/OFF ratio of ≈16. The highest effective field-effect mobility in amorphous GST TFTs is 0.04 cm 2 /Vs, which is obtained in devices with a GST thickness of 5 nm. The devices remain fully operational upon bending to a radius of 6 mm. Furthermore, we find that the TFTs with amorphous channels are more sensitive to bias stress than the ones with crystallized channels. These results show that GST semiconductors are compatible with flexible electronics technology, where high-performance p-type TFTs are strongly needed for the realization of hybrid complementary metal-oxide-semiconductor (CMOS) technology in conjunction with popular n-type oxide semiconductor materials.

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29

Toledo, Pedro, Hamilton Klimach, David Cordova, Sergio Bampi, and Eric Fabris. "MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 103–12. http://dx.doi.org/10.29292/jics.v10i2.411.

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In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.

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Moser, Nicolas, Chi Leng Leong, Yuanqi Hu, Chiara Cicatiello, Sally Gowers, Martyn Boutelle, and Pantelis Georgiou. "Complementary Metal–Oxide–Semiconductor Potentiometric Field-Effect Transistor Array Platform Using Sensor Learning for Multi-ion Imaging." Analytical Chemistry 92, no. 7 (March 6, 2020): 5276–85. http://dx.doi.org/10.1021/acs.analchem.9b05836.

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Liao, M. H., C. W. Liu, Lingyen Yeh, T. L. Lee, and M. S. Liang. "Gate width dependence on backscattering characteristics in the nanoscale strained complementary metal-oxide-semiconductor field-effect transistor." Applied Physics Letters 92, no. 6 (February 11, 2008): 063506. http://dx.doi.org/10.1063/1.2839402.

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32

Takei, Munehisa, Hiroki Hashiguchi, Takuya Yamaguchi, Daisuke Kosemura, Kohki Nagata, and Atsushi Ogura. "Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy." Japanese Journal of Applied Physics 51 (April 20, 2012): 04DA04. http://dx.doi.org/10.1143/jjap.51.04da04.

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33

Takei, Munehisa, Hiroki Hashiguchi, Takuya Yamaguchi, Daisuke Kosemura, Kohki Nagata, and Atsushi Ogura. "Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy." Japanese Journal of Applied Physics 51, no. 4S (April 1, 2012): 04DA04. http://dx.doi.org/10.7567/jjap.51.04da04.

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34

Huang, Chien-Chao, Hao-Yu Chen, and Sanboh Lee. "An Efficient Threshold Voltage Control in Complementary Metal–Oxide–Semiconductor Field Effect Transistor Using Spacer Stress Engineering." Japanese Journal of Applied Physics 49, no. 7 (July 5, 2010): 070204. http://dx.doi.org/10.1143/jjap.49.070204.

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35

Li, Yiming, Chieh-Yang Chen, Min-Hui Chuang, and Pei-Jung Chao. "Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits." Materials 12, no. 9 (May 8, 2019): 1492. http://dx.doi.org/10.3390/ma12091492.

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In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.

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36

Okamoto, Mitsuo, Miwako Iijima, Tsutomu Yatsuo, Kenji Fukuda, and Hajime Okumura. "Effect of Doping Concentration in Buried-Channel NMOSFETs on Electrical Properties of 4H-SiC CMOS Devices." Materials Science Forum 645-648 (April 2010): 995–98. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.995.

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We fabricated 4H-silicon carbide (SiC) Complementary Metal-Oxide-Semiconductor (CMOS) devices with wet gate oxidation processing. The channel properties of n-channel MOS Field-Effect-Transistor (NMOS) were controlled by buried channel (BC) structure. The electrical properties of CMOS devices depended on the doping concentration of the BC-layer (Nbc) for NMOS. The SiC CMOS inverters with high Nbc indicated fast operation at the delay time (Td) of 4.8 ns for supply voltage of 15 V. To our knowledge, Td obtained in this study is the smallest among the reported values for SiC CMOS inverters.

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37

Choi, Kyu-Jin, Jae-Hyun Park, Seong-Kyun Kim, and Byung-Sung Kim. "K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology." Electronics 10, no. 8 (April 8, 2021): 890. http://dx.doi.org/10.3390/electronics10080890.

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A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

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38

XUAN, G., J. KOLODZEY, V. KAPOOR, and G. GONYE. "ELECTRICAL EFFECTS OF DNA MOLECULES ON SILICON FIELD EFFECT TRANSISTOR." International Journal of High Speed Electronics and Systems 14, no. 03 (September 2004): 684–89. http://dx.doi.org/10.1142/s0129156404002673.

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Much research has been devoted to the field of DNA detection for biotechnology and medical diagnostics. Conventionally, this has involved lab-scale large instruments such as fluorescent microscope, with DNA binding and tagging. Recently, however, the possibility of label-free, rapid, sensitive and miniaturized DNA detection electronically has attracted increasing interest in the field. To investigate the feasibility of DNA detection by the semiconductor field effect without tagging or binding agents, we studied the effects of DNA molecules directly on the gate oxide of field effect transistors (FET). DNA solution was deposited onto the gate region of conventional silicon FET devices without gate metal, and current-voltage measurements were performed. Our work showed that the presence of DNA molecules in an aqueous solution on the gate decreased channel current I ds and increased threshold voltage. With increasing concentration in the solution, the threshold voltage increased monotonically. We observed that the channel current was reduced systematically during the hybridization of complementary DNA strands. The mechanism that induced the threshold voltage shift is attributed to the negative charges the DNA molecules carry and to changes in work function (Fermi Energy). Our results showed the possibility that field effect transistors may provide a vehicle for a label-free, miniaturized and semiconductor-based DNA detector.

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39

Kikuchi, Yoshiaki, Hitoshi Wakabayashi, Masanori Tsukamoto, and Naoki Nagashima. "Dual Metal/High-kGate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness." Japanese Journal of Applied Physics 50, no. 8R (August 1, 2011): 084201. http://dx.doi.org/10.7567/jjap.50.084201.

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40

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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41

Kong, Jae-Sung, Hyo-Young Hyun, Sang-Ho Seo, and Jang-Kyoo Shin. "The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip." Optical Review 15, no. 6 (November 2008): 269–75. http://dx.doi.org/10.1007/s10043-008-0043-7.

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42

Chauhan, Manorama, Ravindra Singh Kushwah, Pavan Shrivastava, and Shyam Akashe. "Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits." International Journal of Nanoscience 13, no. 02 (April 2014): 1450012. http://dx.doi.org/10.1142/s0219581x14500124.

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In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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Chen, Zeqi, Jianping Hu, Hao Ye, and Zhufei Chu. "T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)." Micromachines 11, no. 1 (January 7, 2020): 64. http://dx.doi.org/10.3390/mi11010064.

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In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are on either side of the vertical channel. The T-shaped channel structure increases the coupling area between the top gate and the front and back gates, which improves the ability of the gate electrodes to control the channel. What’s more, it makes the top gate have almost the same control ability for the channel as the front gate and the back gate. This unique structure design brings a unique function in that the device is turned on only when two or three inputs are activated. Silvaco technology computer-aided design (TCAD) simulations are used to verify the current characteristics of the proposed Ti-TcFET. The current characteristics of the device are theoretically analyzed, and the results show that the theoretical analysis agrees with the TCAD simulation results. The proposed Ti-TcFET devices with three input terminals can be used to simplify the complex circuits in a compact style with reduced counts of transistors compared with the traditional complementary metal–oxide–semiconductor/ fin field-effect transistors (CMOS/FinFETs) with a single input terminal and thus provides a new idea for future circuit designs.

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44

Kikuchi, Yoshiaki, Hitoshi Wakabayashi, Masanori Tsukamoto, and Naoki Nagashima. "Dual Metal/High-$k$ Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness." Japanese Journal of Applied Physics 50, no. 8 (August 22, 2011): 084201. http://dx.doi.org/10.1143/jjap.50.084201.

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45

Zhao, Xiao Feng, Han Yu Guan, Mei Wei Lv, Yi Nan Bai, and Dian Zhong Wen. "Research of Magnetic Characteristics of the Split-Drain MAGFET Based on Nano-Polysilicon TFTs." Key Engineering Materials 645-646 (May 2015): 132–38. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.132.

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The split-drain magnetic field effect transistor (MAGFET) based on nanopolysilicon thin film transistor (TFT) is fabricated on <100> high resistivity silicon substrates by (complementary metal oxide semiconductor) CMOS technology in this paper. It contains source (S), drain1 (D1), drain2 (D2) and gate (G), and adopts nanopolysilicon thin films and nanopolysilicon/high resistivity silicon heterojunction interfaces as the magnetic field sensing layers. The influence of the channel size and shapes on the transistor, are studied to further improve its magnetic sensitivity. When the ratio of channel length and width (L/W) of MAGFET is 80 μm/160 μm, VDS=5.0 V, the MAGFET with convex channel has higher magnetic sensitivity than the rectangle and concave, the absolute current magnetic sensitivity SI and the absolute voltage magnetic sensitivity SV of the proposed sensor reach the maximum values, and are 0.021 mA/T and 55 mV/T, respectively.

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46

Chen, Hou-Yu, Chia-Yi Lin, Min-Cheng Chen, Chien-Chao Huang, and Chao-Hsin Chien. "Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal–Oxide–Semiconductor Technology." Japanese Journal of Applied Physics 50, no. 4S (April 1, 2011): 04DL05. http://dx.doi.org/10.7567/jjap.50.04dl05.

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47

Yeh, Wen-Kuan, Wen-Han Wang, Yean-Kuen Fang, and Fu-Liang Yang. "Hot-Carrier-Induced Degradation on 0.1 µm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor." Japanese Journal of Applied Physics 42, Part 1, No. 4B (April 30, 2003): 1993–98. http://dx.doi.org/10.1143/jjap.42.1993.

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48

Kim, Ji-Young, Cho-Rong Kim, Jaeyeop Lee, Won-Wook Park, Jae-Young Leem, Hyukhyun Ryu, Won-Jae Lee, et al. "Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device." Japanese Journal of Applied Physics 47, no. 10 (October 17, 2008): 7771–74. http://dx.doi.org/10.1143/jjap.47.7771.

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49

Chen, Hou-Yu, Chia-Yi Lin, Min-Cheng Chen, Chien-Chao Huang, and Chao-Hsin Chien. "Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal–Oxide–Semiconductor Technology." Japanese Journal of Applied Physics 50, no. 4 (April 20, 2011): 04DL05. http://dx.doi.org/10.1143/jjap.50.04dl05.

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50

Ohuchi, Kazuya, Kanna Adachi, Atsushi Murakoshi, Akira Hokazono, Takahisa Kanemura, Nobutoshi Aoki, Masahito Nishigohri, Kyoichi Suguro, and Yoshiaki Toyoshima. "Ultrashallow Junction Formation for Sub-100 nm Complementary Metal-Oxide-Semiconductor Field-Effect Transistor by Controlling Transient Enhanced Diffusion." Japanese Journal of Applied Physics 40, Part 1, No. 4B (April 30, 2001): 2701–5. http://dx.doi.org/10.1143/jjap.40.2701.

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