Dissertations / Theses: 'Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)'

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Lin, Xinnan. "Double gate MOSFET technology and applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.

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李華剛 and Eddie Herbert Li. "Narrow-channel effect in MOSFET." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.

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Peters, Chris (Christopher Joseph) Carleton University Dissertation Engineering Electrical. "MOSFET based gamma radiation detector." Ottawa, 1992.

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Budihardjo, Irwan Kukuh. "A charge based power MOSFET model /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/5975.

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Singh, Jagar. "Technology, characteristics, and modeling of large-grain polysilicon MOSFET /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20SINGH.

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Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.

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Baird, John Malcolm Edward. "A micro processor based A.C. drive with a Mosfet inverter." Thesis, Cape Technikon, 1991. http://hdl.handle.net/20.500.11838/1119.

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Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1991
A detailed study into the development of a three phase motor drive, inverter and microprocessor controller using a scalar control method. No mathematical modelling of the system was done as the drive was built around available technology. The inverter circuit is of a Vo~tage source inverter configuration whicp uses MOSFETs switching at a base frequency of between 1.2 KHz and 2 KHz. Provision has been made for speed control and dynamic braking for special applications, since the drive is not going to be put into a specific application as yet, it was felt that only a basic control should be implemented and space should be left for special requests from prospective customers. The pulses for the inverter are generated from the HEF 4752 I.e. under the control of the micro processor thus giving the processor full control over the inverter and allowing it to change almost any parameter at any time. Although the report might seem to cover a lot of unimportant ground it is imperative that the reader is supplied with the back-ground information in order to understand where A.e. drives failed in the past and where A.e. drives are heading in the future. As well as where this drive seeks to use available technology to the best advantage.

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Bjeletich, Peter John. "Characterization of heteroepitaxial silicon germanium carbon layers for metal oxide semiconductor field effect transistor (MOSFET) applications /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2004. http://uclibs.org/PID/11984.

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Thesis (Ph. D.)--University of California, Davis, 2005.
Degree granted in Electrical Engineering. Dissertation completed in 2004; degree granted in 2005. Also available via the World Wide Web. (Restricted to UC campuses)

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Man, Tsz Yin. "One dimensional quantum mechanical transport in double-gate MOSFET /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20MAN.

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Yoon, Kwang Sub. "A precision analog small-signal model for submicron MOSFET devices." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14935.

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Yin, Chunshan. "Source/drain and gate design of advanced MOSFET devices /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20YIN.

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Bordelon, John H. "A large-signal model for the RF power MOSFET." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15048.

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Tuladhar, Looja R. "Resonant power MOSFET drivers for LED lighting /." Connect to resource online, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1264709029.

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Kong, Frederick. "Silicon-on-sapphire MOSFET parameter extraction by small-signal measurement /." [St. Lucia, Qld.], 2002. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17051.pdf.

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Kulkarni, Anish S. "Study of Tunable Analog Circuits Using Double Gate Metal Oxide Semiconductor Field Effect Transistors." Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1234552603.

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Waseem, Akbar. "Effect of gate length in enhancing current in a silicon nanowire wrap around gate MOSFET." Diss., Columbia, Mo. : University of Missouri-Columbia, 2006. http://hdl.handle.net/10355/5878.

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Thesis (M.S.)--University of Missouri-Columbia, 2006.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 14, 2007) Vita. Includes bibliographical references.

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Yen, Chi-min 1949. "Two-dimensional simulation of power MOSFET near breakdown." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276695.

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A simulation program has been developed to facilitate the investigation and analysis of power semiconductor devices under the reverse-bias condition. The electrostatic potential distribution is solved by using Poisson's equation alone, with particular attention to the neighborhood of avalanche breakdown. Because of its generality and efficiency, the program emerges as a powerful engineering tool for the design of power devices incorporating special junction termination techniques. Results are presented for a DMOS structure to illustrate the improvement in breakdown voltage when a field plate is applied. Numerical solution techniques for solving elliptic partial differential equations in a multi-material domain are discussed. The discretization of this domain is nonuniform in general due to its highly nonuniform physical parameters. By careful selection of grid lines near interfaces, the difference equation coefficients are considerably simplified. The resultant matrix of coefficients is symmetric even though Neumann boundary conditions are specified.

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Tsui, Kenneth Kin Pun. "RF characterization and modeling of MOSFET power amplifier in wireless communication /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20TSUI.

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Wang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.

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Murali, Raghunath. "Scaling opportunities for bulk accumulation and inversion MOSFETs for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/submitted/etd-02132004-173432/unrestricted/murali%5FRaghunath%5F405%5F.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.
Hess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).

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Jeon, Yongjoo. "High-k gate dielectric for 100 nm MOSFET application /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004296.

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Quinones, Eduardo Jose. "Heterojunction MOSFET devices using column IV alloys grown by UHVCVD /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Linewih, Handoko, and h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET." Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.

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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

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Linewih, Handoko. "Design and Application of SiC Power MOSFET." Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.

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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
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25

Davis, Kenneth Ralph 1964. "Two-dimensional simulation of the effects of total dose ionizing radiation on power-MOSFET breakdown." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277053.

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The effects of ionizing radiation on the breakdown-voltage degradation of power-MOSFET termination structures were examined through two-dimensional simulation. A wide variety of sensitivity to surface-charge density was found for various devices employing floating field rings and/or equipotential field plates. Termination structures that were both insensitive to surface charge and possessed a high breakdown voltage were identified. The results were compared with measurements made on selected structures. The principal ionizing radiation damaging mechanisms in MOS devices are discussed. Modifications made to an existing simulation program in order to simulate these complex field ring and field plate structures are described. Background information into how these termination structures improve the breakdown voltage and their sensitivities to positive interface charge buildup is investigated.

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Cheong, Kuan Yew, and n/a. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material." Griffith University. School of Microelectronic Engineering, 2004. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050115.101233.

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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1][7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metaloxidesemiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10][15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridationoxidationnitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitancetransient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiCSiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiCSiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10][16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metaloxide semiconductor fieldeffecttransistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.

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Cheong, Kuan Yew. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material." Thesis, Griffith University, 2004. http://hdl.handle.net/10072/367177.

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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Faculty of Engineering and Information Technology
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Zhou, Sida. "Mobility Modeling and Simulation of SOI Si1-x Gex p-MOSFET." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4954.

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With increasing demand for complex and faster circuits, CMOS technologies are progressing towards the deep-submicron level. Process complexity increases dramatically, and costly techniques are to be developed to create dense field isolation and shallow junctions. Silicon-On-Insulator (SOI) may solve some of these problems. On the other hand, strained Si 1_xGex layers have been successfully grown on Si substrates and demonstrated much higher hole mobility than bulk Si. This can be used to build high-mobility p-MOSFET with a buried Si 1_xGex channel. A high mobility p-MOSFET would improve both the circuit speed and the level of integration. The purpose of the present study was to model and simulate the effective mobility (μeff) of SOI Si 1-xGex p-MOSFET, and to investigate the suitability of local mobility models provided by simulator MEDICI for studying SOI Si 1_xGex p-MOSFET. The simulation is performed by using the two-dimensional device simulation program (MEDICI). The design parameters, such as Si-cap thickness, Ge profile and back-gate bias, were also investigated. A long channel (6μ) and a short channel (0.25μ) SOI and bulk Si 1_xGex p MOSFET were used for the study. Simulation reveals good effective mobility μeff match with experimental results if Si Ge channel of p-MOSFET can simply be treated like a bulk silicon with mobility 250cm2 /Vs. Mobility models provided by MEDICI are two types: a) mobility model (SRFMOB2) that is dependent on transverse electric field only at Si/ Si02 interface, which means that the effective mobility is a function of grid spacing at Si/ Si02 interface, and b) mobility models (PRPMOB, LSMMOB and HPMOB) that are dependent on transverse electric field anywhere in the device. PRPMOB and LSMMOB produce very good μef f and are insensitive to the grid spacing. HP MOB gives slight over estimation of effective mobility μef f. Silicon cap thickness can significantly influence the effective mobility μef f. In general, the thin silicon cap have better effective mobility μef f, but it is limited by manufacturing process. Graded Si 1_:z:Ge:z: channel presents nearly 100% improvement of effective mobility μeff for p-MOSFET over its bulk counterpart. This improvement is sustained up to gate voltage of 2.5 V. Simulation also indicates that large improvement of effective mobility μef f requires higher Ge concentration at the top of SiGe channel with steep grading. The influence of back-gate bias on μeff is small, hence, SOI SiGe MOSFET is well suited to building CMOS circuits.

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Nadimi, Ebrahim. "Quantum Mechanical and Atomic Level ab initio Calculation of Electron Transport through Ultrathin Gate Dielectrics of Metal-Oxide-Semiconductor Field Effect Transistors." Doctoral thesis, Universitätsbibliothek Chemnitz, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200800477.

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The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigated
Die vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden

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Bayimissa, Khader Destaing Mananga. "Characterisation of radiation effects on power system components for cubesats." Thesis, Cape Peninsula University of Technology, 2015. http://hdl.handle.net/20.500.11838/2191.

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Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology.
Front-end power converters for nanosatellite applications demand better performance in accurate reference tracking because of the wide-range input voltage of the solar panels. The very tight output voltage requirements demand a robust, reliable, and high-efficiency converter. The control of such a converter is very complex and time consuming to design. Two commonly used control modes are current and voltage control. The design and implementation of a voltage controller for DC–DC power converter is simpler but compared to current mode controller, does not do provide for overcurrent protection. A single-ended primary inductance converter (SEPIC) was selected for this research work because of its ability to buck or boost the input voltage coupled with the ability to provide noninverting polarity with respect to the input voltage. Parameter values for the converter studied are used to analyse and design both the voltage and the current mode controllers for the nanosatellite front-end power converter. Output voltage reference tracking with step and ramp changes in the input voltage is evaluated in terms of the time taken to reach steady-state after the induced disturbances and either the overshoot or undershoot of the output voltage reference. The design of analogue pulse width modulation (PWM) study was carried out in order to drive the metal-oxide-semiconductor field-effect transistor (MOSFET) switch. For the two controllers, changes in the reference output voltage in response to load changes are also studied. An examination of the effects of solar radiation on the MOSFET switch was conducted; this switch is the main component of the front-end DC–DC power converter for a nanosatellite. At the more general level the examination also provided information on the response of the semiconductor technology in space application. The overall purpose of studying the MOSFET switch was to investigate the mechanisms that will facilitate its ability of switching ‘on’ and ‘off’ without failure as a result of solar radiation. The effects of solar radiation on MOSFET device in space, has resulted in more malfunctions of these devices in the past five years than over the preceding 40 years.

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Kobayashi, Takuma. "Study on Defects in SiC MOS Structures and Mobility-Limiting Factors of MOSFETs." Kyoto University, 2018. http://hdl.handle.net/2433/232043.

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Aminbeidokhti, Amirhossein. "Measurement and Analysis of Electron Mobility in GaN Power HEMTs." Thesis, Griffith University, 2016. http://hdl.handle.net/10072/368007.

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High-electron-mobility transistor (HEMT) is a promising device for power applications because of their high breakdown voltage, high electron mobility in two-dimensional electron gas (2DEG) area, fast switching capability, high-temperature operating capabilities, compatibility with standard electronic circuits, and low production cost. In contrast to the gate in metal–oxide–semiconductor field-effect transistor (MOSFET), which extends from source to drain, the gate in HEMT splits the device into two main sections: field-effect (section under the gate) and resistive (section outside the gate). Resistances of the 2DEG outside the gate sections are constant and modelled by fixed resistors. However, the 2DEG resistance under the gate section is dependent to the gate voltage, which can be modelled by channel resistance of a field-effect transistor (FET). Since these resistances depend on the mobility of electrons in the 2DEG, it is important to separate the electron mobility in the resistive and field-effect sections. Therefore, existence of the resistive section in the HEMT structure leads to requiring new methods for the HEMT mobility measurement. Also, since there is no model for the HEMT in SPICE, novel models are required for the SPICE simulation of the HEMT. In order to solve these issues:
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
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Makineni, Anil Kumar. "Construction and realisation of measurement system in a radiation field of 10 standard suns." Thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-17209.

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A measurement system is to be presented, which is used to obtain the I-V characteristics of a solar cell and to track its temperature during irra-diation before mounting it into a complete array/module. This project presents both the design and implementation of an Electronic load for testing the solar cell under field conditions of 10000 W/m^2, which is able to provide current versus voltage and power versus voltage charac-teristics of a solar cell using a software based model developed in Lab-VIEW. An efficient water cooling method which includes a heat pipe array system is also suggested. This thesis presents the maximum power tracking of a solar cell and the corresponding voltage and current values. In addition, the design of the clamp system provides an easy means of replacing the solar cell during testing.Keywords: Solar cell, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), I-V characteristics, cooling system, solar cell clamp system, LabVIEW, Graphical User Interface (GUI).

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Raszmann, Emma Barbara. "Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/95938.

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This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed.
Master of Science
According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

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Jouvet, Nicolas. "Intégration hybride de transistors à un électron sur un noeud technologique CMOS." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00863770.

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Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.

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Zhang, Zhikuan. "Source/drain engineering for extremely scaled MOSFETs /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20ZHANG.

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Chen, Xiangdong. "Bandgap engineering in vertical MOSFETs." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3025006.

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Shen, Jian. "Double gate MOSFETs : process variations and design considerations /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20SHEN.

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Tamjidi, Mohammad R. "Characteristics of N-channel accumulation mode thin film polysilicon mosfets. /." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,132.

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Krishnamohan, Tejas. "Physics and technology of high mobility, strained germanium channel, heterostructure MOSFETs." access full-text online access from Digital Dissertation Consortium, 2006. http://libweb.cityu.edu.hk/cgi-bin/er/db/ddcdiss.pl?3219310.

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Lau, Mei Po Mabel. "Characterization of hot-carrier induced degradation via small-signal characteristics in mosfets /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16462.pdf.

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Wu, Wen. "Modeling the extrinsic resistance and capacitance of planar and non-planar MOSFETs /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20WUW.

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Palmer, Martin John. "Investigation of high mobility pseudomorphic SiGe p channels in Si MOSFETS at low and high electric fields." Thesis, University of Warwick, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246761.

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Safarjameh, Kourosh 1961. "Fast-neutron-induced resistivity change in power MOSFETs." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277011.

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Fast neutron irradiation tests were performed to determine the correlation of change of drain-source resistance and neutron fluence for power MOSFETs. The Objectives of the tests were: (1) to detect and measure the degradation of critical MOSFET device parameters as a function of neutron fluence (2) to compare the experimental results and the theoretical model. In general, the drain-source resistance increased from 1 Ohm to 100 Ohm after exposure to fast neutron fluence of 3 x 1014 neut/cm2, and decreased by a factor of five after high temperature annealing.

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Martinez, Marino Juan 1965. "The analysis of current-mirror MOSFETs for use in radiation environments." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276910.

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Experiments were conducted on current-mirror MOSFETs to examine their suitability for use in radiation environments. These devices, which allow low loss load current sensing (defined by a current-ratio n'), are an important element of many power integrated circuits (PICs). Total-dose testing demonstrated that the current ratio was virtually unaffected for many operating conditions. In all cases, changes were largest when sense resistance was largest and minimal when sense voltage was approximately equal to the load source's voltage. In addition, testing verified the feasibility of using sense-cell MOSFETs for applications which require radiation exposure. A constant-current op-amp circuit showed minimal current shifts, using proper circuit design, following total-dose exposure. Dose-rate testing showed the feasibility of using sense voltage to trigger g&d2; protection through drain-source voltage clamping, providing a relatively inexpensive alternative to voltage derating.

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Modzelewski, Kenneth Paul. "DC parameter extraction technique for independent double gate MOSFETs a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=11&did=1759989211&SrchMode=1&sid=1&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1250600320&clientId=28564.

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Shelley, Valerie Anderson 1957. "Validity of the Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276801.

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The Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS is investigated. The effects considered are Drain Induced Barrier Lowering, DIBL, and the maximum electric field, Emax, which influences Drain Induced High Field, DIHF. A scaled short channel design is used as the basis for the investigation. Cases are numerically simulated using the MINIMOS program. DIBL and Emax are calculated using the Jain and Balk model. Model values are compared to numerical simulation values. Results show the model consistently overestimates DIBL. Also, the range for which the model closely estimates Emax is found. Variation in Emax with change of junction depth Xj is investigated. The electric field, Ex, as it varies with depth in the channel is investigated, and compared to the Jain and Balk approximation. The deviations suggest that the model must break down for short channels.

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Diawuo, Kwasi. "Buried channel delta-doped metal-oxide semiconductor field effect transistors (#delta#-doped MOSFETs)." Thesis, University of Newcastle Upon Tyne, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.361543.

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Dinse, Brian P. "Silicon-on-insulator MOSFETS : material, process and device characteristics /." Online version of thesis, 1994. http://hdl.handle.net/1850/12193.

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Huang, Chender 1960. "Characterization of interface trap density in power MOSFETs using noise measurements." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276872.

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Low-frequency noise has been measured on commercial power MOSFETs. These devices, fabricated with the VDMOS structure, exhibit a 1/f type noise spectrum. The interface state density obtained from noise measurements was compared with that obtained from the subthreshold-slope method. Reasonable agreement was found between the two measurements. The radiation effects on the noise power spectral density were also investigated. The results indicated that the noise can be attributed to the generation of interface traps near the Si-SiO₂ interface. The level of interface traps generated by radiation was bias dependent. The positive gate bias gave rise to the largest interface-trap density.

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