Relevant bibliographies by topics / Metal oxide semiconductors, Complementary Design and construction

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Conference papers

Academic literature on the topic 'Metal oxide semiconductors, Complementary Design and construction'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Metal oxide semiconductors, Complementary Design and construction"

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Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.

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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outp
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Breslin, Catherine, and Adrian O'Lenskie. "Neuromorphic hardware databases for exploring structure–function relationships in the brain." Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 356, no. 1412 (August 29, 2001): 1249–58. http://dx.doi.org/10.1098/rstb.2001.0904.

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Neuromorphic hardware is the term used to describe full custom–designed integrated circuits, or silicon ‘chips’, that are the product of neuromorphic engineering—a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure–function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed–signal circuitry—a hybrid of the two. Cu
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Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.

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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS w
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Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (June 17, 2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.

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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with thei
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Kalagadda, B., N. Muthyala, and K. K. Korlapati. "Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques." Journal of Engineering Research [TJER] 14, no. 1 (March 1, 2017): 74. http://dx.doi.org/10.24200/tjer.vol14iss1pp74-84.

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Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The adv
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Wang, Xiaochun, Meicheng Fu, Heng Yang, Jiali Liao, and Xiujian Li. "Temperature and Pulse-Energy Range Suitable for Femtosecond Pulse Transmission in Si Nanowire Waveguide." Applied Sciences 10, no. 23 (November 26, 2020): 8429. http://dx.doi.org/10.3390/app10238429.

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We experimentally measured the femtosecond pulse transmission through a silicon-on-insulator (SOI) nanowire waveguide under different temperatures and input pulse energy with a cross-correlation frequency-resolved optical gating (XFROG) measurement setup. The experimental results demonstrated that the temperature and pulse energy dependence of the Si photonic nanowire waveguide (SPNW) is interesting rather than just monotonous or linear, and that the suitable temperature and pulse-energy range is as suggested in this experiment, which will be valuable for analyzing the practical design of the
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Mizuno, Tomohisa, Naoki Mizoguchi, Kotaro Tanimoto, Tomoaki Yamauchi, Mitsuo Hasegawa, Toshiyuki Sameshima, and Tsutomu Tezuka. "New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices." Japanese Journal of Applied Physics 49, no. 4 (April 20, 2010): 04DC13. http://dx.doi.org/10.1143/jjap.49.04dc13.

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Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was
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Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transist
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Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (June 22, 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.

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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alte
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Dissertations / Theses on the topic "Metal oxide semiconductors, Complementary Design and construction"

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Bond, Steven Winfred. "Through-silicon circuit optical communications links." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15390.

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Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.<br>Parallel optical
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Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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Xiao, Haiqiao. "Design of Radio-Frequency Filters and Oscillators in Deep-Submicron CMOS Technology." PDXScholar, 2008. https://pdxscholar.library.pdx.edu/open_access_etds/5233.

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Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operati
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Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.

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Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/9447.

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Blalock, Benjamin Joseph. "A 1-volt CMOS wide dynamic Range operational amplifier." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15441.

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Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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Dong, Zhiwei. "Low-power, low-distortion constant transconductance Gm-C filters." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/25400.

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Mony, Madeleine. "Reprogrammable optical phase array." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103276.

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The evolving needs of network carriers are changing the design of optical networks. In order to reduce cost, latency, and power consumption, electrical switches are being replaced with optical switching fabrics at the core of the networks. An example of such a network is an Agile All-Photonic Network (AAPN).<br>This thesis presents a novel device that was designed to operate as an optical switch within the context of an AAPN network. The device is a Reprogrammable Optical Phase Array (ROPA), and the design consists of applying multiple electric fields of different magnitudes across an electro-
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Books on the topic "Metal oxide semiconductors, Complementary Design and construction"

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Peluso, Vincenzo. Design of low-voltage low-power CMOS Delta-Sigma A/D converters. Boston: Kluwer Academic Publishers, 1999.

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Hogervorst, Ron. Design of low-voltage, low-power operational amplifier cells. Boston: Kluwer Academic Publishers, 1996.

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Craninckx, J. Wireless CMOS frequency synthesizer design. Boston: Kluwer Academic Publishers, 1998.

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CMOS analog integrated circuits: High speed and power efficient design. Boca Raton: Taylor & Francis, 2011.

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Hermann, Mader, and Friedrich H. Dr -Ing, eds. Technologie hochintegrierter Schaltungen. 2nd ed. Berlin: Springer, 1996.

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Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. New York: IEEE Press, 2005.

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1960-, Li Harry W., and Boyce David E. 1940-, eds. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1997.

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Baker, R. Jacob. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1998.

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Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. Piscataway, NJ: IEEE Press, 2008.

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Josʹe M. de la Rosa. Systematic design of CMOS switched-current bandpass sigma-delta modulators for digital communication chips. Boston: Kluwer Academic, 2002.

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Conference papers on the topic "Metal oxide semiconductors, Complementary Design and construction"

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Gillet, Jean-Numa, Yann Chalopin, and Sebastian Volz. "Atomic-Scale Three-Dimensional Phononic Crystals With a Lower Thermal Conductivity Than the Einstein Limit of Bulk Silicon." In ASME 2008 Heat Transfer Summer Conference collocated with the Fluids Engineering, Energy Sustainability, and 3rd Energy Nanotechnology Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/ht2008-56403.

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Extensive research about superlattices with a very low thermal conductivity was performed to design thermoelectric materials. Indeed, the thermoelectric figure of merit ZT varies with the inverse of the thermal conductivity but is directly proportional to the power factor. Unfortunately, as nanowires, superlattices reduce heat transfer in only one main direction. Moreover, they often show dislocations owing to lattice mismatches. Therefore, fabrication of nanomaterials with a ZT larger than the alloy limit usually fails with the superlattices. Self-assembly is a major epitaxial technology to f
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