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Journal articles on the topic 'Metal oxide semiconductors, Complementary Design and construction'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.

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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outp

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2

Breslin, Catherine, and Adrian O'Lenskie. "Neuromorphic hardware databases for exploring structure–function relationships in the brain." Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 356, no. 1412 (August 29, 2001): 1249–58. http://dx.doi.org/10.1098/rstb.2001.0904.

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Neuromorphic hardware is the term used to describe full custom–designed integrated circuits, or silicon ‘chips’, that are the product of neuromorphic engineering—a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure–function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed–signal circuitry—a hybrid of the two. Cu

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3

Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.

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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS w

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4

Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (June 17, 2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.

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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with thei

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5

Kalagadda, B., N. Muthyala, and K. K. Korlapati. "Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques." Journal of Engineering Research [TJER] 14, no. 1 (March 1, 2017): 74. http://dx.doi.org/10.24200/tjer.vol14iss1pp74-84.

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Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The adv

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6

Wang, Xiaochun, Meicheng Fu, Heng Yang, Jiali Liao, and Xiujian Li. "Temperature and Pulse-Energy Range Suitable for Femtosecond Pulse Transmission in Si Nanowire Waveguide." Applied Sciences 10, no. 23 (November 26, 2020): 8429. http://dx.doi.org/10.3390/app10238429.

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We experimentally measured the femtosecond pulse transmission through a silicon-on-insulator (SOI) nanowire waveguide under different temperatures and input pulse energy with a cross-correlation frequency-resolved optical gating (XFROG) measurement setup. The experimental results demonstrated that the temperature and pulse energy dependence of the Si photonic nanowire waveguide (SPNW) is interesting rather than just monotonous or linear, and that the suitable temperature and pulse-energy range is as suggested in this experiment, which will be valuable for analyzing the practical design of the

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7

Mizuno, Tomohisa, Naoki Mizoguchi, Kotaro Tanimoto, Tomoaki Yamauchi, Mitsuo Hasegawa, Toshiyuki Sameshima, and Tsutomu Tezuka. "New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices." Japanese Journal of Applied Physics 49, no. 4 (April 20, 2010): 04DC13. http://dx.doi.org/10.1143/jjap.49.04dc13.

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8

Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was

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9

Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transist

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10

Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (June 22, 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.

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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alte

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11

Ren, Xiaojiao, Ming Zhang, Nicolas Llaser та Yiqi Zhuang. "On-Chip Measurement of Quality Factor Implemented in 0.35μm CMOS". Journal of Circuits, Systems and Computers 25, № 08 (17 травня 2016): 1650087. http://dx.doi.org/10.1142/s0218126616500870.

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Based on time-domain quality factor (Q-factor) measurement principle, we have proposed an architecture which has the potential to be integrated on-chip. Thanks to the proposed original reconfigurable structure, the main measurement error from the offset of the operational transconductance amplifier (OTA) used can be cancelled automatically during the measurement operation, leading to a high accuracy Q-factor measurement. The digital control circuit plays an important role in the automatic passage between the two configurations designed, i.e., peak detector and comparator. The main advantages o

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12

Kajal and Vijay Kumar Sharma. "An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic." Micro and Nanosystems 13 (January 25, 2021). http://dx.doi.org/10.2174/1876402913666210125144339.

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Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of very large-scale integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in deep s

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13

"The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology." International Journal of Engineering and Advanced Technology 9, no. 1 (October 30, 2019): 43–49. http://dx.doi.org/10.35940/ijeat.a1027.109119.

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Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic

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14

"The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI Designs AT 32NM Technology." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 361–66. http://dx.doi.org/10.35940/ijrte.d6903.118419.

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Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual V

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15

Naz, Syed Farah, Sadat Riyaz, and Vijay Kumar Sharma. "A Review of QCA Nanotechnology as an Alternate to CMOS." Current Nanoscience 17 (March 1, 2021). http://dx.doi.org/10.2174/1573413717666210301111822.

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Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical li

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16

Torres, Florent, Eric Kerhervé, Andreia Cathelin, and Magali De Matos. "A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications." International Journal of Microwave and Wireless Technologies, August 25, 2020, 1–18. http://dx.doi.org/10.1017/s1759078720001087.

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Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm ar

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17

TR, Mrs Lakshmidevi, Mr K. N. Jeevan Reddy, Mr Ashrith Rao, Mr Dhanush Kashyap S, and Ms Chandini K. "Comparison of 4-Bit SAR ADC Using Different Logic Styles in 90nm Technology." International Journal of Advanced Research in Science, Communication and Technology, August 6, 2021, 100–108. http://dx.doi.org/10.48175/ijarsct-1817.

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In recent years, we have come across a growing need for the design of low power, long battery life Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC). ADCs are the major component of all the systems which need to process an analogue signal obtained from measuring real world parameters and hence they need to be efficient enough depending on the application and power constraint of the device. Speed is also an important parameter as it is used in many real time applications. The basic components of the SAR ADC can be implemented using circuits of various logics available f

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18

Chang, Jane P. "Innovative Curriculum on Electronic Materials Processing and Engingeering." MRS Proceedings 684 (2001). http://dx.doi.org/10.1557/proc-684-gg5.2.

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Recognizing that the traditional engineering education training is often inadequate in preparing the students for the challanges presented by this industry's dynamic environment and insufficient to meet the empoyer's criteria in hiring new engineers, a new curriculum on Semiconductor Manufacturing is instituted in the Chemical Engineering Department at UCLA to train the students in various scientific and technologica areas that are pertinenet to the microelectronics industries. This paper describes this new mutidisciplinary curriculum that provides knowledge and skills in semiconductor manufac

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19

Li, Kai, Chao Teng, Shuang Wang, and Qianhao Min. "Recent Advances in TiO2-Based Heterojunctions for Photocatalytic CO2 Reduction With Water Oxidation: A Review." Frontiers in Chemistry 9 (April 15, 2021). http://dx.doi.org/10.3389/fchem.2021.637501.

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Photocatalytic conversion of CO2 into solar fuels has gained increasing attention due to its great potential for alleviating the energy and environmental crisis at the same time. The low-cost TiO2 with suitable band structure and high resistibility to light corrosion has proven to be very promising for photoreduction of CO2 using water as the source of electrons and protons. However, the narrow spectral response range (ultraviolet region only) as well as the rapid recombination of photo-induced electron-hole pairs within pristine TiO2 results in the low utilization of solar energy and limited

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20

Rahimi, Ronak, and D. Korakakis. "Charge transport in ambipolar pentacene thin film transistors." MRS Proceedings 1286 (2011). http://dx.doi.org/10.1557/opl.2011.239.

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ABSTRACTAmbipolar organic transistors are technologically interesting because of their potential applications in light-emitting field-effect transistors [1] and complementary-metal-oxide-semiconductor (CMOS) devices by providing ease of design, low cost of fabrication, and flexibility [2]. Although common organic semiconductors show either n- or p-type charge transport characteristic, organic transistors with ambipolar characteristics have been reported recently. In this work, we show that ambipolar transport can be achieved within a single transistor channel using LiF gate dielectric in the t

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