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Dissertations / Theses on the topic 'Metal semiconductor field-effect transistors'

Author: Grafiati

Published: 4 June 2021

Last updated: 31 July 2024

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1

Frenzel, Heiko. "ZnO-based metal-semiconductor field-effect transistors." Doctoral thesis, Universitätsbibliothek Leipzig, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:15-qucosa-61957.

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Die vorliegende Arbeit befasst sich mit der Entwicklung, Herstellung und Untersuchung von ZnO-basierten Feldeffekttransistoren (FET). Dabei werden im ersten Teil Eigenschaften von ein- und mehrschichtigen Isolatoren mit hohen Dielektrizitätskonstanten betrachtet, die mittels gepulster Laserabscheidung (PLD) dargestellt wurden. Die elektrischen und kapazitiven Eigenschaften dieser Isolatoren innerhalb von Metall-Isolator-Metall (MIM) bzw. Metall-Isolator-Halbleiter (MIS) Übergängen wurden untersucht. Letzterer wurde schließlich als Gate-Struktur in Metall-Isolator-Halbleiter-FET (MISFET) mit unten (backgate) bzw. oben liegendem Gate (topgate) genutzt. Der zweite Teil konzentriert sich auf Metal-Halbleiter-FET (MESFET), die einen Schottky-Kontakt alsGate nutzen. Dieser wurde mittels reaktiver Kathodenzerstäubung (Sputtern) von Ag, Pt, Pd oder Au unter Einflußvon Sauerstoff hergestellt. ZnO-MESFET stellen eine vielversprechende Alternative zu den bisher in der Oxid-basierten Elektronik verwendeten MISFET dar. Durch die Variation des verwendeten Gate-Metalls, Dotierung, Dicke und Struktur des Kanals und Kontakstruktur, wurde ein Herstellungsstandard gefunden, der zu weiteren Untersuchungen herangezogen wurde. So wurde die Degradation der MESFET unter Belastung durch dauerhaft angelegte Spannung, Einfluss von Licht und erhöhten Temperaturen sowie lange Lagerung getestet. Weiterhin wurden ZnO-MESFET auf industriell genutztem Glasssubstrat hergestellt und untersucht, um die Möglichkeit einer großflächigen Anwendung in Anzeigeelementen aufzuzeigen. Einfache integrierte Schaltungen, wie Inverter und ein NOR-Gatter, wurden realisiert. Dazu wurden Inverter mit sogenannten Pegelschiebern verwendet, welche die Ausgangsspannung des Inverters so verschieben, dass eine logische Aneinanderreihungvon Invertern möglich wird. Schließlich wurden volltransparente MESFET und Inverter, basierend auf neuartigen transparenten gleichrichtenden Kontakten demonstriert.

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2

Vega, Reinaldo A. "Schottky field effect transistors and Schottky CMOS circuitry /." Online version of thesis, 2006. http://hdl.handle.net/1850/5179.

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3

Shi, Xuejie. "Compact modeling of double-gate metal-oxide-semiconductor field-effect transistor /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202006%20SHI.

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4

Todescato, Francesco. "Functional dielectric/semiconductor and metal/semiconductor interfaces in organic field-effect transistors." Doctoral thesis, Università degli studi di Padova, 2007. http://hdl.handle.net/11577/3425125.

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The work presented in this thesis focuses on the investigation of two interfaces which play a crucial role in the physics of organic electronic devices: the dielectric/organic semiconductor and the organic semiconductor/metal ones. Regarding the dielectric/OS interface, we have deeply investigated the relationship between the SiO2 cleaning protocol or treatment and the electrical response of OFETs based on two PPV semiconducting polymers (MEH-PPV and OC1C10-PPV) and on a quarterthiopene derivative small molecule (DHCO-4T). Regarding the OS/metal interface, we investigated the electrical performances of PPV and DHCO-4T based OFETs with different metal contacts.

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5

Zhang, Zhikuan. "Source/drain engineering for extremely scaled MOSFETs /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20ZHANG.

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6

Lord, Joseph Louis Martin. "FET upconverter design using load dependent mixing transconductance." Thesis, University of British Columbia, 1988. http://hdl.handle.net/2429/28499.

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The conversion gain of GaAs MESFET mixers is known to be dependent on the impedances seen by the applied signals and the resulting mixing products at all ports of the device. For an accurate representation, all these loading conditions should be considered; however, the design of gate and drain networks then becomes rather difficult. As a result, no sufficiently accurate and yet usable design procedures exist for MESFET mixers; instead, a few simple rules involving short- and open-circuit terminations have been given by various authors. Unfortunately, these rules are often inappropriate, particularly in upconverter applications. In this thesis, the conversion efficiency dependence on the drain loading at the local oscillator frequency has been studied for a gate upconverter; the local oscillator signal is by far the most dominant in terms of its influence on mixer performance. It has been found that the conversion gain can significantly deteriorate for a narrow range of load values. In addition, the local oscillator drain termination resulting in highest gain has been found to be generally different from the short-circuit recommended in the literature. Based on these findings, a novel FET upconverter design procedure has been developed that incorporates the local oscillator loading phenomenon in the FET equivalent circuit by means of a load dependent mixing transconductance. It allows the optimization of the drain network for an acceptable match at the selected sideband and desired local oscillator rejection while avoiding impedance values in the local oscillator frequency range which would otherwise cause severe degradation in conversion gain.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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7

Randell, Heather Eve. "Applications of stress from boron doping and other challenges in silicon technology." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0010292.

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8

Klüpfel, Fabian J., Wenckstern Holger von, and Marius Grundmann. "Low frequency noise of ZnO based metal-semiconductor field-effect transistors." American Institute of Physics, 2015. https://ul.qucosa.de/id/qucosa%3A31224.

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The low frequency noise of metal-semiconductor field-effect transistors (MESFETs) based on ZnO:Mg thin films grown by pulsed laser deposition on a-plane sapphire was investigated. In order to distinguish between noise generation in the bulk channel material, at the semiconductor surface, and at the gate/channel interface, ohmic ZnO channels without gate were investigated in detail, especially concerning the dependency of the noise on geometrical variations. The experiments suggest that the dominating 1/f noise in the frequency range below 1 kHz is generated within the bulk channel material, both for bare ZnO channels and MESFETs.

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9

Fleischer, Stephen. "A study of gate-oxide leakage in MOS devices." Thesis, [Hong Kong : University of Hong Kong], 1993. http://sunzi.lib.hku.hk/hkuto/record.jsp?B1364600X.

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10

Takshi, Arash. "Organic metal-semiconductor field-effect transistor (OMESFET)." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31531.

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Organic electronics offers the possibility of producing ultra-low-cost and large-area electronics using printing methods. Two challenges limiting the utility of printed electronic circuits are the high operating voltage and the relatively poor performance of printed transistors. It is shown that voltages can be reduced by replacing the capacitive gate used in Organic Field-Effect Transistors (OFETs) with a Schottky contact, creating a thin-film Organic Metal-Semiconductor Field-Effect Transistor (OMESFET). This geometry solves the voltage issue, and promises to be useful in situations where low voltage operation is important, but good performance is not essential. In cases where high voltage is acceptable or required, it is shown that OFET performance can be greatly improved by employing a Schottky contact as a second gate. The relatively thick insulating layer between the gate and the semiconductor in OFETs makes it necessary to employ a large change of gate voltage (~40 V) to control the drain current. In order to reduce the voltage to less than 5 V a very thin (<10 nm) insulating layer and/or high-k dielectric materials can be used, but these solutions are not compatible with current printing technology. Simulations and implementations of OMESFET devices demonstrate low voltage operation (<5 V) and improved sub-threshold swing compared to the OFET. However, these benefits are achieved at the expense of mobility. In order to achieve good performance in an OFET, including threshold voltage, current ratio and output resistance, the semiconductor thickness has to be less than 50 nm, whereas the thickness of a printed semiconductor is typically larger than 200 nm. The addition of a top Schottky contact on the OFET creates a depletion region thereby reducing the effective thickness of the semiconductor, and resulting in enhanced transistor performance. Simulations and experimental results show improvements in the threshold voltage, the current ratio, and the output resistance of a dual gate transistor, when compared to those in an OFET of the same thickness. The transistors introduced in this work demonstrate means of improving the performance of thick-film OFETs and of achieving substantially lower operation voltage in organic transistors.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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11

Höhr, Timm. "Quantum-mechanical modeling of transport parameters for MOS devices /." Konstanz : Hartnung-Gorre, 2006. http://www.loc.gov/catdir/toc/fy0707/2007358987.html.

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Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16228.
Summary in German and English, text in English. Includes bibliographical references (p. 123-132).

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12

Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.

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13

Rutherford, William C. "Gallium arsenide integrated circuit modeling, layout and fabrication." Thesis, University of British Columbia, 1987. http://hdl.handle.net/2429/26733.

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The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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14

Peng, Harry W. "The effects of stress on gallium arsenide device characteristics." Thesis, University of British Columbia, 1988. http://hdl.handle.net/2429/28584.

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For VLSI applications, it is essential to have consistent device characteristics for devices fabricated on different fabrication runs, on different wafers, and especially across a single wafer. MESFETs fabricated on GaAs have been found to have an orientation dependence in their threshold voltage and other characteristics. For MESFETs with gate length less than 2 μm, changing the device orientation can so significantly alter the device characteristics that it must be considered during the transistor design stage. The causes for the orientation dependence in the device characteristics have been suggested to be the piezoelectric property of GaAs and stress in the substrate. Stress produced by the encapsulating dielectric film generates a polarization charge density in the substrate. If the magnitude of the polarization charge density is large enough to alter the channel doping profile, then the device characteristics are changed. In this thesis, the effects of stress on GaAs MESFET device characteristics were studied by modelling and experimental works. In the modelling part, polarization charge densities under the gate of an encapsulated MESFET were calculated by using the so called distributed force model and the edge concentrated model. The distributed force model is a much better model because it describes more realistically the stress distribution in the film and in the substrate. It should provide a much more accurate calculation of the induced polarization charge density. The results show that the polarizarition charge densities calculated by the two models have similar distribution pattern, but the magnitudes are very different. With an identical set of conditions, a much larger polarization charge density is predicted by the edge concentrated model. In addition, the distributed force model distinguishes different films by a "hardness" value, based on their elastic property, whereas the edge concentrated model does not. A film with a larger "hardness" value is predicted to generate a larger polarization charge density. Two types of film were considered, SiO₂ and Si₃N₄. Using bulk film characteristics, the calculations showed that Si0₂ film is "harder" than Si₃N₄ film. If an equal built-in stress value is assumed, then a larger polarization charge density is predicted for Si0₂ than for Si₃N₄ encapsulated substrates. In the experimental part, stress was applied to test devices by bending strips of GaAs wafers in a cantilever configuration. MESFETs tested were oriented in the [011] or the [011̅] direction. Both static stress and time-varying stress were applied. In the statics stress experiment, the changes in the barrier height and the C-V profile were measured. It was found that, with equal stress applied, Schottky barriers with a larger ideality factor showed a larger change in the barrier height. In the time-varying stress experiment, attempts were made to measure the effect of the polarization charge density on device characteristics by measuring changes in the drain-source current.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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15

Wu, Kehuey. "Strain effects on the valence band of silicon piezoresistance in p-type silicon and mobility enhancement in strained silicon pMOSFET /." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0008390.

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16

Wu, Xu Sheng. "Three dimensional multi-gates devices and circuits fabrication, characterization, and modeling /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20WUX.

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17

Modzelewski, Kenneth Paul. "DC parameter extraction technique for independent double gate MOSFETs a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=11&did=1759989211&SrchMode=1&sid=1&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1250600320&clientId=28564.

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18

Trivedi, Vishal P. "Physics and design of nonclassical nanoscale CMOS devices with ultra-thin bodies." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0009860.

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19

Shen, Jian. "Double gate MOSFETs : process variations and design considerations /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20SHEN.

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20

Krishnamohan, Tejas. "Physics and technology of high mobility, strained germanium channel, heterostructure MOSFETs." access full-text online access from Digital Dissertation Consortium, 2006. http://libweb.cityu.edu.hk/cgi-bin/er/db/ddcdiss.pl?3219310.

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21

Tamjidi, Mohammad R. "Characteristics of N-channel accumulation mode thin film polysilicon mosfets. /." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,132.

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22

Lin, Xinnan. "Double gate MOSFET technology and applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.

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23

Ahmed, Muhammad Mansoor. "Optimisation of submicron low-noise GaAs MESFETs." Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242966.

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24

Chen, Xiangdong. "Bandgap engineering in vertical MOSFETs." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3025006.

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25

Jeedigunta, Manjeera. "Analytical and compact modeling of highly asymmetrical independent double-gated transistors a dissertation presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=1908035741&SrchMode=1&sid=2&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1265058157&clientId=28564.

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26

Lau, Mei Po Mabel. "Characterization of hot-carrier induced degradation via small-signal characteristics in mosfets /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16462.pdf.

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27

Ng, Chun Wai. "On the inversion and accumulation layer mobilities in N-channel trench DMOSFETS /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20NG.

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28

Wu, Wen. "Modeling the extrinsic resistance and capacitance of planar and non-planar MOSFETs /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20WUW.

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29

Ouyang, Qiqing Christine. "Physical model enhancement and exploration of bandgap engineering in novel sub-100nm pMOSFETs /." Digital version:, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p9992880.

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30

Haasmann, Daniel Erwin. "Active Defects in 4H–SiC MOS Devices." Thesis, Griffith University, 2015. http://hdl.handle.net/10072/367037.

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The research findings presented in this thesis have provided several key contributions towards a better understanding of the SiC–SiO2 interface in SiC MOS structures. The electrically active defects directly responsible for degrading the channel-carrier mobility in 4H–SiC MOSFETs have been identified and a novel technique to detect these defects in 4H–SiC MOS capacitors has been proposed and experimentally demonstrated. With a better understanding of defects at the SiC–SiO2 interface two alternative gate oxide growth processes have been proposed to overcome the practical limitations associated with current NO-nitridation techniques in high-volume, production based oxidation furnaces. This work therefore contributes to the wider research effort towards improving the performance of SiC MOSFETs in several ways. The following paragraphs summarise the key conclusions that have been obtained as a result of this study. Electrically Active Defects and the Channel-Carrier Mobility (Chapter 3) A critical review of defects at the SiC–SiO2 interface exposed a few key discrepancies in both the current understanding of the dominant defects responsible for channel-carrier mobility degradation in 4H–SiC MOSFETs and in the current approach to characterise and evaluate the SiC–SiO2 interface. Firstly, it was recognised that the Shockley-Read-Hall statistical model, based on thermally activated transport for traps spatially located at the semiconductor-oxide interface, cannot be directly applied to describe the transfer mechanism between free conduction band electrons and the shallow NITs near EC. This implication tends to suggest that the NITs near EC in SiC MOS structures cannot be accurately examined using traditional MOS characterisation techniques that are based on this statistical model. Secondly, in accordance with the studies conducted by Saks et. al. [1-3], it was realized that channel-carrier mobility degradation in 4H–SiC MOSFETs is primarily due to the significantly reduced free electron density in the inversion channel. In light of this understanding, the interfacial defects that actively trap channel electrons under strong inversion conditions were considered to be dominant in these devices as opposed to the NITs near EC that are typically examined using conventional MOS characterisation techniques on N-type MOS capacitors in depletion. To further support this hypothesis, a theoretical analysis of the inversion carrier concentration using the charge sheet model was conducted to demonstrate that the NITs with energy levels corresponding to strong inversion are of key importance to the channel-carrier mobility.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
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31

Olsen, Sarah H. "Strained silicon/silicon germanium heterojunction n-chanel metal oxide semiconductor field effect transistors." Thesis, University of Newcastle Upon Tyne, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246619.

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32

Diawuo, Kwasi. "Buried channel delta-doped metal-oxide semiconductor field effect transistors (#delta#-doped MOSFETs)." Thesis, University of Newcastle Upon Tyne, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.361543.

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33

Turner, Gary Chandler. "Zinc Oxide MESFET Transistors." Thesis, University of Canterbury. Electrical and Computer Engineering, 2009. http://hdl.handle.net/10092/3439.

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Zinc oxide is a familiar ingredient in common household items including sunscreen and medicines. It is, however, also a semiconductor material. As such, it is possible to use zinc oxide (ZnO) to make semiconductor devices such as diodes and transistors. Being transparent to visible light in its crystalline form means that it has the potential to be the starting material for so-called 'transparent electronics', where the entire device is transparent. Transparent transistors have the potential to improve the performance of the electronics currently used in LCD display screens. Most common semiconductor devices require the material to be selectively doped with specific impurities that can make the material into one of two electronically distinct types – p- or n-type. Unfortunately, making reliable p-type ZnO has been elusive to date, despite considerable efforts worldwide. This lack of p-type material has hindered development of transistors based on this material. One alternative is a Schottky junction, which can be used as the active element in a type of transistor known as a metal-semiconductor field effect transistor, MESFET. Schottky junctions are traditionally made from noble metal layers deposited onto semiconductors. Recent work at the Canterbury University has shown that partially oxidised metals may in fact be a better choice, at least to zinc oxide. This thesis describes the development of a fabrication process for metal-semiconductor field effect transistors using a silver oxide gate on epitaxially grown zinc oxide single crystals. Devices were successfully produced and electrically characterised. The measurements show that the technology has significant potential.

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34

Pratapgarhwala, Mustansir M. "Characterization of Transistor Matching in Silicon-Germanium Heterojunction Bipolar Transistors." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7536.

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Transistor mismatch is a crucial design issue in high precision analog circuits, and is investigated here for the first time in SiGe HBTs. The goal of this work is to study the effects of mismatch under extreme conditions including radiation, high temperature, and low temperature. One portion of this work reports collector current mismatch data as a function of emitter geometry both before and after 63 MeV proton exposure for first-generation SiGe HBTs with a peak cut-off frequency of 60 GHz. However, minimal changes in device-to-device mismatch after radiation exposure were experienced. Another part of the study involved measuring similar devices at different temperatures ranging from 298K to 377K. As a general trend, it was observed that device-to-device mismatch improved with increasing temperature.

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35

Smith, Casey Eben Reidy Richard F. "Advanced technology for source drain resistance reduction in nanoscale FinFETs." [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-6052.

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Yoon, Kwang Sub. "A precision analog small-signal model for submicron MOSFET devices." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14935.

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37

Shelley, Valerie Anderson 1957. "Validity of the Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276801.

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The Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS is investigated. The effects considered are Drain Induced Barrier Lowering, DIBL, and the maximum electric field, Emax, which influences Drain Induced High Field, DIHF. A scaled short channel design is used as the basis for the investigation. Cases are numerically simulated using the MINIMOS program. DIBL and Emax are calculated using the Jain and Balk model. Model values are compared to numerical simulation values. Results show the model consistently overestimates DIBL. Also, the range for which the model closely estimates Emax is found. Variation in Emax with change of junction depth Xj is investigated. The electric field, Ex, as it varies with depth in the channel is investigated, and compared to the Jain and Balk approximation. The deviations suggest that the model must break down for short channels.

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38

Palmer, Martin John. "Investigation of high mobility pseudomorphic SiGe p channels in Si MOSFETS at low and high electric fields." Thesis, University of Warwick, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246761.

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39

Baird, John Malcolm Edward. "A micro processor based A.C. drive with a Mosfet inverter." Thesis, Cape Technikon, 1991. http://hdl.handle.net/20.500.11838/1119.

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Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1991
A detailed study into the development of a three phase motor drive, inverter and microprocessor controller using a scalar control method. No mathematical modelling of the system was done as the drive was built around available technology. The inverter circuit is of a Vo~tage source inverter configuration whicp uses MOSFETs switching at a base frequency of between 1.2 KHz and 2 KHz. Provision has been made for speed control and dynamic braking for special applications, since the drive is not going to be put into a specific application as yet, it was felt that only a basic control should be implemented and space should be left for special requests from prospective customers. The pulses for the inverter are generated from the HEF 4752 I.e. under the control of the micro processor thus giving the processor full control over the inverter and allowing it to change almost any parameter at any time. Although the report might seem to cover a lot of unimportant ground it is imperative that the reader is supplied with the back-ground information in order to understand where A.e. drives failed in the past and where A.e. drives are heading in the future. As well as where this drive seeks to use available technology to the best advantage.

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40

Singh, Jagar. "Technology, characteristics, and modeling of large-grain polysilicon MOSFET /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20SINGH.

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41

李華剛 and Eddie Herbert Li. "Narrow-channel effect in MOSFET." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.

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42

Huang, Chender 1960. "Characterization of interface trap density in power MOSFETs using noise measurements." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276872.

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Low-frequency noise has been measured on commercial power MOSFETs. These devices, fabricated with the VDMOS structure, exhibit a 1/f type noise spectrum. The interface state density obtained from noise measurements was compared with that obtained from the subthreshold-slope method. Reasonable agreement was found between the two measurements. The radiation effects on the noise power spectral density were also investigated. The results indicated that the noise can be attributed to the generation of interface traps near the Si-SiO₂ interface. The level of interface traps generated by radiation was bias dependent. The positive gate bias gave rise to the largest interface-trap density.

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43

Kulkarni, Anish S. "Study of Tunable Analog Circuits Using Double Gate Metal Oxide Semiconductor Field Effect Transistors." Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1234552603.

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44

Tse, Koon-Yiu. "High-K gate oxides and metal gate materials for future complementary metal-oxide-semiconductor field-effect transistors." Thesis, University of Cambridge, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611979.

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45

Duffy, Christopher James. "Modeling hot-electron injection and impact ionization in pFET's." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14796.

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46

Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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47

Waseem, Akbar. "Effect of gate length in enhancing current in a silicon nanowire wrap around gate MOSFET." Diss., Columbia, Mo. : University of Missouri-Columbia, 2006. http://hdl.handle.net/10355/5878.

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Abstract:

Thesis (M.S.)--University of Missouri-Columbia, 2006.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 14, 2007) Vita. Includes bibliographical references.

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Kottantharayil, Anil. "Low voltage hot carrier issues in deep sub-micron metal oxide semiconductor field effect transistors." [S.l. : s.n.], 2002. http://deposit.ddb.de/cgi-bin/dokserv?idn=963719645.

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Liu, Hsi-Wen, and 劉錫紋. "Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/r9ts9h.

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博士
國立中山大學
物理學系研究所
107
Metal-oxide-semiconductor-field-effect transistors (MOSFETs) have the advantages of low manufacturing cost, low power consumption and easy scaling down. They are widely used in the IC industry, and the MOSFETs continue to shrink with the Moore''s Law. When the gate oxide layer is shrunk to a thickness of only 1 nm, the quantum tunneling effect becomes very serious at this scale, resulting in extremely large gate leakage and reliability problems. To continue the scaling down, gate leakage current is the primary problem that must be solved. Therefore, high dielectric constant oxides have been introduced as a solution. The high dielectric constant oxide is grown on the top of SiO2, which allows the gate oxide layer to have a thicker physical thickness and better transistor characteristics. Among many high dielectric constant materials, hafnium-based oxide is the most suitable material for high dielectric gate oxide due to its comprehensive properties. However, pure HfO2 has a low crystallization temperature. It is easy to crystallize after high temperature treatment, causing an increase in gate leakage current. Therefore, additional elements such as N, Si, Al, Ti, Ta and La have been doped into the high-k gate dielectrics to increase crystallization temperature. In addition, dipole can be formed in the oxide layer due to the difference in oxygen density. The dipole can be used to modulate the threshold voltage. The first part of this dissertation uses metal-oxide-semiconductor capacitance (MOSCAP) to investigate the doping dipole in HfO2 effect the electrical characteristic and reliability. We found that the capacitance of gate oxide is increased and gate leakage is decreased in dipole doped sample, but in positive bias temperature instability (PBTI) test is deteriorates severely in dipole doped sample. We consider the explanation is energy band bending due to dipole which causing the electrons has more kinetic energy after tunneling from Si to HfO2, so it is easier to trap and generate defects. In addition, time dependent dielectric breakdown (TDDB) reliability statistics shows the dielectric breakdown correspond to the Weibull distribution, and the dipole doped sample has a shorter lifetime under the same gate voltage. In the second part, we use our laboratory''s low temperature supercritical fluid processing technology to perform supercritical hydridation, fluoridation, and nitridation on MOSCAPs. In the supercritical hydridation and fluoridation treatment, There is no obvious change in the electrical characteristics for control sample and dipole sample., but in the reliability test of TDDB, the lifetime of both devices becomes longer. We think this is because supercritical hydridation and fluoridation can repair dangling bond at HfO2/SiO2 interface. In the third part, we used MOSFET to compare the effects of hot carrier degradation (HCD) of zirconium doped into HfO2. Previous n-MOSFET studies have shown that zirconium-doped hafnium oxide reduces charge trapping and improves PBTI. In this study, a significant reduction in HCD was observed with zirconium-doped HfO2 because channel hot electrons (CHE) trapping in pre-existed defects in HfO2 are the main degradation mechanisms. However, this reduced HCD becomes ineffective at ultra-low temperatures because CHE captured in deep defects at ultra-low temperatures, while zirconium doping only passes defects with shallower energy depths. Finally, p-type FinFETs were used and found an abnormal gate induced gate leakage (GIDL) occurred in the linear operation region after the 120-degree negative bias temperature instability (NBTI). The GIDL diminished when returning to room temperature. As a result, we believe that the linear region GIDL is mainly caused by (1. thermal emission and (2. interface defects at gate to drain overlap regions assisted tunneling. we used the 30-degree hot carrier degradation as a verification. There shows no GIDL in linear region after the 30-degree HCD, however, when the temperature was raised to 120 degrees, the linear region GIDL was measured.

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HUANG, ZHONG-LIN, and 黃仲麟. "A study of metal-insulator-semiconductor field effect transistors." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/75855493686570448599.

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