Relevant bibliographies by topics / Micro-Architecture CPU en pipeline

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers
  5. Reports

Academic literature on the topic 'Micro-Architecture CPU en pipeline'

Author: Grafiati
Published: 7 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "Micro-Architecture CPU en pipeline"

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Chen, Lin, Xiao Ma, and Xiang Ji. "FPGA-based LoongArch Five-stage Pipeline CPU." Journal of Physics: Conference Series 2450, no. 1 (2023): 012058. http://dx.doi.org/10.1088/1742-6596/2450/1/012058.

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Abstract We designed and implemented a five-stage pipeline CPU based on the FPGA platform, programmed in Verilog hardware description language to implement LoongArch architecture. The design and implementation of the Instruction Fetch (IF) stage, Instruction Decode (ID) stage, Instruction Execute (EX) stage, Memory Access (MEM) stage, and Write Back (WB) stage. The design and implementation of the important modules in the pipeline are given. The use of the Bubble method and Bypass technique solves most of the parameter passing problems and branch judgment problems in the pipeline. The access m
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McClain, Bryan, Jinyu Fang, Prathamesh Kale, and John J. Lee. "Simulation of Pipelined MIPS Floating-Point Units using Node-RED." International Journal on Computational Science & Applications 12, no. 5 (2022): 1–12. http://dx.doi.org/10.5121/ijcsa.2022.12501.

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The pipelined processor architecture is the best way to increase instruction-level parallelism, and thus, understanding its operation is one of the keys in computer architecture learning. To help with the leaning process, we have devised a series of pipeline simulation methodologies. This article presents one of them – a simulation methodology of hazard detection and forwarding in MIPS32 pipelined floating-point units. Our implementation approach is using the Node-RED programming environment, an event-driven dragand-drop system for designing data flows with business logic. In addition, to impl
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Qin, Zhongyang. "Design and hazard solving of five-stage pipeline RISC-V processor structure." Applied and Computational Engineering 36, no. 1 (2024): 198–203. http://dx.doi.org/10.54254/2755-2721/36/20230446.

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Benefiting from its late arrival, the RISC-V architecture capitalizes on the maturity of computer architecture technology achieved through years of development. This allows the RISC-V design to sidestep issues that have been exhaustively examined during the evolution of computer architecture over time. Adhering to a specific sequence for executing instructions with a CPU results in extended processing durations. However, in a pipelined architecture, the execution of one instruction doesn't disrupt the synchronized progression of other instructions. The introduction of a pipeline structure can
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Deng, Lifu. "Design a 5-stage pipeline RISC-V CPU and optimise its ALU." Applied and Computational Engineering 34, no. 1 (2024): 237–44. http://dx.doi.org/10.54254/2755-2721/34/20230334.

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The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structur
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Gaitan, Vasile Gheorghita, Nicoleta Cristina Gaitan, and Ioan Ungurean. "CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 9 (2015): 1661–74. http://dx.doi.org/10.1109/tvlsi.2014.2346542.

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Apoorva, Reddy Proddutoori. "Latency Throughput Linear Analysis for GPU Architecture Pipeline." European Journal of Advances in Engineering and Technology 8, no. 11 (2021): 95–98. https://doi.org/10.5281/zenodo.12771283.

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Recent focus has been on eliminating redundant network worload through content-based cracking and utilizing low latency components, using a computationally heavy algorithm. A GPU-based implementation of this algorithm is proposed in this paper, with optimization strategies to enhance performance and throughput of the pipeline architecture. Despite ongoing research on GPU-to-GPU communication, achieving performance on multi-GPU systems remains a challenge due to data workload transfer latency and memory access or allocation issues. Additionally, GPU parallel computation with memory allocation o
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Abramov, E. M. "IMPLEMENTATION OF THE BRANCH PREDICTION SCHEMES FOR THE MICROPROCESSOR OF RISC-V ARCHITECTURE." Issues of radio electronics, no. 8 (August 20, 2018): 49–55. http://dx.doi.org/10.21778/2218-5453-2018-8-49-55.

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One of the limiting factors for increasing the performance of CPU computation pipeline is the pipelining of control transfer instructions. This article provides a review of the problems of raising the instruction pipeline efficiency while executing the branch instructions, by the example of microarchitecture with the implementation of open RISC-V ISA. It gives a description of the various methods of resolving the control hazards. Implementations of the various static and dynamic branch prediction methods, as well as the scheme of calculating a jump address, has been provided. For the dynamic s
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Geetha, Dr K. S., Deepika M, Mrudhul M J, and S. Vedram. "Localization of a Robot on FPGA with 5-Stage Pipeline RISC-V CPU." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 03 (2025): 1–9. https://doi.org/10.55041/ijsrem42440.

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Custom silicon offers an untapped opportunity for addressing complex challenges in robotics by providing optimized performance and energy efficiency. RISC-V—a novel, open- source Instruction Set Architecture (ISA)—has been gaining rapid traction due to its flexibility and customizability. In this work, we explore the capabilities of RISC-V in the robotics do- main by implementing a complete localization and motion control solution on an FPGA. Leveraging the reconfigurability of FPGAs alongside the extensibility of a custom five-stage pipelined RISC- V processor, our approach demonstrates signi
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Zagan, Ionel, and Vasile Gheorghita Gaitan. "Improving the Performance of CPU Architectures by Reducing the Operating System Overhead (Extended Version)." Electrical, Control and Communication Engineering 10, no. 1 (2016): 13–22. http://dx.doi.org/10.1515/ecce-2016-0002.

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Abstract The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The major problems for real-time operating systems are determined by an excessive jitter, introduced mainly through task switching. This can alter deadline requirements, and, consequently, the predictability of hard real-time tasks. New requirements also arise for a real-time operating system used in mixed-criticality systems, when the executions of hard real-time applications require timing predictability. The present
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Abdellah, Marwan, Ayman Eldeib, and Amr Sharawi. "High Performance GPU-Based Fourier Volume Rendering." International Journal of Biomedical Imaging 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/590727.

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Fourier volume rendering (FVR) is a significant visualization technique that has been used widely in digital radiography. As a result of itsO(N2log⁡N)time complexity, it provides a faster alternative to spatial domain volume rendering algorithms that areO(N3)computationally complex. Relying on theFourier projection-slice theorem, this technique operates on the spectral representation of a 3D volume instead of processing its spatial representation to generate attenuation-only projections that look likeX-ray radiographs. Due to the rapid evolution of its underlying architecture, the graphics pro
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Dissertations / Theses on the topic "Micro-Architecture CPU en pipeline"

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Hoseininasab, Sara sadat. "Using HLS to raise the design abstraction level for faster exploration of different CPU Micro-architectures." Electronic Thesis or Diss., Université de Rennes (2023-....), 2025. http://www.theses.fr/2025URENS004.

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La conception de circuits complexes, tels que les processeurs, nécessite un prototypage itératif afin d’explorer diverses caractéristiques micro architecturales et d’obtenir des performances optimales. Ce processus repose usuellement sur l’utilisation des langages de description matérielle comme Verilog qui nécessitent beaucoup de travail et sont sujets aux erreurs. Modifier un design impose souvent une réécriture significative du code HDL, rendant la conception itérative et l’exploration de l’espace de conception fastidieuses et inefficaces, en particulier avec l’augmentation de la complexité
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Endo, Fernando Akira. "Génération dynamique de code pour l'optimisation énergétique." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAM044/document.

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Dans les systèmes informatiques, la consommation énergétique est devenue le facteur le plus limitant de la croissance de performance observée pendant les décennies précédentes. Conséquemment, les paradigmes d'architectures d'ordinateur et de développement logiciel doivent changer si nous voulons éviter une stagnation de la performance durant les décennies à venir.Dans ce nouveau scénario, des nouveaux designs architecturaux et micro-architecturaux peuvent offrir des possibilités d'améliorer l'efficacité énergétique des ordinateurs, grâce à la spécialisation matérielle, comme par exemple les co
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Yan, Jar-shin, and 嚴嘉鑫. "Optimizing Performance of Dynamic Delayed Micro-pipeline Architecture in Digital Signal Processing." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/93348833768953934762.

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碩士<br>元智大學<br>資訊工程研究所<br>88<br>The hardware architecture is an important technology of the digital signal processing, (as VLIW, pipeline, parellel …etc.) Those technologys improve digital signal processor’s performance greatly. Generally, DSP implementation technology often using the synchronous architecture, but synchronous architecture always brought some issues, like clock skew, drive of fan out, power consumption…and so on. Now we provide a different method to avoids these issue, this method not only avoids synchronous architecture’s issues but also improves the performane of di
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Book chapters on the topic "Micro-Architecture CPU en pipeline"

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Acosta Eric, Liu Alan, Sieck Jennifer, Muniz Gilbert, Bowyer Mark, and Armonda Rocco. "A Multi-core CPU Pipeline Architecture for Virtual Environments." In Studies in Health Technology and Informatics. IOS Press, 2009. https://doi.org/10.3233/978-1-58603-964-6-10.

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Physically-based virtual environments (VEs) provide realistic interactions and behaviors for computer-based medical simulations. Limited CPU resources have traditionally forced VEs to be simplified for real-time performance. Multi-core processors greatly increase the computational capacity of computers and are quickly becoming standard. However, developing non-application specific methods to fully utilize all available CPU cores for processing VEs is difficult. The paper describes a pipeline VE architecture designed for multi-core CPU systems. The architecture enables development of VEs that l
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Preethish Nandan, Botlagunta. "Architectural trends in RISC-V, GPUs, TPUs, and domain-specific artificial intelligence accelerators." In Deep Science Publishing. Deep Science Publishing, 2025. https://doi.org/10.70593/978-93-49910-47-8_10.

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For years, the open-source RISC-V instruction set has been driving innovation in processor design. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. This unit should enable dynamic custom instruction sequence execution whose usage could be to compress binaries, obfuscate behavior, etc. RISC architectures are designed to integrate few instructions, thus lacking the micro-decoding mechanism. The open-source RISC-V ISA provides
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Conference papers on the topic "Micro-Architecture CPU en pipeline"

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Ben-Asher, Yosi, and Ibrahim Qashqoush. "An Extended pipeline RISC-V CPU architecture." In 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2024. https://doi.org/10.1109/mcsoc64144.2024.00090.

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Zhang, Wendi, Yonghui Zhang, and Kun Zhao. "Design and Verification of Three-stage Pipeline CPU Based on RISC-V Architecture." In 2021 5th Asian Conference on Artificial Intelligence Technology (ACAIT). IEEE, 2021. http://dx.doi.org/10.1109/acait53529.2021.9731161.

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Dodiu, Eugen, and Vasile Gheorghita Gaitan. "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation." In 2012 IEEE International Conference on Electro/Information Technology (EIT 2012). IEEE, 2012. http://dx.doi.org/10.1109/eit.2012.6220705.

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Hagiwara, Kesami, Tomoichi Hayashi, Shumpei Kawasaki, et al. "A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications." In 2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS). IEEE, 2018. http://dx.doi.org/10.1109/coolchips.2018.8373084.

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Bances P, Enrique, Vedant Dalvi, Urs Schneider, and Thomas Bauernhansl. "Deploying a Transformer-based Model in Microservices Architecture: An Approach for Real-Time Body Pose Classification." In 13th International Conference on Human Interaction & Emerging Technologies: Artificial Intelligence & Future Applications. AHFE International, 2025. https://doi.org/10.54941/ahfe1005921.

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Real-time body pose classification is essential in preventing injuries caused by repetitive strain or poor ergonomics. In industrial environments, ensuring worker safety often requires monitoring the poses of multiple individuals performing different tasks. However, analysing the movements of many workers simultaneously presents computational challenges, potentially impacting accuracy and latency. In this context, microservices architecture offers significant advantages for enabling individual application functionalities to operate independently. Also, this architecture allows systems to scale
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Ardalani, Newsha, Clint Lestourgeon, Karthikeyan Sankaralingam, and Xiaojin Zhu. "Cross-architecture performance prediction (XAPP) using CPU code to predict GPU performance." In MICRO-48: The 48th Annual IEEE/ACM International Symposium of Microarchitecture. ACM, 2015. http://dx.doi.org/10.1145/2830772.2830780.

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Cai, Xuyi, Ying Wang, Xiaohan Ma, Yinhe Han, and Lei Zhang. "DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture." In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2022. http://dx.doi.org/10.1109/micro56248.2022.00094.

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Yahya, Jawad Haj, Haris Volos, Davide B. Bartolini, et al. "AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications." In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2022. http://dx.doi.org/10.1109/micro56248.2022.00063.

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Qin, Guofeng, Yue Hu, Linyu Huang, and YuChen Guo. "Design and Performance Analysis on Static and Dynamic Pipelined CPU in Course Experiment of Computer Architecture." In 2018 13th International Conference on Computer Science & Education (ICCSE). IEEE, 2018. http://dx.doi.org/10.1109/iccse.2018.8468729.

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Delic-Ibukic, A. "Digital architecture for background calibration of pipeline ADCs." In 5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications. IEE, 2005. http://dx.doi.org/10.1049/cp:20050171.

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Reports on the topic "Micro-Architecture CPU en pipeline"

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Song, Frank. PR-015-0835-R01 Development of Variable Cathodic Protection Criteria. Pipeline Research Council International, Inc. (PRCI), 2010. http://dx.doi.org/10.55274/r0010716.

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The CP criteria for buried piping systems are not consistent in different global CP standards. For instance, the standard of the International Standard Organization (ISO) and the European standard (EN) offer more specific CP criteria with respect to environmental conditions such as soil resistivity, aeration, presence of bacteria, pipe temperature and overprotection. However, they do not have the -850 mV on-potential criterion contained in the NACE Standard SP 0169-2007. The Australian National Standard (SAA) recommends the use of coupons or an electrical resistance (ER) probe in conjunction w
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