Dissertations / Theses on the topic 'Microelectronic circuit'

Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Prof. Madhavan Swaminathan; Committee Member: Prof. Andrew Peterson; Committee Member: Prof. Sungkyu Lim

Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingping.

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.

Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

La récupération d’énergie est un thème de recherche prometteur qui explore un large éventail de sources. Parmi ces sources, on trouve l’énergie mécanique, thermique, électromagnétique, etc. Cette thèse se propose d’explorer des solutions techniques de récupération de l’énergie électromagnétique ambiante. Ce type d’énergie offre une belle opportunité pour participer à l’alimentation, partielle ou complète, d’un système de communication sans fil à basse consommation. Beaucoup d’applications intéressantes telles que les réseaux de capteurs sans fil (WSN), assurant ainsi l’IoT (internet of things), dans le domaine médical et dans la sécurité, sont dotés d’une antenne. Or cette antenne qui est un composant passif volumineux n’est utilisée qu’une faible fraction du temps pour les seules communications. Dans le cadre de la récupération d’énergie RF, l’idée est de mettre à profit ce composant pour glaner l’énergie électromagnétique ambiante, malgré la faible puissance récupérée. Associée à l’antenne, la récupération d’énergie RF est basée sur la mise en œuvre de diodes en redresseurs. Dans ce manuscrit, des diodes intégrées issues d’une technologie moderne : FDSOI 28 nm sont utilisées.A l’issue de ces travaux, trois « runs » dont deux en technologie FDSOI ont pu être réalisés. Des convertisseurs d’énergie RF, du type Dickson, d’un et deux étages, ont été conçus et réalisés à l’aide de cette technologie, mesurés et même comparés à des convertisseurs RF-DC réalisés avec une autre technologie BiCMOS 55 nm. Les convertisseurs réalisés sont à l’état de l’art au niveau du rendement de conversion énergétique pour une puissance donnée de l’ordre de -20 dBm. La technologie FD-SOI offre un nouveau degré de liberté à l’aide de la polarisation de la grille arrière (BG : Back Gate). Cette polarisation du BG permet de modifier les paramètres de l’élément non-linéaire à la base de la conversion. Par ailleurs, une étude sur la réalisation d’une diode Schottky intégrée dans le processus de la FDSOI 28 nm a même été envisagée. A l’issue de ces premières expériences, une méthode d’optimisation de la conception de ces convertisseurs Dickson à partir d’un cahier des charges simplifiée, a été proposée
Energy harvesting is a promising research theme which analyzes a wide range of sources for the application. These sources can be mechanical, thermal or electromagnetic, etc. Hereby, the work presented explores technical solutions for ambient electromagnetic energy harvesting. Electromagnetic energy is capable of partly or completely supplying energy to low-power wireless communication systems. Many interesting applications are feasible, such as, wireless sensor networks (WSN) ensuring IoT (Internet-of-Things), in the medical field, security, by using equipments containing an antenna. However, the antenna is a voluminous passive component which is utilized merely for a fraction of the time, i.e., just for communications. The underlying idea of RF energy harvesting is to use the antenna to harvest the ambient electromagnetic energy, despite the low power recovered. Associated with the antenna, the RF energy harvesting is based on implementing diodes in rectifiers. In this manuscript, integrated diodes from modern technology: FD-SOI 28 nm are studied.In this work, three run for RF energy harvesting are designed. Two of them are realized in FD-SOI technology. One and two stage Dickson rectifiers for RF energy harvesting using FD-SOI are designed, characterized, measured and compared to RF-DC converters made with 55nm BiCMOS technology. These rectifiers are state-of-the-art in terms of the power conversion efficiency for a given power of the order of -20 dBm. Furthermore, FD-SOI technology offers a new degree of freedom with the back gate polarization (BG). This polarization of the BG makes it viable to change the parameters of the non-linear elements at the base of the conversion. Moreover, an investigation of integrated Schottky diodes using FDSOI 28 nm is presented. At the end of these experiments, a method of optimizing of the design of these Dickson converters based on simplified specifications is proposed

Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Dr. Suresh K. Sitaraman; Committee Member: Dr. F. Levent Degertekin; Committee Member: Dr. Ioannis Papapolymerou; Committee Member: Dr. Madhavan Swaminathan; Committee Member: Dr. Nazanin Bassiri-Gharb. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.
Includes bibliographical references.

Thesis (Ph. D.)--Chemistry and Biochemistry, Georgia Institute of Technology, 2008.
Committee Chair: Dr. C. P. Wong; Committee Member: Dr. Boris Mizaikoff; Committee Member: Dr. Rigoberto Hernandez; Committee Member: Dr. Z. John Zhang; Committee Member: Dr. Z.L. Wang.

"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and therefore, are subjected to higher current densities. However, the technology is now reaching its fundamental limitations in terms of pitch, processability, and current-handling due to electromigration. Electromigration in solder bumps is one of the major causes of device failures. It is accelerated by many factors, one of which is current crowding. Current crowding is the non-uniform distribution of current at the interface of the solder bump and under-bump metallurgy, resulting in an increase in local current density and temperature. These factors, along with the formation of intermetallic compounds, can lead to voiding and ultimately failure. Electromigration in solder bumps has prevented pitch-scaling below 180-210 microns, producing a shift in the packaging industry to other interconnection approaches, specifically copper pillars with solder. This research aims to explore the electromigration resistance of an adhesive-based copper-to-copper (Cu-Cu) interconnection method without solder, which is thermo-compression bonded at a low temperature of 180C. While solder bumps are more susceptible to electromigration, Cu is capable of handling two orders of magnitude higher current density. This makes it an ideal candidate for next generation flip chip interconnections. Using finite element analysis, the current crowding and joule heating effects were evaluated for a 30 micron diameter Cu-Cu interconnection in comparison with two existing flip chip interconnection techniques, Cu pillar with solder and Pb-free solder. A test vehicle (TV) was fabricated for experimental analysis with 760 bumps arranged in an area-array format with a bump diameter of 30 micron. Thermo-mechanical reliability of the test vehicle was validated under thermal cycling from -55C to 125C. The Cu-Cu interconnections were then subjected to high current and temperature stress from 1E4 to 1E6 amps per square centimeter at a temperature of 130C. The results establish the high thermo-mechanical reliability and high electromigration resistance of the proposed Cu-Cu interconnection technology.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.
Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.
Includes bibliographical references.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.

Dans la conception des circuits électroniques les variations statistiques des valeurs des paramètres des circuits doivent être prises en compte car elles ont un impact sur la qualité des circuits fabriques. Ces fluctuations statistiques essentiellement dues au processus de fabrication des tolérances, induisent des variations dans les réponses des circuits fabriqués. Le rendement de fabrication, qui est la proportion des circuits fabriqués répondant à un ensemble de contraintes d'acceptabilité spécifiées par le concepteur, est d'un intérêt considérable. Obtenir un rendement acceptable est l'un des principaux objectifs d'un concepteur de circuits électroniques. La méthode de Monte-Carlo a été utilisée pour simuler les variations dans les paramètres des composants ainsi que pour estimer le rendement de fabrication. Cette méthode est choisie a cause de sa généralité et de sa faible dépendance des variables stochastiques. Un programme fondée sur cette méthode a été élaboré et couplé au simulateur SPICE-PAC dont la structure modulaire se prête mieux aux exigences de l'analyse statistiques. Lorsque le rendement de fabrication est faible, il est nécessaire de l'améliorer. C’est la méthode des centres de gravite qui a été utilisée pour optimiser le rendement. L’échantillonnage statistique est amélioré grâce à la méthode des points communs. Malgré que la méthode des centres de gravite soit robuste et d'une utilisation aisée, elle peut être piégée dans optimum local du rendement. Pour résoudre ce problème, nous avons propose une approche d'optimisation du rendement de fabrication qui combine la méthode des centres de gravite et la méthode du recuit simulé

La electrónica orgánica/impresa está continuamente creciendo en interés, con la aparición de nuevas propuestas y aplicaciones. Este tipo de tecnologías no pretenden competir directamente con las que provienen de la industria tradicional basada en Silicio, sino que tienen como propósito complementarla con nuevos dispositivos que proporcionen ciertas ventajas en determinadas situaciones, ya sea en términos de coste u otras. Sin embargo, en lo que se refiere al campo del procesado digital queda mucho trabajo por hacer para, paulatinamente, ir siguiendo los pasos del modelo ‘fabless’ que rige el mercado de semiconductores actual. Este modelo consiste en la deslocalización entre los equipos de diseño y los fabricantes. Respecto a dicho progreso me refiero no solo a las mejoras que acontecen a nivel de procesos de fabricación, sino también en el campo de la automatización de los procesos de diseño. Nuestro grupo de investigación concibió una novedosa estrategia para producir, de manera eficiente, diseños de circuitos digitales para electrónica impresa, basados en lo que denominamos Inkjet-configurable Gate Arrays, aprovechando las ventajas de la impresión digital. Estos Inkjet Gate Arrays consisten en matrices de transistores sobre sustratos flexibles que, una vez conectados mediante impresión digital, conforman puertas lógicas; las cuales, en su conjunto, materializan circuitos. El trabajo presentado en esta tesis se centra en una etapa específica de cualquier flujo de diseño común de circuitos integrados, llamada síntesis física. En concreto, este trabajo proporciona una novedosa metodología para resolver el problema de ubicar y conectar, ‘Placement and Routing’, los circuitos sobre las mencionadas matrices de transistores, teniendo en cuenta su rendimiento, y con independencia de la tecnología de fabricación. Se aborda la manera de cómo tratar con tecnologías impresas diferentes, que puedan presentar distintos niveles de rendimiento, normalmente debidos a la alta variabilidad intrínseca a los procesos de fabricación actuales. En tales casos, un factor clave para asegurar que la colocación de los circuitos sea funcionalmente correcta es poder procesar de manera efectiva la información sobre la distribución de fallos de las matrices. Además del concepto de mapeo según el rendimiento, la novedosa heurística aquí propuesta proporciona la capacidad de personalizar los circuitos, lo que permite mayor flexibilidad en su construcción, dependiendo de distintas razones u objetivos posibles (p. ej. congestión). Esta metodología no solo es conveniente para los primeros pasos que, en la actualidad, se están llevando a cabo en el desarrollo de prototipos de circuitos digitales para la electrónica orgánica, sino que también es escalable hacia nuevas mejoras en el rendimiento de las tecnologías de fabricación, así como en tamaños y densidad de integración.
Organic/Printed Electronics are, day by day, increasing on interest, as new applications are being proposed and developed. This kind of technologies do not intend to compete directly with the Silicon-based well-established industry, but rather to complement it with new devices that are advantageous for certain situations, whether in terms of cost or others. However, in the digital processing domain there is still much work to be done to, slowly but steadily, follow the steps of the conventional fabless model that rules today’s semiconductor market. I am referring not only to progresses at fabrication level, but also on the field of Electronic Design Automation. Our research group conceived a novel strategy to efficiently produce Printed Electronics digital circuit designs based on what we called Inkjet-configurable Gate Arrays, which takes advantage of digital printing techniques. The Inkjet Gate Arrays consist in matrices of transistors over flexible substrates that, after being connected by digital printing techniques, they describe logic gates, and thus circuits. The work presented in this dissertation targets a specific stage of any common Integrated Circuit design flow, referred to as physical synthesis. Specifically, my contribution provides a new approach to the Placement and Routing problem, where circuits are mapped onto the Inkjet Gate Arrays in a technology independent yield-aware manner. I tackle the issue of dealing with different Printed Electronics technologies that might present distinct yield properties, usually due to the intrinsic high variability of current fabrication processes. In such cases, being able to effectively process the IGA’s fault distribution information is key to ensure that the mapped circuits will be capable of working correctly, from a functional perspective. In addition to the yield awareness concept, the circuit personalization capabilities of the novel P&R heuristic proposed herein allow more mapping flexibility, depending on different possible reasons/purposes (e.g. congestion). This approach is not only convenient for today’s first steps of digital circuit prototyping over Organic Electronics, but also scalable to future technological improvements at yield level, and on sizes and integration density.

Le disiliciure wsi::(2) pour la metallisation d'un circuit vlsi (contacts et lignes d'interconnexion) est forme a une temperature aussi basse que possible en utilisant la structure "sandwich" a-si: h(150 a)/w(110 a)/a-si: h(540 a)/c-si implantee par des ions a faible courant et a temperature ambiante. La concentration residuelle d'oxygene dans les couches de w et de a-si:h et a leur interface a une influence decisive sur la formation et la resistivite de wsi::(2). Les plus faibles temperatures de formation de wsi::(2) atteintes sont les plus basses, 550**(o)c apres recuit, 350**(o)c apres implantation de w puis recuit. Les resistivites sont aussi plus faible. Interet et sensibilite de la spectroscopie ir dans la caracterisation des impuretes

En els darrers anys ha anat creixent l’interès per la fabricació de sistemes de baix cost, flexibles i sobre gran àrea com, per exemple, les etiquetes RFID per a identificació de productes, les pantalles flexibles o les etiquetes intel•ligents entre d’altres. La tecnologia d’impressió electrònica (Printed Electronics) s’ha posicionat com una de les tecnologies alternatives de fabricació més prometedores pel fet de no utilitzar tècniques fotolitogràfiques i de buit. Alhora, la millora en materials orgànics i inorgànics ha provocat un increment en les prestacions dels dispositius impresos. Tot i això, la fabricació de transistors orgànics, element clau per a construir circuits electrònics d’adquisició o processament, es veu afectada per la poca resolució i registre entre capes de les tecnologies d’impressió actuals com inkjet o gravat. Per compensar-ho, els transistors implementats utilitzant aquestes tecnologies tenen llargades de canal molt grans i grans solapaments entre porta i font/drenador. Aquestes grans dimensions limiten les prestacions dels transistors impresos, tot i les millores obtingudes en els materials. Aquesta tesi està enfocada en contrarestar els problemes provocats per la poca resolució en impressió utilitzant tècniques de compensació i noves geometries de dispositius mantenint el procés completament inkjet. Aquest treball s’enfoca en el desenvolupament de dispositius microelectrònics passius i actius implementats amb maquinària inkjet de baix cost. He enfocat el meu esforç en el disseny, la fabricació i la caracterització (elèctrica i morfològica) amb l’objectiu de fer possible la fabricació de circuits integrats orgànics. En el marc de la tesi, s’han fabricat varis milers de transistors, capacitats i resistències exclusivament amb tecnologia inkjet. Tots els dispositius s’han caracteritzat tant elèctrica com morfològicament. S’ha dut a terme un gran número d’experiments per assegurar una fabricació eficient, estudiar la variabilitat dels paràmetres i obtenir dades estadísticament significatives. La variació en els processos de fabricació de transistors porta a una important variabilitat en els paràmetres dels dispositius impresos fins ara poc estudiada. Escalabilitat, variabilitat i rendiment s’han analitzat utilitzant diferents estratègies. S’han obtingut circuits digitals amb un comportament adient, demostrant l’estat actual de la tecnologia inkjet per a integrar dispositius impresos en circuits. Aquest és un primer pas en el camí per fabricar circuits més complexes amb tecnologia d’impressió inkjet. La quantitat de mostres fabricades amb tecnologia inkjet es pot considerar com un assoliment important i contribueix a millorar el coneixement del comportament i els orígens de fallades dels dispositius orgànics i impresos.
In the last years there has been a growing interest in the realization of low-cost, flexible and large area electronic systems such as item-level RFID tags, flexible displays or smart labels, among others. Printed Electronics has emerged as one of the most promising alternative manufacturing technologies due to its lithography- and vacuum-free processing. Related to this, organic and inorganic solution processed materials advanced rapidly improving the performance of printed devices. However, the fabrication of organic transistors, key element to build circuits for acquisition and processing, suffers from the poor resolution and layer-to-layer registration of current printing techniques such as inkjet and gravure printing. To compensate that transistors implemented in those technologies have large channel lengths and large gate to source/drain overlaps. These large dimensions limit the performance of the printed transistors, despite the improvements in materials. This thesis focuses on circumventing the printing resolution challenges using compensation techniques and new layout geometries while keeping an all-inkjet purely printing process. The dissertation deals with the development of microelectronic passive and active devices implemented using low-cost inkjet printing machinery. I focussed my effort in the design, manufacturing & characterization (electrical and morphological) points of view in order to allow the fabrication of organic integrated circuits. Several thousands of resistors, capacitors and transistors were fabricated, all of them fully inkjet-printed. All devices were morphologically and electrically characterized. A high number of experiments were developed to ensure efficient manufacturing and report on parameter variation, thus obtaining statistically significant data. Process variations present in transistor fabrication lead to a certain variability on the resulting transistor parameters that need to be taken in account. Scalability, variability and yield were analysed by using different strategies. Fabricated inverters show a clear inversion behaviour demonstrating the state of the inkjet fabrication process to integrate printed devices in circuits. This is a first step in the way to fabricate all-inkjet complex circuits. The amount of samples manufactured by the fully inkjet printing approach can be considered an outstanding achievement and contributes to a better knowledge of the behaviour and failure origins of organic and printed devices.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.
Includes bibliographical references (leaves 116-127). Also available in electronic version. Access restricted to campus users.

Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the substrate or the substrate and the board. Compliant interconnects are replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic component. Research is being conducted to develop compliant interconnect structures which offer good mechanical compliance without adversely affecting electrical performance, thus obtaining good thermo-mechanical reliability. However, little information is available regarding the behavior of compliant interconnects under shock and impact loads. The objective of this thesis is to study the response of a proposed multi-path compliant interconnect structure when subjected to shock and impact loading. As part of this work, scaled-up substrate-compliant interconnect-die assemblies will be fabricated through stereolithography techniques. These scaled-up prototypes will be subjected to experimental drop testing. Accelerometers will be placed on the board, and strain gauges will be attached to the board and the die at various locations. The samples will be dropped from different heights to different shock levels in the components, according to Joint Electron Devices Engineering Council (JEDEC) standards. In parallel to such experiments with compliant interconnects, similar experiments with scaled-up solder bump interconnects will also be conducted. The strain and acceleration response of the compliant interconnect assemblies will be compared against the results from solder bump interconnects. Simulations will also be carried out to mimic the experimental conditions and to gain a better understanding of the overall response of the compliant interconnects under shock and impact loading. The findings from this study will be helpful for improving the reliability of compliant interconnects under dynamic mechanical loading.

Thesis (Ph. D.) -- University of Maryland, College Park, 2009.
Thesis research directed by: Reliability Engineering Program. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

En raison de la demande de miniaturisation croissante dans l’industrie microélectronique, il est nécessaire de développer des circuits imprimés multicouches (PCB, Printed Circuit Board) présentant une densité d’interconnections de plus en plus élevée. Avec leurs bonnes propriétés physico-chimiques et mécaniques et un relatif faible coût, les matériaux composites à base de résine époxy sont des matériaux de premier choix pour ce type d’application. Cependant, la réduction de la taille des connexions électriques de cuivre (largeur < 1 µm), implique que l’adhésion cuivre/époxy soit améliorée. Dans la littérature, des études ont montré que le taux de réticulation des résines epoxy est un paramètre clé, contrôlant la résistance chimique de la résine epoxy (vis-à-vis des procédés industriels d’impression de cuivre par voie chimique) et les propriétés d’adhésion du cuivre sur le substrat composite.L’objectif de cette thèse est d’étudier de façon approfondie la cinétique de réticulation d’un composite époxy/silice (ABF) utilisé en production de masse dans l’industrie microélectronique afin de proposer un protocole de fabrication des circuits imprimés en fonction du taux de réticulation.Le comportement rhéologique du matériau composite en fonction du taux de réticulation a été étudié par analyse mécanique dynamique (DMA). L’influence du taux de réticulation sur les processus de gélification et de vitrification est présentée et une analyse du comportement viscoélastique de la résine epoxy près de la transition vitreuse est discutée. Le modèle WLF est utilisé pour décrire la dynamique de réseau du polymère. La cinétique de réticulation du composite a été étudiée in situ en spectroscopie proche-infrarouge (NIR) et en calorimétrie différentielle à balayage (DSC) en modes isotherme et non-isotherme. L’analyse iso-conversionnelle a permis de déterminer l’énergie d’activation de la réaction de réticulation. Cependant, une modélisation plus approfondie de la cinétique de réticulation a été nécessaire en raison d’une contribution de diffusion s’ajoutant à la contribution chimique de la réaction. Cette étude a montré que les cinétiques de réticulation peuvent être décrites par le modèle auto-catalytique d’ordre n combiné aux modèles de Rabinowitch et WLF-modifié, modèles tenant compte de la contribution de diffusion. Ce modèle a permis de prédire le comportement du matériau dans une large gamme temps/température et d’établir le diagramme Température-Temps-Transformation du matériau .Compte tenu de l’importance du taux de réticulation sur les propriétés d’adhésion des connexions électriques de cuivre, une méthode de mesure du taux de réticulation sur des PCB industriels a été développée. La spectroscopie infrarouge en réflexion diffuse (DRIFTS) s’est avérée être une technique d’analyse parfaitement adaptée. L’influence du taux de réticulation sur l’étape de “desmear” du procédé de fabrication a également été étudiée. Cette étape, constituée d’une phase de gonflement de la résine epoxy (swelling) suivie d’une attaque oxydante au permanganate et d’une étape de réduction, est déterminante quant à la rugosité de surface obtenue et donc l’adhésion du cuivre sur le substrat composite. Une méthode originale a été développée pour déterminer le profil de diffusion de l’agent de gonflement (sweller) au sein du matériau, méthode alliant microtomie et analyse chromatographique. L’effet des conditions de “swelling” sur la rugosité finale du matériau a été déterminé par microscopie à force atomique (AFM). Des tests d’adhésion du cuivre ont également été réalisés afin d’étudier l’influence du taux de réticulation de la résine epoxy et de la rugosité de surface du composite sur la force d’adhésion. Finalement, une bonne adhésion du cuivre (environ 4 N/cm) pour des surfaces de faible rugosité (< 10 nm)
Due to the increasing miniaturization in microelectronics the manufacturing of densely interconnected multilayer printed-circuit boards (PCB) is needed. With their well-balanced physico-chemical and mechanical properties and low cost, epoxy-based composites are insulating materials of prime choice. However, to achieve interconnections at a lower scale (copper line width down to ca. 1 µm), the adhesion between the composite substrate and the copper interconnections must be enhanced. Previous studies showed that the degree of curing of the epoxy matrix (i.e. conversion of crosslinking reaction) is one key-parameter, driving the matrix chemical and mechanical resistance (during the PCP manufacturing process) and the composite/copper line adhesion properties.In this work we present and discuss an in-depth study of the curing kinetics of an epoxy/silica composite (ABF) relevant to the microelectronics industry. The final objective is to propose a process protocol of the PCB manufacturing as function of the degree of curing.The rheological behaviour of the composite material is investigated by dynamic mechanical analysis (DMA). The gelation and vitrification mechanisms are presented as a function of the degree of curing. The viscoelastic behavior of the epoxy matrix near the glass-transition is studied and is shown to be well-described by the WLF model.The curing kinetics of the epoxy composite are studied by in situ near-infrared (NIR) spectroscopy and both isothermal and non-isothermal differential scanning calorimetry (DSC). Iso-conversional analyses are performed to determine the apparent activation energy of the curing reaction. Due to a non-negligible contribution of the diffusion part in the curing reaction, further modelling was needed to achieve a complete description of the curing kinetics. This study showed that the curing kinetic is well-described by the nth-order autocatalytic fitting model in combination with the Rabinowitch/modified-WLF models, taking into account the diffusion contribution. This model is used to predict the material behaviour in a wide time/temperature range and to propose a Temperature-Time-Transformation diagram of the material.Due to the influence of the degree of curing on the adhesion of copper electrical lines, an experimental method for the measurement of the degree of curing of industrial PCB was developed. Diffuse-reflectance infrared spectroscopy (DRIFTS) is found to be a versatile and accurate technique. The influence of the degree of curing on the “desmear” step of the PCB manufacturing process is studied as well. The “desmear” step proceeds in the swelling of the epoxy matrix and the subsequent permanganate etching and reduction reactions. The “desmear” step is quite important regarding the composite surface roughness and, as a consequence, the adhesion of the copper lines. An original method for the determination of the diffusion profile of the sweller through the depth of the material was developed using microtomy and chromatography. The effect of swelling experimental parameters on the final roughness of the composite is determined by atomic force microscopy (AFM). Adhesion tests of copper lines on the composite substrate are performed to study the influence of the initial degree of curing and the roughness on the peel strength. Good adhesion of copper (about 4 N/cm) is achieved for a low substrate roughness (< 10 nm)

Orientador: José Antonio Siqueira Dias
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
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Resumo: Esse trabalho visa conceber um circuito baseado na teoria e técnica translinear a fim de ser utilizado na camada física de geração de pulsos de transmissão de dados chamado LIN "Local Interconect Network" difundido largamente na indústria automotiva e utilizado como protocolo de transmissão de dados de baixa velocidade 10kbit/seg ou 20kbit/seg em anel. Esse projeto será parte integrante da malha de controle analógico dessa camada física afim de gerar transições previamente estabelecidas com taxas de subida e descida constantes em 1 Volt por micro segundo (1V/us). O projeto consiste em desenvolver um gerador de pulsos de relógio "clock" utilizando um oscilador de relaxação com corrente de referencia gerada por um circuito translinear. A implementação do circuito será em tecnologia BiCMOS trabalhando na especificação automotiva de VBAT de 6 V a 40 V e variação de temperatura de -40ºC a 150ºC e devera ser capaz de gerar uma frequência inversamente proporcional a variação positiva da bateria convertendo-se em pulsos finitos de "clock" por intermédio de um oscilador de relaxação que realimentara o sistema de controle ao qual gerencia a "forca" a ser aplicada ao barramento LIN a qual varia de 1k Ohm/1nF a 500Ohm/10nF
Abstract: A novel technique to control the LIN (Local Interconnect Network) bus slew rate transitions in automotive environment, where large fluctuations of the battery voltage are present, is reported. A bipolar translinear circuit generates a non-linear current that is used to modulate a MOS relaxation oscillator, producing a clock frequency that delivers a constant number of pulses during the LIN bus digital signal transition. This frequency modulated clock when applied to a digitally controlled analogue wave-shape driver results in a LIN bus digital transition at 10kBit/s or 20kBit/s with a slew-rate that is constant and independent of the car battery voltage. Experimental results measured in an IC implemented in a BiCMOS process showed that constant slew-rate transition of 1 V /us is obtained for battery voltages varying from 6 V to 40 V, over the temperature range of -40ºC to 150ºC
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

The use of aluminum nitride as a substrate material for microelectronics is examined. A brief look at thermal, mechanical, and electrical properties of aluminum nitride show that it is a viable alternative material for this use. A study of the interfaces between aluminum nitride and several thick film pastes (palladium silver conductor, ruthenium oxide resistor, and gold conductor) was performed with optical microscopy, scanning electron microscopy, and energy dispersive spectroscopy. Results of this investigation showed that the contaminants in the substrate material that affect thermal conductivity do not affect the adhesion of the thick film pastes. However, it was found that the lack of certain elements in the binder of the thick film paste could lead to weaker adhesion, and severe degradation of the thick film's adhesion during thermal cycling.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitaraman.

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
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Resumo: Este trabalho envolve o estudo de uma nova arquitetura para filtros integrados com freqüência de corte em sub-hertz, orientado para aplicações na área biomédica, possuindo requisitos como baixo consumo e baixa tensão de operação. Devido a sua aplicação também em sistemas implantáveis, o circuito deve operar com tensão de alimentação variando de 0,9V até 1,6V. Para as aplicações envolvendo circuitos implantáveis, as variações de temperatura não são críticas, embora o circuito tenha sido projetado para uma variação de 0°C até 100°C. Este estudo engloba análise, projeto, simulação, fabricação e caracterização experimental do filtro, sendo também testado com um modelo de sinal de eletrocardiograma (ECG). O filtro proposto é do tipo gm-C e se utiliza do controle da impedância vista pela fonte de um transistor NMOS para o ajuste da freqüência de corte. Comparativamente a outras topologias, possui vantagens como o simples controle da freqüência de corte, além da facilidade de imposição de uma tensão de modo-comum. Em termos de desvantagens, uma das principais está no fato de haver distorções significativas para sinais de alta amplitude (tipicamente acima de algumas dezenas de mili-volts). Na maioria das aplicações biomédicas, ou mesmo, por exemplo, sinais de origem sísmica, onde ambos possuem componentes de freqüência bem baixas, as amplitudes são de baixa magnitude. O principal parâmetro testado no circuito foi a freqüência de corte e seu ajuste com a corrente de polarização. Ainda, de forma a testar a capacidade do circuito de processar um sinal sem distorção, impondo um modo comum ao mesmo, foi utilizado o padrão adotado pela norma européia CENELEC (European Committee for Electrotechnical Standardization) para o sinal de ECG. No desenvolvimento foram utilizadas técnicas de projeto para circuitos de baixa potência, assim como utilização do modelo compacto ACM (Advanced Compact Model) para dimensionamento e cálculos manuais, obtendo-se expressões simples para a freqüência de corte. Fatores importantes para este tipo de projeto como correntes de fuga e nível de inversão do canal foram considerados, assim como as influências das capacitâncias parasitas. As correntes de fuga possuem um modelamento muitas vezes questionável e impreciso. Deste modo, de forma a obter uma idéia clara das fugas envolvidas, duzentos transistores NMOS unitários (0,8?m/10?m) foram colocados em paralelo para medir a fuga nas junções em função da temperatura e tensão reversa de polarização. Os dados obtidos de dez amostras de um mesmo lote mostraram um comportamento dentro do esperado. A média medida das correntes de fuga de um transistor unitário para as temperaturas de 27°C e 85°C foram respectivamente 46fA e 3,4pA. Dois filtros foram projetados para obter uma maior flexibilidade nos testes. Ambos os filtros se utilizam de uma fonte de corrente proporcional à temperatura (PTAT) única de valor típico medido igual a 5,65nA como polarização. Cada filtro se utiliza de um OP-AMP para impor o modo-comum e um divisor de corrente de Bult, obtendo-se uma corrente da ordem de pA para polarizar o filtro propriamente dito. O primeiro filtro usa a própria corrente de PTAT para polarização do nó de entrada que define a freqüência de corte. Com isto, é possível uma compensação de primeira ordem para sua variação com temperatura. O segundo filtro possui uma entrada de corrente independente, de forma que a mesma pode ser alterada externamente, possibilitando verificar a variação da freqüência de corte em função da polarização. A verificação funcional dos sub-circuitos que constituem o filtro, assim como todo o sistema, foi realizada utilizando-se simuladores SMASH/PSPICE/Cadence com modelos Bsim3v3, considerando-se a variação dos parâmetros de processo e intervalo de temperatura de 0ºC à 100ºC. O layout do circuito foi realizado através do programa Cadence, e possui uma área efetiva de 0,263mm2 para os dois filtros. A fabricação foi feita na foundry da AMS, usando-se tecnologia CMOS 0,35?m. A caracterização experimental envolveu análise da freqüência de corte, fugas em junções, resposta a um sinal de ECG, consumo e, comportamento com relação à tensão de alimentação. Resultados experimentais para a freqüência de corte do primeiro filtro, em dez amostras, resultaram em uma média de 2,38Hz e desvio padrão de 0,32Hz. A corrente de referência PTAT apresentou uma média de 6,90nA e um desvio padrão de 1,04nA. O comportamento PTAT da mesma pôde ser observado experimentalmente (de forma indireta) na faixa de 27°C à 85°C. A freqüência de corte em função da corrente de polarização foi analisada usando-se o segundo filtro, que confirmou a dependência linear por quase uma década de variação da corrente de entrada. Também, as respostas aos padrões de sinal de ECG de baixa e alta amplitude foram analisadas com sucesso no primeiro filtro. O trabalho teve seus objetivos alcançados, realizando etapas de especificação, projeto, layout e caracterização. Os resultados experimentais obtidos estão dentro do esperado, validando a arquitetura proposta de um filtro passa-altas, totalmente integrado, com freqüência de corte em sub-hertz
Abstract: This work aims the study of a new topology for integrated filters with cut-off frequencies around sub-hertz, oriented to biomedical applications, having requisites as low consumption and low voltage operation. Due to its application also in implantable systems, the circuit must operate with supply voltage varying from 0.9V to 1.6V. For applications involving implantable circuits, temperature variations are not critical, although this circuit was designed for an operation from 0ºC to 100ºC. This study conducts analyses, design, simulation, fabrication and experimental characterization of the filter, being tested with an electrocardiogram signal (ECG). The proposed filter is a gm-C type and uses the control of the impedance seen from the source of a NMOS transistor to adjust the cut-off frequency. Comparatively to other topologies, it has advantages as simple cut-off frequency control and its easiness to impose a common-mode voltage. As drawbacks, one of the most significant is in the fact of having significant distortions with high amplitude signals (tipically above some tens of milli-volts). In most biomedical applications, or even signals with a seismic origin, for example, where both have very low frequency components, their amplitudes are low in magnitude. The main tested parameter in the circuit was the cut-off frequency and its adjustment with the biasing current. Besides, as a test for the circuit capability of processing a signal without distortion, while imposing it a common-mode, it was used a standard from an European norm called CENELEC (European Committee for Electrotechnical Standardization) for the ECG signal. In the development were used design techniques for low power circuits, as well as the use of the compact model ACM (Advanced Compact Model) for dimensioning and hand calculations, getting simple expression for the cut-off frequency. Important factors for this kind of project as leakage current and channel inversion level were considered, also the influence of stray capacitances. The leakage current has a doubtful and imprecise modeling. Herewith, as a way to get a better idea of leakage values involved, two hundred unity NMOS transistors (0,8?m/10?m) were placed in parallel in order to measure the junction leakages as a function of temperature and reverse voltage biasing. The obtained data for ten samples of a single batch showed a behavior as expected. The mean value for the leakage currents of a unity transistor for temperatures between 27ºC and 85ºC were repectivelly, 46fA and 3.4pA. Two filters were designed to obtain a larger flexibility during the tests. Both filters use a unique PTAT current source with measured typical value equal to 5,65nA as biasing. Each filter uses an OP-AMP to impose a common-mode voltage and a Bult current divider, getting a current with a magnitude of pA to bias the filter itself. The first filter uses the proportional to temperature (PTAT) current directly from source to bias the input branch that defines the cut-off frequency. The second filter has and independent input, so that it can be changed externally, allowing to verify the cut-off frequency as a function of biasing current. The functional verification of the sub-circuits that build-up the filter, as the whole system, was performed using simulators SMASH/PSPICE/Cadence with Bsim3v3 models, considering the process parameters variations and temperature interval from 0ºC to 100ºC. The circuit layout was developed through Cadence program, and has an effective area of 0,263mm2 for both filters. The fabrication was done on AMS foundry, using the CMOS 0.35?m technology. The experimental characterization considered cut-off frequency analysis, junction leakages, response to an ECG signal, consumption and, behavior with respect to supply voltage. Experimental results for cut-off frequency of the first filter, on ten samples, resulted in a mean value of 2.38Hz with a standard deviation of 0.32Hz. The PTAT current presented a mean value of 6.90nA with 1.04nA of standard deviaton. The PTAT behavior of this current could be experimentally observed on range of 27ºC to 85ºC. The cut-off frequency as a function of biasing current was analyzed using the second filter, which confirmed the linear dependency for almost a decade of input current variation. Also, the responses to ECG standard signals of low and high amplitudes were analyzed successfully on the first filter. This work has achieved its purpose, making specifications stages, design, layout and characterization. The experimental results obtained are within expected, validating the proposed architecture of a high-pass filter, fully integrated, with cut-off frequency in sub-hertz
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e equações que modelam um circuito são compatíveis com a forma desse problema de otimização. Os receptores para sistemas de comunicação modernos realizam o processo de downconvertion usando uma freqüência intermediária baixa ou diretamente em banda-base. As topologias de receptor Zero-IF e Low-IF são preferidas por sua alta capacidade de integração e baixo consumo de área e de potência. Os filtros analógicos são blocos de composição básicos nesses sistemas. Neste trabalho é desenvolvida uma metodologia de projeto baseada na aplicação de programação geométrica para projeto de filtros Gm-C. A metodologia de projeto foi usada para projetar filtros analógicos complexos e reais para os padrões de comunicação Bluetooth e Zigbee IEEE/802.15.4. Os resultados obtidos mostram que a metodologia de projeto proposta neste trabalho é uma solução efetiva para reduzir o tempo de projeto e otimizar o desempenho de filtros analógicos.
The tendency of the microelectronic market is to integrate in the same chip complete electronic systems, including digital, analog and RF circuits simultaneously. The analog part of those systems represents the bottleneck in the design process. The complexity of analog design makes this one an intuitive and creative process but time expensive. An alternative methodology for analog integrated circuits design is to represent the design as a mathematical optimization problem known as geometric programming. The advantages are: global optimum achieved efficiently, and the possibility of design automation. The main disadvantage, is that all the parameters or equations that characterize a circuit are not compatible with the form of this optimization problem. Modern receivers perform downconvertion of the signal using very low, or zero intermediate frequency. Zero-IF and Low-IF topologies are preferred because of their high integration capabilities, and low area and power consumption. Analog filters are basic building blocks of such systems. In this work, a design methodology based on geometric programming is developed, for automated and optimal design of Gm-C filters. The design methodology was used to design analog complex and real filters for the digital communications standards Bluetooth and Zigbee IEEE/802.15.4. The results show that the design methodology proposed in this work is an effective solution for fast, automated and optimal analog filter design

Actuellement, il est important de disposer des moyens de comparaison des differentes technologies (bipolaires si et ga as, mos si et mesfet ga as) selon les criteres vlsi (vitesse, puissance, densite d'integration, rendement de fabrication, cout des processus, outils de cao disponible, etc. . . ); nous donnons une modelisation simplifiee des performances dynamiques des portes ecl cml et nous montrons comment les portes complexes peuvent etre ramenees aux portes simples pour l'evaluation des performances. Nous presentons les regles de dessin simplifiees, definies a partir des technologies hbip 3a et hbip 3b de thomson sdc et nous en deduisons une methodologie d'implantation symbolique sur grille pour les circuits non satures ecl cml, une bibliotheque de fonctions a pu etre etablie. Cette strategie permet un dessin rapide des masques, d'une part, et d'autre part, une evaluation de la surface du circuit integre permettant ainsi de comparer l'implantation de fonction suivant differentes versions ecl cml; ceci nous a permis de comparer les differentes versions d'un vehicule de test: les surfaces et les frequences maximales de fonctionnement pour differentes puissances dissipees. Cette comparaison montre l'interet des familles permettant le "series gating" par rapport aux familles ne permettant que le et cable (stl) et nous permet de comprendre l'interet pour les logiques "multilevel differential ecl" qui offre une grande puissance logique par porte complexe. Nous proposons ensuite une solution alternative a l'utilisation de l'empilement d'etages differentiels et nous comparons les performances des versions binaires des additionneurs 3 entrees-2 sorties et 7 entrees- 3 sorties avec des versions multivaluees en courant, l'additionneur 7-3 permet de diminuer le nombre de couches logiques necessaires pour la realisation des arbres de wallace des multiplicateurs combinatoires

Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e Computação
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Resumo: Este trabalho descreve o desenvolvimento de um sensor de umidade relativa que tem como elemento sensor um polímero (poli(óxido de etileno-co-epicloridrina)84:16), cuja condutividade varia com a umidade. O polímero foi depositado por casting sobre um substrato cerâmico sobre o qual, por sua vez, foram depositados dois eletrodos em forma interdigitada aos quais é aplicada uma corrente alternada com forma de onda quadrada e amplitude DC nula. Este sinal de excitação é produzido por um circuito integrado que também realiza a leitura da tensão nos terminais do eletrodo. Além disto, o circuito contém um sensor de temperatura cuja informação é necessária para a correta leitura da umidade. Amostras do circuito integrado, cujo projeto é parte deste trabalho, foram fabricadas em tecnologia CMOS 0,35um e caracterizadas juntamente com o elemento sensor. Os resultados mais relevantes da caracterização do sensor desenvolvido são: Faixa de medição: máx 90%RH para evitar condensação; Sensibilidade do elemento sensor: 188,83W/%RH a 55%RH; Histerese: 3,4% a 55%RH; Temperatura de operação: 0 a 60oC; Tempo de resposta: +/-30s. A principal contribuição deste trabalho reside na proposição de um sensor de umidade que é composto de um elemento sensor polimérico e de um circuito integrado que realiza o condicionamento e leitura dos sinais envolvidos, constituindo deste modo uma solução robusta e de baixo custo
Abstract: This work describes the development of a relative-humidity sensor, which uses as sensing element a polymer (poly(ethylene oxide-co-epichlorohydrin)84:16) whose conductivity varies with humidity. The polymer was deposited by casting over a ceramic substrate, on which two interdigitized electrodes were previously deposited. An integrated circuit, also developed as part of the work, provides a square wave current with no DC component as excitation signal to the electrodes and reads the voltage across them. The developed integrated circuit also includes a temperature sensor, whose produced signal is used to yield the correct humidity measurement. Samples of the integrated circuit were fabricated in 0.35µm CMOS technology and were characterized together with the sensing element. The most relevant characteristics of the developed humidity sensor are: Measuring range: 90%RH max, to avoid condensing; Sensor element sensitivity: 188,83W/%RH at 55%RH; Hysteresis: 3,4% at 55%RH; Operating temperature: 0 to 60oC; Response time: +/-30s. The main contribution of this work is the proposition of a humidity sensor, which is based on a compound of a polymeric sensing element that operates in conjunction with an integrated circuit. The developed integrated circuit performs the necessary conditioning of the involved signals, in addition to include a temperature sensor. The developed humidity sensor has proven to be robust and can be produced at a relative low cost
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

Dans le cadre de ce memoire nous avons etudie sur le plan theorique l'influence de la tension acceleratrice des electrons incidents sur les dimensions des traces obtenus. En s'appuyant sur des resultats obtenus anterieurement nous avons simule pour une methode de monte-carlo, les trajectoires des particules incidents. Nous avons pu ainsi localiser l'energie deposee par les electrons incidents les electrons retrodiffuses par le substrat et les electrons secondaires. L'ensemble des resultats montre l'interet theorique presente par l'emploi de tensions plus elevees (100 kev) que celles habituellement utilisees en microlithographie (20 a 50 kev). Afin de preciser les differents mecanismes intervenant dans la modification de la resine nous avons etudie a l'aide d'un analyseur de pertes d'energie des electrons l'evolution au cours de l'irradiation du spectre obtenu. Les performances obtenues sont illustrees par differentes gravures representant le trace de motifs realises dans une couche de pmma de 0,5 micron d'epaisseur, avec des lignes de 0,4 micron de large

L'isolation des circuits cmos est une des cles de leur miniaturisation extreme. Les technologies d'isolation de l'ulsi devront eliminer les risques de courants de fuite et de "latch up" a la peripherie du caisson, ainsi que les phenomenes perimetriques, dus a l'isolation de champ, qui degradent les performances des petits transistors (tension de seuil, capacite de diffusion). L'isolation dielectrique du caisson par tranchee profonde est choisie ici pour sa compatilibite avec les filieres de fabrication existantes. La principale difficulte de la technique reside dans la gravure parfaitement verticale des tranchees. Le remplacement de l'isolation de champ, par oxydation localisee du silicium (locos), par une technique de depots d'oxyde de silicium nivelles (box) necessite la mise au point d'un procede de "planarisation" de l'oxyde. La mise en place de la filiere technologique et la conception des dispositifs de test sont finalement exposees

Esta tese objetiva propor algorítmos para a redução do tamanho dos fios em circuitos VLSI considerando elementos críticos dos circuitos. O problema é abordado em duas perspectivas diferentes: posicionamento e roteamento. Na abordagem de posicionamento, a tese explora métodos para realizar posicionamento de um tipo particular de circuito VLSI, que são conhecidos como circuitos 3D. Diferente de trabalhos anteriores, este tese aborda o problema considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um fluxo completo, iniciando no tratamento de pinos de entrada e saída (E/S), posicionamento global, posicionamento detalhado e posicionamento das 3D-Vias. A primeira etapa espalha os pinos de E/S de maneira equilibrada objetivando auxiliar o posicionamento para obter uma quantidade reduzida de 3D-Vias. O mecanismo de posicionamento global baseado no algorítmo de Quadratic Placement considera informações da tecnologia e requerimento de espaçamento de 3D-Vias para reduzir o comprimento das conexões e equilibrar a distrubuição das células em 3D. Conexes críticas podem ser tratadas através da insercão de redes artificiais que auxiliam a evitar que 3D-Vias sejam usadas em conexões críticas do circuito. Finalmente, 3D-Vias são posicionadas por um algorítmo rápido baseado na legalizaçãao Tetris. O framework completo reforça os potenciais benefícios dos circuitos 3D para a melhora do comprimento das conexões e apresenta algorítmos eficientes projetados para circutos 3D podendo estes serem incorporados em novas ferramentas. Na abordagem de roteamento, um novo algorítmo para obtenção de árvores de Steiner chamado AMAZE é proposto, combinando métodos existentes com novos métodos que são efetivos para produzir fios curtos e de baixo atraso para elementos críticos. Um técnica de biasing atua na redução do tamanho dos fios, obtendo resultados próximos da solução ótima enquanto que dois fatores de timing chamados path-length factor e sharing factor propiciam melhora do atraso para conexões sabidas como críticas. Enquanto que AMAZE apresenta melhorias significativas em um algorítmo padrão na indústria de CAD (Maze Routers), ele produz árvores de roteamento com uso de CPU comparável com algorítmos heurísticos de árvore de Steiner e menor atraso.
This thesis targets the wire length improvement of VLSI circuits considering critical elements of a circuit. It considers the problem from two different perspectives: placement and routing. On placement, it explores methods to perform placement of 3D circuits considering issues related to vertical interconnects (3D-Vias). A complete flow, starting from the I/O pins handling, global placement, detailed placement and 3D-Via placement is presented. The I/O pins algorithm spreads the I/Os evenly and aids the placer to obtain a reduced number of 3D-Vias. The global placement engine based on Quadratic algorithm considers the technology information and 3D-Via pitch to reduce wire length and balance the cells distribution on 3D. Critical connections can be handled by insertion of artificial nets that lead to 3D-Via avoidance for those nets. Finally, 3D-Vias are placed by a fast algorithm based on Tetris legalization. The whole framework enforces the potential benefits of 3DCircuits on wire length improvement and demonstrates efficient algorithms designed for 3D placement that can be incorporated in new tools. On routing, a new flexible Steiner tree algorithm called AMAZE is proposed, combining existing and new methods that are very effective to produce short wire length and low delay to critical elements. A biasing technique provides close to optimal wire lengths while a path length factor and a sharing factor enables a very wide delay and wire length trade-off. While AMAZE presents significant improvements on a industry standard routing algorithm (Maze Routers), it produces routing trees with comparable speed and beter delay than heuristic Steiner tree algorithms such as AHHK and P-Trees.

Description des différentes étapes de la conception d'un microprocesseur pour le contrôle des automatismes de sécurité, en particulier pour les systèmes de transport. Ce microprocesseur est autotestable, c'est-à-dire capable de détecter ses propres erreurs. La conception du circuit est basée sur les hypothèses de pannes au niveau analytique dans la technologie NMOS. Les blocs fonctionnels «Strongly Fault Secure» et les contrôleurs «Strongly Code Disjoint» sont à la base des circuits «Self-checking», dits autotestables. Le circuit COBRA démontre la faisabilité d'un microprocesseur autotestable. COBRA gère indépendamment 19 signaux différents, date des événements externes, mesure des fréquences, surveille 14 entrées logiques et possède 7 sorties indépendantes. Le programme d'application de COBRA est contenu dans une mémoire morte programmable externe de 16 Koctets adressés par 14 bits multiplexés sur le bus interne de 8 bits. COBRA contient également une liaison série, une mémoire à accès direct de 64 octets et 3 temporisateurs de 14 bits indépendants ainsi qu'une unité arithmétique et logique de 8 bits, COBRA exécute un jeu de 43 instructions