Relevant bibliographies by topics / Microprocessors Metal oxide semiconductors, Complementary

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  2. Dissertations / Theses
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Academic literature on the topic 'Microprocessors Metal oxide semiconductors, Complementary'

Author: Grafiati
Published: 4 June 2021
Last updated: 3 February 2022

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Journal articles on the topic "Microprocessors Metal oxide semiconductors, Complementary"

1

Bernstein, Kerry. "Circuit Responses to Radiation-Induced Upsets." MRS Bulletin 28, no. 2 (February 2003): 126–30. http://dx.doi.org/10.1557/mrs2003.40.

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AbstractHistorically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.
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Fitzgerald, E. A., and L. C. Kimerling. "Silicon-Based Microphotonics and Integrated Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 39–47. http://dx.doi.org/10.1557/s0883769400030256.

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The need for integrated optical interconnects in electronic systems is derivedfrom the cost and performance of electronic systems. If we examine the cost of all interconnects, it becomes apparent that there is an exponential growth in cost per interconnect with the length of the interconnect. A remarkable feature of interconnect cost is that the exponential relation holds over all length scales—from the shortest interconnects on a chip to the longest interconnects in global telecommunications networks. Longer interconnects are drastically more expensive, and these costs are ultimately related to the labor cost associated with each interconnect. Given this economic pressure, it is not surprising that there is a driving force to condense more functions locally on the same chip, board, or system. In condensing these functions, the number of long interconnects are decreased and the overall cost of the electronic system decreases dramatically. A specific glaring example of this driving force is Si complementary-metal-oxide-semiconductor (CMOS) technology, especially the case of microprocessors. In the Si microprocessor case, the flood gates to interconnect condensation were opened and the miraculous trend of lower cost for exponentially increasing performance was revealed.
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Nakada, Kazuki, Tetsuya Asai, and Yoshihito Amemiya. "Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller." Journal of Robotics and Mechatronics 16, no. 4 (August 20, 2004): 397–403. http://dx.doi.org/10.20965/jrm.2004.p0397.

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The present paper proposes analog integrated circuit (IC) implementation of a biologically inspired controller in quadruped robot locomotion. Our controller is based on the central pattern generator (CPG), which is known as the biological neural network that generates fundamental rhythmic movements in locomotion of animals. Many CPG-based controllers for robot locomotion have been proposed, but have mostly been implemented in software on digital microprocessors. Such a digital processor operates accurately, but it can only process sequentially. Thus, increasing the degree of freedom of physical parts of a robot deteriorates the performance of a CPG-based controller. We therefore implemented a CPG-based controller in an analog complementary metal-oxide-semiconductor (CMOS) circuit that processes in parallel essentially, making it suitable for real-time locomotion control in a multi-legged robot. Using the simulation program with integrated circuit emphasis (SPICE), we show that our controller generates stable rhythmic patterns for locomotion control in a quadruped walking robot, and change its rhythmic patterns promptly.
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Eaglesham, David J. "What We Still Don't Know About Silicon." MRS Bulletin 19, no. 12 (December 1994): 57–60. http://dx.doi.org/10.1557/s0883769400048739.

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A question sometimes posed to researchers in silicon is: Why are you still working on silicon? How much more do we need to learn? Not only is Si a relatively simple element, it is one of the most common in the earth's crust. This element has been very extensively studied. One reason we keep studying silicon is because it is not just an element, it is also an industry. The microelectronics business has a massive economic impact on our lives. From cars to washing machines, almost all consumer goods contain silicon microprocessors in some form. Our daily lives depend on the stuff. Figure 1 shows the predominance of Si in a breakdown of the microelectronics industry. In 1994 microelectronics has been a $1 × 1011-per year industry worldwide, and it is still growing rapidly. CMOS, or complementary metal-oxide-semiconductor transistors, dominate this business, some being bipolar. The entire compound semiconductor industry is a small part of this picture, composing 2% of the business (although $2 billion is not bad for a “niche” market). The $100 billion business built around silicon makes it the most important element in world economics, although there is some evidence that C and O may also be important for the support of our daily lives. One thing, however, is clear-the economic need to understand silicon and everything it does is tremendous.
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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (October 2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.
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6

John, Vimukth, Shylu Sam, S. Radha, P. Sam Paul, and Joel Samuel. "Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process." Circuit World 46, no. 4 (March 23, 2020): 257–69. http://dx.doi.org/10.1108/cw-12-2018-0104.

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Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.
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7

Toriumi, Akira. "0.1μm complementary metal–oxide–semiconductors and beyond." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 14, no. 6 (November 1996): 4020. http://dx.doi.org/10.1116/1.588635.

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Saha, H., and C. Chaudhuri. "Complementary Metal Oxide Semiconductors Microelectromechanical Systems Integration." Defence Science Journal 59, no. 6 (November 24, 2009): 557–67. http://dx.doi.org/10.14429/dsj.59.1560.

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Wickramasinghe, Thushan E., Gregory Jensen, Ruhi Thorat, Miles Lindquist, Shrouq H. Aleithan, and Eric Stinaff. "Complementary growth of 2D transition metal dichalcogenide semiconductors on metal oxide interfaces." Applied Physics Letters 117, no. 21 (November 23, 2020): 213104. http://dx.doi.org/10.1063/5.0027225.

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Janesick, James. "Lux transfer: Complementary metal oxide semiconductors versus charge-coupled devices." Optical Engineering 41, no. 6 (June 1, 2002): 1203. http://dx.doi.org/10.1117/1.1476692.

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Dissertations / Theses on the topic "Microprocessors Metal oxide semiconductors, Complementary"

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Correll, Jeffrey. "The design and implementation of an 8 bit CMOS microprocessor /." Online version of thesis, 1992. http://hdl.handle.net/1850/11649.

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Al-Ahmadi, Ahmad Aziz. "Complementary orthogonal stacked metal oxide semiconductor a novel nanoscale complementary metal oxide semiconductor architecture /." Ohio : Ohio University, 2006. http://www.ohiolink.edu/etd/view.cgi?ohiou1147134449.

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Gurcan, Zeki B. "0.18 [mu]m high performance CMOS process optimization for manufacturability /." Online version of thesis, 2005. http://hdl.handle.net/1850/5197.

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Wu, Ting. "Design of terabits/s CMOS crossbar switch chip /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WU.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.
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Huang, Amy. "On the plasma induced degradation of organosilicate glass (OSG) as an interlevel dielectric for sub 90 nm CMOS /." Online version of thesis, 2008. http://hdl.handle.net/1850/5899.

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Csutak, Sebastian Marius. "Optical receivers and photodetectors in 130nm CMOS technology." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3036588.

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Hildreth, Scott A. "Statistical SPICE parameter extraction for an N-Well CMOS process /." Online version of thesis, 1995. http://hdl.handle.net/1850/12177.

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Upadhyaya, Parag. "High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver." Online access for everyone, 2005. http://www.dissertations.wsu.edu/Thesis/Spring2005/p%5Fupadhyaya%5F050505.pdf.

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Price, David T. "N-Well CMOS process integration /." Online version of thesis, 1992. http://hdl.handle.net/1850/11261.

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Shum, Roger Chi Fai Carleton University Dissertation Engineering Electrical. "A timing macro model for performance optimization of CMOS logic circuits." Ottawa, 1992.

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Books on the topic "Microprocessors Metal oxide semiconductors, Complementary"

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inc, Motorola. M68HC11 reference manual. Phoenix, Ariz: Motorola, 1990.

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Bernstein, Kerry. SOI circuit design concepts. Boston: Kluwer Academic Publishers, 2000.

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Zhao, Yi. Wafer level reliability of advanced CMOS devices and processes. New York: Nova Science Publishers, 2008.

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Lancaster, Don. CMOS cookbook. 2nd ed. Indianapolis, Ind: H.W. Sams, 1988.

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M, Berlin Howard, ed. CMOS cookbook. 2nd ed. Boston: Newnes, 1997.

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F, Hawkins Charles, ed. CMOS electronics: How it works, how it fails. New York: IEEE Press, 2004.

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Helms, Harry L. High-speed (HC/HCT) CMOS guide. Englewood Cliffs, N.J: Prentice Hall, 1989.

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Kwon, Min-jun. CMOS technology. Hauppauge, N.Y: Nova Science Publishers, 2010.

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Shoji, Masakazu. CMOS digital circuit technology. Englewood Cliffs, N.J: Prentice Hall, 1988.

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Pfaffli, Paul. Characterisation of degradation and failure phenomena in MOS devices. Konstanz [Germany]: Hartung-Gorre, 1999.

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Book chapters on the topic "Microprocessors Metal oxide semiconductors, Complementary"

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Munteanu, Daniela, and Jean-Luc Autran. "Interactions between Terrestrial Cosmic-Ray Neutrons and III–V Compound Semiconductors." In Modeling and Simulation in Engineering - Selected Problems. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.92774.

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This work explores by numerical simulation the impact of high-energy atmospheric neutrons and their interactions with III–V binary compound semiconductors. The efforts have focused on eight III–V semiconductors: GaAs, AlAs, InP, InAs, GaSb, InSb, GaN, and GaP. For each material, extensive Geant4 numerical simulations have been performed considering a bulk target exposed to a neutron source emulating the atmospheric neutron spectrum at terrestrial level. Results emphasize in detail the reaction rates per type of reaction (elastic, inelastic, nonelastic) and offer a classification of all the neutron-induced secondary products as a function of their atomic number, kinetic energy, initial stopping power, and range. Implications for single-event effects (SEEs) are analyzed and discussed, notably in terms of energy and charge deposited in the bulk material and in the first nanometers of particle range with respect to the critical charge for modern complementary metal oxide semiconductor (CMOS) technologies.
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Conference papers on the topic "Microprocessors Metal oxide semiconductors, Complementary"

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Yee, Wai Mun, Mario Paniccia, Travis Eiles, and Valluri Rao. "Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors." In ISTFA 2000. ASM International, 2000. http://dx.doi.org/10.31399/asm.cp.istfa2000p0003.

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Abstract A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.
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Osseily, Hassan Amine, and Ali Massoud Haidar. "Octal to binary conversion using multi-input floating gate complementary metal oxide semiconductors." In 2011 10th International Symposium on Signals, Circuits and Systems (ISSCS). IEEE, 2011. http://dx.doi.org/10.1109/isscs.2011.5978644.

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Osseily, Hassan Amine, and Ali Massoud Haidar. "Hexadecimal to binary conversion using multi-input floating gate complementary metal oxide semiconductors." In 2015 International Conference on Applied Research in Computer Science and Engineering (ICAR). IEEE, 2015. http://dx.doi.org/10.1109/arcse.2015.7338134.

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Gillet, Jean-Numa, Yann Chalopin, and Sebastian Volz. "Atomic-Scale Three-Dimensional Phononic Crystals With a Lower Thermal Conductivity Than the Einstein Limit of Bulk Silicon." In ASME 2008 Heat Transfer Summer Conference collocated with the Fluids Engineering, Energy Sustainability, and 3rd Energy Nanotechnology Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/ht2008-56403.

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Extensive research about superlattices with a very low thermal conductivity was performed to design thermoelectric materials. Indeed, the thermoelectric figure of merit ZT varies with the inverse of the thermal conductivity but is directly proportional to the power factor. Unfortunately, as nanowires, superlattices reduce heat transfer in only one main direction. Moreover, they often show dislocations owing to lattice mismatches. Therefore, fabrication of nanomaterials with a ZT larger than the alloy limit usually fails with the superlattices. Self-assembly is a major epitaxial technology to fabricate ultradense arrays of germaniums quantum dots (QD) in a silicon matrix for many promising electronic and photonic applications as quantum computing. We theoretically demonstrate that high-density three-dimensional (3-D) periodic arrays of small self-assembled Ge nanoparticles (i.e. the QDs), with a size of some nanometers, in Si can show a very low thermal conductivity in the three spatial directions. This property can be considered to design thermoelectric devices, which are compatible with the complementary metal-oxide-semiconductor (CMOS) technologies. To obtain a computationally manageable model of these nanomaterials, we simulate their thermal behavior with atomic-scale 3-D phononic crystals. A phononic-crystal period (supercell) consists of diamond-like Si cells. At each supercell center, we substitute Si atoms by Ge atoms in a given number of cells to form a box-like Ge nanoparticle. The phononic-crystal dispersion curves, which are computed by classical lattice dynamics, are flat compared to those of bulk Si. In an example phononic crystal, the thermal conductivity can be reduced below the value of only 0.95 W/mK or by a factor of at least 165 compared to bulk silicon at 300 K. Close to the melting point of silicon, we obtain a larger decrease of the thermal conductivity below the value of 0.5 W/mK, which is twice smaller than the classical Einstein Limit of single crystalline Si. In this paper, we use an incoherent-scattering approach for the nanoparticles. Therefore, we expect an even larger decrease of the phononic-crystal thermal conductivity when multiple-scattering effects, as multiple reflections and diffusions of the phonons between the Ge nanoparticles, will be considered in a more realistic model. As a consequence of our simulations, a large ZT could be achieved in 3-D ultradense self-assembled Ge nanoparticle arrays in Si. Indeed, these nanomaterials with a very small thermal conductivity are crystalline semiconductors with a power factor that can be optimized by doping using CMOS-compatible technologies, which is not possible with other recently-proposed nanomaterials.
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