Journal articles: 'Microprocessors Metal oxide semiconductors, Complementary'

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Bernstein, Kerry. "Circuit Responses to Radiation-Induced Upsets." MRS Bulletin 28, no. 2 (February 2003): 126–30. http://dx.doi.org/10.1557/mrs2003.40.

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AbstractHistorically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.

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Fitzgerald, E. A., and L. C. Kimerling. "Silicon-Based Microphotonics and Integrated Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 39–47. http://dx.doi.org/10.1557/s0883769400030256.

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The need for integrated optical interconnects in electronic systems is derivedfrom the cost and performance of electronic systems. If we examine the cost of all interconnects, it becomes apparent that there is an exponential growth in cost per interconnect with the length of the interconnect. A remarkable feature of interconnect cost is that the exponential relation holds over all length scales—from the shortest interconnects on a chip to the longest interconnects in global telecommunications networks. Longer interconnects are drastically more expensive, and these costs are ultimately related to the labor cost associated with each interconnect. Given this economic pressure, it is not surprising that there is a driving force to condense more functions locally on the same chip, board, or system. In condensing these functions, the number of long interconnects are decreased and the overall cost of the electronic system decreases dramatically. A specific glaring example of this driving force is Si complementary-metal-oxide-semiconductor (CMOS) technology, especially the case of microprocessors. In the Si microprocessor case, the flood gates to interconnect condensation were opened and the miraculous trend of lower cost for exponentially increasing performance was revealed.

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Nakada, Kazuki, Tetsuya Asai, and Yoshihito Amemiya. "Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller." Journal of Robotics and Mechatronics 16, no. 4 (August 20, 2004): 397–403. http://dx.doi.org/10.20965/jrm.2004.p0397.

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The present paper proposes analog integrated circuit (IC) implementation of a biologically inspired controller in quadruped robot locomotion. Our controller is based on the central pattern generator (CPG), which is known as the biological neural network that generates fundamental rhythmic movements in locomotion of animals. Many CPG-based controllers for robot locomotion have been proposed, but have mostly been implemented in software on digital microprocessors. Such a digital processor operates accurately, but it can only process sequentially. Thus, increasing the degree of freedom of physical parts of a robot deteriorates the performance of a CPG-based controller. We therefore implemented a CPG-based controller in an analog complementary metal-oxide-semiconductor (CMOS) circuit that processes in parallel essentially, making it suitable for real-time locomotion control in a multi-legged robot. Using the simulation program with integrated circuit emphasis (SPICE), we show that our controller generates stable rhythmic patterns for locomotion control in a quadruped walking robot, and change its rhythmic patterns promptly.

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Eaglesham, David J. "What We Still Don't Know About Silicon." MRS Bulletin 19, no. 12 (December 1994): 57–60. http://dx.doi.org/10.1557/s0883769400048739.

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A question sometimes posed to researchers in silicon is: Why are you still working on silicon? How much more do we need to learn? Not only is Si a relatively simple element, it is one of the most common in the earth's crust. This element has been very extensively studied. One reason we keep studying silicon is because it is not just an element, it is also an industry. The microelectronics business has a massive economic impact on our lives. From cars to washing machines, almost all consumer goods contain silicon microprocessors in some form. Our daily lives depend on the stuff. Figure 1 shows the predominance of Si in a breakdown of the microelectronics industry. In 1994 microelectronics has been a $1 × 1011-per year industry worldwide, and it is still growing rapidly. CMOS, or complementary metal-oxide-semiconductor transistors, dominate this business, some being bipolar. The entire compound semiconductor industry is a small part of this picture, composing 2% of the business (although $2 billion is not bad for a “niche” market). The $100 billion business built around silicon makes it the most important element in world economics, although there is some evidence that C and O may also be important for the support of our daily lives. One thing, however, is clear-the economic need to understand silicon and everything it does is tremendous.

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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (October 2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.

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John, Vimukth, Shylu Sam, S. Radha, P. Sam Paul, and Joel Samuel. "Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process." Circuit World 46, no. 4 (March 23, 2020): 257–69. http://dx.doi.org/10.1108/cw-12-2018-0104.

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Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

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Toriumi, Akira. "0.1μm complementary metal–oxide–semiconductors and beyond." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 14, no. 6 (November 1996): 4020. http://dx.doi.org/10.1116/1.588635.

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Saha, H., and C. Chaudhuri. "Complementary Metal Oxide Semiconductors Microelectromechanical Systems Integration." Defence Science Journal 59, no. 6 (November 24, 2009): 557–67. http://dx.doi.org/10.14429/dsj.59.1560.

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Wickramasinghe, Thushan E., Gregory Jensen, Ruhi Thorat, Miles Lindquist, Shrouq H. Aleithan, and Eric Stinaff. "Complementary growth of 2D transition metal dichalcogenide semiconductors on metal oxide interfaces." Applied Physics Letters 117, no. 21 (November 23, 2020): 213104. http://dx.doi.org/10.1063/5.0027225.

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Janesick, James. "Lux transfer: Complementary metal oxide semiconductors versus charge-coupled devices." Optical Engineering 41, no. 6 (June 1, 2002): 1203. http://dx.doi.org/10.1117/1.1476692.

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Lačević, Amela, and Edina Vranić. "Different digital imaging techniques in dental practice." Bosnian Journal of Basic Medical Sciences 4, no. 2 (May 20, 2004): 37–40. http://dx.doi.org/10.17305/bjbms.2004.3412.

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Different imaging techniques are used to pick up the signal of interest in digital sensors, including charge-coupled devices (CCD), complementary metal-oxide semiconductors (CMOS), photostimulable phosphors plates (PSP) and tuned-aperture computed tomography (TACT) Digital radiography sensors are divided into: storage phosphor plates (SPP) called photostimulable phosphor plates (PSP), silicon devices such as charge-coupled devices (CCD) or complementary metal oxide semiconductors (CMOS).Relatively new type of imaging that may hold advantage over current radiographic modalities is tuned-aperture computed tomography (TACT).

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Charbon, E. "Single-photon imaging in complementary metal oxide semiconductor processes." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130100. http://dx.doi.org/10.1098/rsta.2013.0100.

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This paper describes the basics of single-photon counting in complementary metal oxide semiconductors, through single-photon avalanche diodes (SPADs), and the making of miniaturized pixels with photon-counting capability based on SPADs. Some applications, which may take advantage of SPAD image sensors, are outlined, such as fluorescence-based microscopy, three-dimensional time-of-flight imaging and biomedical imaging, to name just a few. The paper focuses on architectures that are best suited to those applications and the trade-offs they generate. In this context, architectures are described that efficiently collect the output of single pixels when designed in large arrays. Off-chip readout circuit requirements are described for a variety of applications in physics, medicine and the life sciences. Owing to the dynamic nature of SPADs, designs featuring a large number of SPADs require careful analysis of the target application for an optimal use of silicon real estate and of limited readout bandwidth. The paper also describes the main trade-offs involved in architecting such chips and the solutions adopted with focus on scalability and miniaturization.

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Balasubramanian, Padmanabhan, Douglas Maskell, and Nikos Mastorakis. "Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic." Electronics 7, no. 10 (October 9, 2018): 243. http://dx.doi.org/10.3390/electronics7100243.

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

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Ker, Ming-Dou, Hsin-Chyh Hsu, and Jeng-Jie Peng. "Novel Implantation Method to Improve Machine-Model Electrostatic Discharge Robustness of Stacked N-Channel Metal-Oxide Semiconductors (NMOS) in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductors (CMOS) Technology." Japanese Journal of Applied Physics 41, Part 2, No. 11B (November 15, 2002): L1288—L1290. http://dx.doi.org/10.1143/jjap.41.l1288.

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Ye, Heqing, Hyeok-Jin Kwon, Xiaowu Tang, Dong Yun Lee, Sooji Nam, and Se Hyun Kim. "Direct Patterned Zinc-Tin-Oxide for Solution-Processed Thin-Film Transistors and Complementary Inverter through Electrohydrodynamic Jet Printing." Nanomaterials 10, no. 7 (July 3, 2020): 1304. http://dx.doi.org/10.3390/nano10071304.

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The solution-processed deposition of metal-oxide semiconducting materials enables the fabrication of large-area and low-cost electronic devices by using printing technologies. Additionally, the simple patterning process of these types of materials become an important issue, as it can simplify the cost and process of fabricating electronics such as thin-film transistors (TFTs). In this study, using the electrohydrodynamic (EHD) jet printing technique, we fabricated directly patterned zinc-tin-oxide (ZTO) semiconductors as the active layers of TFTs. The straight lines of ZTO semiconductors were successfully drawn using a highly soluble and homogeneous solution that comprises zinc acrylate and tin-chloride precursors. Besides, we found the optimum condition for the fabrication of ZTO oxide layers by analyzing the thermal effect in processing. Using the optimized condition, the resulting devices exhibited satisfactory TFT characteristics with conventional electrodes and conducting materials. Furthermore, these metal-oxide TFTs were successfully applied to complementary inverter with conventional p-type organic semiconductor-based TFT, showing high quality of voltage transfer characteristics. Thus, these printed ZTO TFT results demonstrated that solution processable metal-oxide transistors are promising for the realization of a more sustainable and printable next-generation industrial technology.

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Steindl, Bernhard, Reinhard Enne, and Horst Zimmermann. "Thick detection zone single-photon avalanche diode fabricated in 0.35 μ m complementary metal-oxide semiconductors." Optical Engineering 54, no. 5 (May 22, 2015): 050503. http://dx.doi.org/10.1117/1.oe.54.5.050503.

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Schmidt, Jan-Uwe. "Amorphous TiAl films for micromirror arrays with stable analog deflection integrated on complementary metal oxide semiconductors." Journal of Micro/Nanolithography, MEMS, and MOEMS 7, no. 2 (April 1, 2008): 021012. http://dx.doi.org/10.1117/1.2945230.

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Roh, Il Pyo, Sang Hyeon Kim, Yun Heub Song, and Jin Dong Song. "Uniformly strained AlGaSb/InGaSb/AlGaSb quantum well on GaAs substrates for balanced complementary metal-oxide-semiconductors." Current Applied Physics 17, no. 3 (March 2017): 417–21. http://dx.doi.org/10.1016/j.cap.2017.01.003.

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Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.

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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.

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Stemmer, Susanne. "Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal–oxide–semiconductors." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 22, no. 2 (2004): 791. http://dx.doi.org/10.1116/1.1688357.

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Bennett, Brian R., Mario G. Ancona, and J. Brad Boos. "Compound Semiconductors for Low-Power p-Channel Field-Effect Transistors." MRS Bulletin 34, no. 7 (July 2009): 530–36. http://dx.doi.org/10.1557/mrs2009.141.

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AbstractResearch in n-channel field-effect transistors based upon III–V compound semiconductors has been very productive over the last 30 years, with successful applications in a variety of high-speed analog circuits. For digital applications, complementary circuits are desirable to minimize static power consumption. Hence, p-channel transistors are also needed. Unfortunately, hole mobilities are generally much lower than electron mobilities for III–V compounds. This article reviews the recent work to enhance hole mobilities in antimonide-based quantum wells. Epitaxial heterostructures have been grown with the channel material in 1–2% compressive strain. The strain modifies the valence band structure, resulting in hole mobilities as high as 1500 cm2/Vs. The next steps toward an ultra-low-power complementary metal oxide semiconductor technology will include development of a compatible insulator technology and integration of n- and p-channel transistors.

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John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.

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Kalagadda, B., N. Muthyala, and K. K. Korlapati. "Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques." Journal of Engineering Research [TJER] 14, no. 1 (March 1, 2017): 74. http://dx.doi.org/10.24200/tjer.vol14iss1pp74-84.

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Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.

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Radamson, Henry H., Huilong Zhu, Zhenhua Wu, Xiaobin He, Hongxiao Lin, Jinbiao Liu, Jinjuan Xiang, et al. "State of the Art and Future Perspectives in Advanced CMOS Technology." Nanomaterials 10, no. 8 (August 7, 2020): 1555. http://dx.doi.org/10.3390/nano10081555.

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Wang, Xiaochun, Meicheng Fu, Heng Yang, Jiali Liao, and Xiujian Li. "Temperature and Pulse-Energy Range Suitable for Femtosecond Pulse Transmission in Si Nanowire Waveguide." Applied Sciences 10, no. 23 (November 26, 2020): 8429. http://dx.doi.org/10.3390/app10238429.

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We experimentally measured the femtosecond pulse transmission through a silicon-on-insulator (SOI) nanowire waveguide under different temperatures and input pulse energy with a cross-correlation frequency-resolved optical gating (XFROG) measurement setup. The experimental results demonstrated that the temperature and pulse energy dependence of the Si photonic nanowire waveguide (SPNW) is interesting rather than just monotonous or linear, and that the suitable temperature and pulse-energy range is as suggested in this experiment, which will be valuable for analyzing the practical design of the operating regimes and the fine dispersion engineering of various ultrafast photonic applications based on the SPNWs. The research results will contribute to developing the SPNWs with photonic elements and networks compatible with mature complementary metal–oxide–semiconductors (CMOS).

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Marks, Tobin J. "Materials for organic and hybrid inorganic/organic electronics." MRS Bulletin 35, no. 12 (December 2010): 1018–27. http://dx.doi.org/10.1557/mrs2010.707.

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Materials scientists involved in synthesis are exceptionally skilled at designing and constructing individual molecules with the goal of introducing rationally tailored chemical and physical properties. However, the task of assembling such special molecules into organized, supramolecular structures with precise, nanometer-level organizational control to execute specific functions presents a daunting challenge. Soft and hard matter suitable for unconventional types of electronic circuitry represents a case in point and, in principal, offer capabilities not readily achievable with conventional silicon electronics. In this context, “unconventional” means circuitry that can span large areas, can be mechanically flexible and/or optically transparent, can be created by large-scale, high-throughput fabrication techniques, and has atomic-level tunability of properties. In the process of preparing, characterizing, and fabricating prototype devices with such materials, we learn many new things about the electronic and electrical properties of the materials and the interfaces between them. This account briefly overviews recent progress in three interconnected areas: (1) organic semiconductors for complementary π-electron circuits, (2) soft matter high-κ gate dielectrics for organic and inorganic electronics, and (3) metal-oxide semiconductors as components in such devices. Space limitations allow only touching upon selected highlights in this burgeoning field.

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Linardatos, Dionysios, Anastasios Konstantinidis, Ioannis Valais, Konstantinos Ninos, Nektarios Kalyvas, Athanasios Bakas, Ioannis Kandarakis, George Fountos, and Christos Michail. "On the Optical Response of Tellurium Activated Zinc Selenide ZnSe:Te Single Crystal." Crystals 10, no. 11 (October 22, 2020): 961. http://dx.doi.org/10.3390/cryst10110961.

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In this study, the light output of a zinc selenide activated with tellurium (ZnSe: Te) single crystal was measured for X-ray radiography applications. A cubic crystal (10 × 10 × 10 mm) was irradiated using X-rays with tube voltages from 50 to 130 kV. The resulting energy absorption efficiency, detective quantum efficiency, and absolute luminescence efficiency were compared to published data for equally sized GSO: Ce (gadolinium orthosilicate) and BGO (bismuth germanium oxide) crystals. The emitted light was examined to estimate the spectral compatibility with widely used optical sensors. Energy absorption efficiency and detective quantum efficiency of ZnSe: Te and BGO were found to be similar, within the X-ray energies in question. Light output of all three crystals showed a tendency to increase with increasing X-ray tube voltage, but ZnSe: Te stood at least 2 EU higher than the others. ZnSe: Te can be coupled effectively with certain complementary metal–oxide–semiconductors (CMOS), photocathodes, and charge-coupled-devices (CCD), as the effective luminescence efficiency results assert. These properties render the material suitable for various imaging applications, dual-energy arrays included.

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Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.

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Hettick, Mark, Hao Li, Der-Hsien Lien, Matthew Yeh, Tzu-Yi Yang, Matin Amani, Niharika Gupta, Daryl C. Chrzan, Yu-Lun Chueh, and Ali Javey. "Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C." Proceedings of the National Academy of Sciences 117, no. 2 (December 31, 2019): 902–6. http://dx.doi.org/10.1073/pnas.1915786117.

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III–V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III–Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)–coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III–Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics.

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Kotaki, Hiroshi, Masayuki Nakano, Shigeki Hayashida, Seizou Kakimoto, Katsunori Mitsuhashi, and Junkou Takagi. "Novel Oxygen Free Titanium Silicidation (OFS) Processing for Low Resistance and Thermally Stable SALICIDE (Self-Aligned Silicide) in Deep Submicron Dual Gate CMOS (Complementary Metal-Oxide Semiconductors)." Japanese Journal of Applied Physics 34, Part 1, No. 2B (February 28, 1995): 776–81. http://dx.doi.org/10.1143/jjap.34.776.

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Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.

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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.

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Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

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Fuhrer, Michael S., Chun Ning Lau, and Allan H. MacDonald. "Graphene: Materially Better Carbon." MRS Bulletin 35, no. 4 (April 2010): 289–95. http://dx.doi.org/10.1557/mrs2010.551.

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AbstractGraphene, a single atom–thick plane of carbon atoms arranged in a honeycomb lattice, has captivated the attention of physicists, materials scientists, and engineers alike over the five years following its experimental isolation. Graphene is a fundamentally new type of electronic material whose electrons are strictly confined to a two-dimensional plane and exhibit properties akin to those of ultrarelativistic particles. Graphene's two-dimensional form suggests compatibility with conventional wafer processing technology. Extraordinary physical properties, including exceedingly high charge carrier mobility, current-carrying capacity, mechanical strength, and thermal conductivity, make it an enticing candidate for new electronic technologies both within and beyond complementary metal oxide semiconductors (CMOS). Immediate graphene applications include high-speed analog electronics and highly conductive, flexible, transparent thin films for displays and optoelectronics. Currently, much graphene research is focused on generating and tuning a bandgap and on novel device structures that exploit graphene's extraordinary electrical, optical, and mechanical properties.

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Fan, Zhihua, Qinling Deng, Xiaoyu Ma, and Shaolin Zhou. "Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration." Materials 14, no. 5 (March 7, 2021): 1272. http://dx.doi.org/10.3390/ma14051272.

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In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

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Leonardi, Antonio Alessio, Maria José Lo Faro, and Alessia Irrera. "CMOS-Compatible and Low-Cost Thin Film MACE Approach for Light-Emitting Si NWs Fabrication." Nanomaterials 10, no. 5 (May 18, 2020): 966. http://dx.doi.org/10.3390/nano10050966.

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Silicon nanowires (Si NWs) are emerging as an innovative building block in several fields, such as microelectronics, energetics, photonics, and sensing. The interest in Si NWs is related to the high surface to volume ratio and the simpler coupling with the industrial flat architecture. In particular, Si NWs emerge as a very promising material to couple the light to silicon. However, with the standard synthesis methods, the realization of quantum-confined Si NWs is very complex and often requires expensive equipment. Metal-Assisted Chemical Etching (MACE) is gaining more and more attention as a novel approach able to guarantee high-quality Si NWs and high density with a cost-effective approach. Our group has recently modified the traditional MACE approach through the use of thin metal films, obtaining a strong control on the optical and structural properties of the Si NWs as a function of the etching process. This method is Complementary Metal-Oxide-Semiconductors (CMOS)-technology compatible, low-cost, and permits us to obtain a high density, and room temperature light-emitting Si NWs due to the quantum confinement effect. A strong control on the Si NWs characteristics may pave the way to a real industrial transfer of this fabrication methodology for both microelectronics and optoelectronics applications.

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Mizuno, Tomohisa, Naoki Mizoguchi, Kotaro Tanimoto, Tomoaki Yamauchi, Mitsuo Hasegawa, Toshiyuki Sameshima, and Tsutomu Tezuka. "New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices." Japanese Journal of Applied Physics 49, no. 4 (April 20, 2010): 04DC13. http://dx.doi.org/10.1143/jjap.49.04dc13.

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Ellinger, Frank, David Fritsche, Gregor Tretter, Jan Dirk Leufker, Uroschanit Yodprasit, and C. Carta. "Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications." Frequenz 71, no. 1-2 (January 1, 2017): 1–9. http://dx.doi.org/10.1515/freq-2016-0119.

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Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

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Kotaki, Hiroshi, Yoshiyuki Takegawa, Yukiko Mori, Katsunori Mitsuhashi, and Junkou Takagi. "Elevated Polycide Source/Drain Shallow Junctions with Advanced Silicidation Processing and Al Plug/Collimated PVD (Physical Vapor Deposition)-Ti/TiN/Ti/Polycide Contact for Deep-Submicron Complementary Metal-Oxide Semiconductors." Japanese Journal of Applied Physics 33, Part 1, No. 1B (January 30, 1994): 532–40. http://dx.doi.org/10.1143/jjap.33.532.

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Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

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Lopez-Diaz, Daniel, Ingmar Kallfass, Axel Tessmann, Rainer Weber, Hermann Massler, Arnulf Leuther, Michael Schlechtweg, and Oliver Ambacher. "High-performance 60 GHz MMICs for wireless digital communication in 100 nm mHEMT technology." International Journal of Microwave and Wireless Technologies 3, no. 2 (March 3, 2011): 107–13. http://dx.doi.org/10.1017/s1759078711000109.

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Wireless data communication is pushing towards 60 GHz and will most likely be served by SiGe and Complementary Metal Oxide Semiconductor (CMOS) technologies in the consumer market. Nevertheless, some applications are imposing superior performance requirements on the analog frontend, and employing III-V compound semiconductors can provide significant advantages with respect to transmitter power and noise figure. In this paper, we present essential building blocks and a novel single-chip low complexity transceiver Monolithic Microwave Integrated Circuit (MMIC) with integrated antenna switches for 60 GHz communication, fabricated in a 100 nm metamorphic high electron mobility transistor (mHEMT) technology. This technology features a measured noise figure of <2.5 dB in low-noise amplifiers at 60 GHz and the realized medium power amplifiers achieve more than 20 dBm saturated output power. Integrated antenna switches with an insertion loss of less than 1.5 dB enable the integration of the transmit and the receive stages on a single chip. A single-chip transceiver with external subharmonic Local Oscillator (LO) supply for its I/Q down- and up-converter achieves a linear conversion gain in both, the Transmit (Tx) and the Receive (Rx) paths, of more than 10 dB.

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Daus, Alwin, Songyi Han, Stefan Knobelspies, Giuseppe Cantarella, and Gerhard Tröster. "Ge2Sb2Te5 p-Type Thin-Film Transistors on Flexible Plastic Foil." Materials 11, no. 9 (September 9, 2018): 1672. http://dx.doi.org/10.3390/ma11091672.

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In this work, we show the performance improvement of p-type thin-film transistors (TFTs) with Ge 2 Sb 2 Te 5 (GST) semiconductor layers on flexible polyimide substrates, achieved by downscaling of the GST thickness. Prior works on GST TFTs have typically shown poor current modulation capabilities with ON/OFF ratios ≤20 and non-saturating output characteristics. By reducing the GST thickness to 5 nm, we achieve ON/OFF ratios up to ≈300 and a channel pinch-off leading to drain current saturation. We compare the GST TFTs in their amorphous (as deposited) state and in their crystalline (annealed at 200 °C) state. The highest effective field-effect mobility of 6.7 cm 2 /Vs is achieved for 10-nm-thick crystalline GST TFTs, which have an ON/OFF ratio of ≈16. The highest effective field-effect mobility in amorphous GST TFTs is 0.04 cm 2 /Vs, which is obtained in devices with a GST thickness of 5 nm. The devices remain fully operational upon bending to a radius of 6 mm. Furthermore, we find that the TFTs with amorphous channels are more sensitive to bias stress than the ones with crystallized channels. These results show that GST semiconductors are compatible with flexible electronics technology, where high-performance p-type TFTs are strongly needed for the realization of hybrid complementary metal-oxide-semiconductor (CMOS) technology in conjunction with popular n-type oxide semiconductor materials.

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Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (June 22, 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.

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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

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Kaintura, Arun, Kyle Foss, Odysseas Zografos, Ivo Couckuyt, Adrien Vaysset, Tom Dhaene, and Bart Sorée. "Fast Characterization of Input-Output Behavior of Non-Charge-Based Logic Devices by Machine Learning." Electronics 9, no. 9 (August 26, 2020): 1381. http://dx.doi.org/10.3390/electronics9091381.

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Non-charge-based logic devices are promising candidates for the replacement of conventional complementary metal-oxide semiconductors (CMOS) devices. These devices utilize magnetic properties to store or process information making them power efficient. Traditionally, to fully characterize the input-output behavior of these devices a large number of micromagnetic simulations are required, which makes the process computationally expensive. Machine learning techniques have been shown to dramatically decrease the computational requirements of many complex problems. We use state-of-the-art data-efficient machine learning techniques to expedite the characterization of their behavior. Several intelligent sampling strategies are combined with machine learning (binary and multi-class) classification models. These techniques are applied to a magnetic logic device that utilizes direct exchange interaction between two distinct regions containing a bistable canted magnetization configuration. Three classifiers were developed with various adaptive sampling techniques in order to capture the input-output behavior of this device. By adopting an adaptive sampling strategy, it is shown that prediction accuracy can approach that of full grid sampling while using only a small training set of micromagnetic simulations. Comparing model predictions to a grid-based approach on two separate cases, the best performing machine learning model accurately predicts 99.92% of the dense test grid while utilizing only 2.36% of the training data respectively.

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Kuhr, Werner G., Antonio R. Gallo, Robert W. Manning, and Craig W. Rhodine. "Molecular Memories Based on a CMOS Platform." MRS Bulletin 29, no. 11 (November 2004): 838–42. http://dx.doi.org/10.1557/mrs2004.238.

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AbstractHybrid complementary metal oxide semiconductor (CMOS)/molecular memory devices are based on a dynamic random-access memory (DRAM) architecture, are fast, have high density, and exhibit low power consumption. These devices use a well-characterized charge storage mechanism to store information based on the intrinsic properties of molecules attached to a CMOS platform. The molecules are designed in a rational way to have known electrical properties and can be incorporated into CMOS devices with only minor modification of existing fabrication methods. Each memory element contains a monolayer of molecules (typically 100,000–1,000,000) to store charge; this process yields a structure that has many times the charge density of a typical DRAM capacitor, obviating the necessity for a trench or stacked capacitor geometry. The magnitude of voltage required to remove each electron is quantized (typically a few hundred millivolts per state), making it much easier to put molecules in a known state and to detect that state with low-power operation. Existing devices have charge retention times that are >1000 times that of semiconductors, and nonvolatile strategies based on simple modifications of existing systems are possible. All of these devices are ultimately scalable to molecular dimensions and will enable the production of memory products as small as state-of-the-art lithography will allow.

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Ren, Xiaojiao, Ming Zhang, Nicolas Llaser, and Yiqi Zhuang. "On-Chip Measurement of Quality Factor Implemented in 0.35μm CMOS." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650087. http://dx.doi.org/10.1142/s0218126616500870.

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Based on time-domain quality factor (Q-factor) measurement principle, we have proposed an architecture which has the potential to be integrated on-chip. Thanks to the proposed original reconfigurable structure, the main measurement error from the offset of the operational transconductance amplifier (OTA) used can be cancelled automatically during the measurement operation, leading to a high accuracy Q-factor measurement. The digital control circuit plays an important role in the automatic passage between the two configurations designed, i.e., peak detector and comparator. The main advantages of the proposed time-domain Q-factor measurement lay on the possibility of being integrated next to the Micro Electro Mechanical System (MEMS) resonator to be measured, the miniaturization of the whole measuring system as well as the enhancement of the measurement performance, and to guide the design of such architecture, a theoretical analysis linking the required accuracy and the given Q-factor to the circuit parameters have been given in this paper. The proposed circuit is designed and simulated in a 0.35[Formula: see text][Formula: see text]m Complementary Metal Oxide Semiconductors (CMOS) technology. The post-layout simulation results show that the operating frequency can reach up to 200[Formula: see text]kHz with an accuracy of 0.4%.

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Saggese, Gerardo, Mattia Tambaro, Elia A. Vallicelli, Antonio G. M. Strollo, Stefano Vassanelli, Andrea Baschirotto, and Marcello De Matteis. "Comparison of Sneo-Based Neural Spike Detection Algorithms for Implantable Multi-Transistor Array Biosensors." Electronics 10, no. 4 (February 8, 2021): 410. http://dx.doi.org/10.3390/electronics10040410.

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Real-time neural spike detection is an important step in understanding neurological activities and developing brain-silicon interfaces. Recent approaches exploit minimally invasive sensing techniques based on implanted complementary metal-oxide semiconductors (CMOS) multi transistors arrays (MTAs) that limit the damage of the neural tissue and provide high spatial resolution. Unfortunately, MTAs result in low signal-to-noise ratios due to the weak capacitive coupling between the nearby neurons and the sensor and the high noise power coming from the analog front-end. In this paper we investigate the performance achievable by using spike detection algorithms for MTAs, based on some variants of the smoothed non-linear energy operator (SNEO). We show that detection performance benefits from the correlation of the signals detected by the MTA pixels, but degrades when a high firing rate of neurons occurs. We present and compare different approaches and noise estimation techniques for the SNEO, aimed at increasing the detection accuracy at low SNR and making it less dependent on neurons firing rates. The algorithms are tested by using synthetic neural signals obtained with a modified version of NEUROCUBE generator. The proposed approaches outperform the SNEO, showing a more than 20% increase on averaged sensitivity at 0 dB and reduced dependence on the neuronal firing rate.

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Kim, Hyung-Il, and Seok Bong Yoo. "Trends in Super-High-Definition Imaging Techniques Based on Deep Neural Networks." Mathematics 8, no. 11 (October 31, 2020): 1907. http://dx.doi.org/10.3390/math8111907.

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Images captured by cameras in closed-circuit televisions and black boxes in cities have low or poor quality owing to lens distortion and optical blur. Moreover, actual images acquired through imaging sensors of cameras such as charge-coupled devices and complementary metal-oxide-semiconductors generally include noise with spatial-variant characteristics that follow Poisson distributions. If compression is directly applied to an image with such spatial-variant sensor noises at the transmitting end, complex and difficult noises called compressed Poisson noises occur at the receiving end. The super-high-definition imaging technology based on deep neural networks improves the image resolution as well as effectively removes the undesired compressed Poisson noises that may occur during real image acquisition and compression as well as in transmission and reception systems. This solution of using deep neural networks at the receiving end to solve the image degradation problem can be used in the intelligent image analysis platform that performs accurate image processing and analysis using high-definition images obtained from various camera sources such as closed-circuit televisions and black boxes. In this review article, we investigate the current state-of-the-art super-high-definition imaging techniques in terms of image denoising for removing the compressed Poisson noises as well as super-resolution based on the deep neural networks.

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Cherivirala, Y. K., H. Lyu, H. A. Alhowri, and A. Babakhani. "Wirelessly Powered Microchips for Mapping Hydraulic Fractures." SPE Journal 24, no. 04 (March 11, 2019): 1830–38. http://dx.doi.org/10.2118/194491-pa.

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Summary The onset of the era of internet of things and artificial intelligence comes with the ever-growing demand for self-sustaining and efficient sensors. Sensors based on complementary metal oxide semiconductors (CMOSs) have attracted significant attention in the implementation of distributed sensor systems for a vast number of applications because of their economical and complex integration benefits. In this work, we report CMOS-based energy-harvesting chips as wireless nodes for mapping hydraulic fractures during the shale gas extraction process. The CMOS chips are tested in a custom benchtop core-holder chamber that emulates a downhole environment. An induction coil, sized at 5 × 5 mm, connected to a custom CMOS chip, is used as a receiver inside the core holder to harvest electromagnetic (EM) energy transmitted by an external antenna. On the basis of the custom core-holder experiment, it is shown that encapsulated CMOS chips are able to harvest EM energy and thereby operate wirelessly. The receiver has a resonance frequency of 198 MHz. The CMOS chip is equipped with an integrated power management unit (PMU), energy-harvesting unit, and a signal-generation block. The CMOS chip inside the chamber produces an output signal with a frequency proportional to the harvested power. By measuring the frequency of the output signal produced by the chip, we are able to localize the chips within the rock inside the custom core holder.

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Ramesh, Tatapudi, Gurugubelli Upendra, Bandaru Sravani Krishna, Sahithi Dathar, Priyankesh Sinha, Raghavendra M.N, Myla Swathi, and K. Roja Vara Lakshmi. "A comparative study to diagnose the accuracy of E-speed film, complimentary metal oxide semiconductor and storage phosphor systems in the detection of proximal caries: An in vitro study." International Journal of Dental Research 4, no. 1 (January 24, 2016): 1. http://dx.doi.org/10.14419/ijdr.v4i1.5717.

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Background: Dental caries is one of the most commonly encountered conditions in clinical dentistry and these lesions remain undetected when confined to the vicinity of inter-proximal surfaces. Radiography plays a key role in the detection of inter-proximal caries especially in tight contacts.Objectives: The purpose of this study was to compare the diagnostic accuracy of E-speed film, complementary metal oxide semiconductors (CMOS) and storage phosphor systems (PSP) in the detection of proximal caries of the posterior teeth.Methods: Conventional films, CMOS and PSP images were used in detecting proximal caries on mesial and distal surfaces of 63 teeth (126 surfaces). Interpretation of all digital and conventional radiographs were performed and reanalyzed by four observers. The collected data was subjected to statistical analysis using chi square test, weighed kappa statistics and spearman rank correlation coefficient.Results: The PSP images showed more accurate results in identifying normal tooth, enamel caries, dentinal caries and deep dental caries and kappa statistics had represented almost perfect reading of 0.8 – 0.9 for PSP images whereas CMOS images showed substantial reading of 0.6 – 0.7, and for IOPA images it showed moderate reading of 0.5 – 0.6, which stated that the higher inter-observer agreement was obtained for PSP images when compared with images taken by IOPA and CMOS. The intra-observer reliability by kappa statistics had shown highly significant value (0.82) in the present study.Conclusion: Conventional films, CMOS and PSP images had shown almost appropriate results in the detection of proximal caries but PSP receptors were better in disclosing the details more accurately in terms of delineating the actual extent of the lesion pertaining to their high resolution capacity and further their flexibility made them easier during handling the radiograph, when compared with that of rigid CMOS receptors.

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Garg, Sandeep, and Tarun Kumar Gupta. "A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET." Circuit World ahead-of-print, ahead-of-print (July 23, 2020). http://dx.doi.org/10.1108/cw-09-2019-0128.

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Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

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Journal articles on the topic 'Microprocessors Metal oxide semiconductors, Complementary'

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